Skip to content

Y
yosys-tests
Commit 9c8c9592 by SergeyDegtyar
Options

Review 'simple' test group

parent c0b775eb
Showing with 8517 additions and 0 deletions
simple_reviewed/.gitignore 0 → 100644
*/work_*/
/.stamp
/run-test.mk
simple_reviewed/Makefile 0 → 100644
PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
all::
run-test.mk: ../generate.py
@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
include run-test.mk
.PHONY: all clean
simple_reviewed/aigmap/aigmap.ys 0 → 100644
read_verilog ../top.v
tee -o result1.out dump
aigmap
tee -o result.out dump
proc
aigmap
synth -top top
aigmap
simple_reviewed/aigmap/aigmap_nand.ys 0 → 100644
read_verilog ../top.v
tee -o result1.out dump
aigmap -nand
tee -o result.out dump
proc
aigmap -nand
synth -top top
aigmap -nand
simple_reviewed/aigmap/aigmap_select.ys 0 → 100644
read_verilog ../top.v
tee -o result1.out dump
aigmap -select
tee -o result.out dump
proc
aigmap -select
synth -top top
simple_reviewed/aigmap/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
reg Y;
wire[3:0] S;
wire[15:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
8 : Y = D[8];
9 : Y = D[9];
10 : Y = D[10];
11 : Y = D[11];
12 : Y = D[12];
13 : Y = D[13];
14 : Y = D[14];
15 : Y = D[15];
endcase
end
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
simple_reviewed/alu/gates.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -g gates
stat
select -assert-count 98 t:$_ANDNOT_
select -assert-count 465 t:$_AND_
select -assert-count 32 t:$_DFF_P_
select -assert-count 786 t:$_NAND_
select -assert-count 43 t:$_NOR_
select -assert-count 3 t:$_NOT_
select -assert-count 92 t:$_ORNOT_
select -assert-count 257 t:$_OR_
select -assert-count 18 t:$_XNOR_
select -assert-count 26 t:$_XOR_
simple_reviewed/alu/luts.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 4
stat
select -assert-count 32 t:$_DFF_P_
select -assert-count 689 t:$lut
simple_reviewed/alu/top.v 0 → 100644
module top (
input clock,
input [31:0] dinA, dinB,
input [2:0] opcode,
output reg [31:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule
simple_reviewed/async2sync/async2sync.ys 0 → 100644
read_verilog ../top.v
proc
select -assert-count 2 t:$dffsr
async2sync
select -assert-none t:$dffsr
simple_reviewed/async2sync/async2sync_latch.ys 0 → 100644
read_verilog ../top_latch.v
proc
select -assert-count 4 t:$dlatch
async2sync
select -assert-none t:$dlatch
simple_reviewed/async2sync/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/async2sync/top_latch.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple_reviewed/attrmap/attrmap.ys 0 → 100644
read_verilog ../top.v
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
proc
tee -o result1.out dump
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
tee -o result.out dump
simple_reviewed/attrmap/attrmap_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result1.out dump
attrmap -tocase keep -remove keep="true"
tee -o result.out dump
simple_reviewed/attrmap/attrmap_modattr.ys 0 → 100644
read_verilog ../top.v
proc
attrmap -modattr -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0 -rename keep keep_attr
tee -o result.out dump
simple_reviewed/attrmap/top.v 0 → 100644
module top (en, a, b);
input en;
input a;
output reg b;
(* keep = "true" *) wire int_dat;
always @(en or a)
b <= (en)? a : 1'bZ;
endmodule
simple_reviewed/clk2fflogic/clk2fflogic.ys 0 → 100644
read_verilog ../top.v
proc
select -assert-any t:$dffsr
select -assert-any t:$dff
select -assert-any t:$adff
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dffsr
select -assert-none t:$dff
select -assert-none t:$adff
select -assert-any t:$ff
simple_reviewed/clk2fflogic/clk2fflogic_latch.ys 0 → 100644
read_verilog ../top_latch.v
proc
select -assert-any t:$dlatch
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dlatch
select -assert-any t:$ff
simple_reviewed/clk2fflogic/clk2fflogic_mem.ys 0 → 100644
read_verilog ../top_mem.v
memory_collect
proc
select -assert-any t:$dff
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dff
select -assert-any t:$ff
simple_reviewed/clk2fflogic/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/clk2fflogic/top_latch.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple_reviewed/clk2fflogic/top_mem.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/design_import/design_import.ys 0 → 100644
read_verilog ../top.v
proc
design -save top
design -import top
write_verilog synth.v
simple_reviewed/design_import/design_import_as.ys 0 → 100644
read_verilog ../top.v
proc
design -save top
design -import top -as top_new
write_verilog synth.v
simple_reviewed/design_import/top.v 0 → 100644
module top
(
input [7:0] x,
output o_and,
output o_or,
output o_xor,
output o_nand,
output o_nor,
output o_xnor
);
assign o_and = &x;
assign o_or = |x;
assign o_xor = ^x;
assign o_nand = ~&x;
assign o_nor = ~|x;
assign o_xnor = ~^x;
endmodule
simple_reviewed/dff2dffe/dff2dffe_error_fail.pat 0 → 100644
ERROR: No cell types matched pattern '$ff'.
simple_reviewed/dff2dffe/dff2dffe_error_fail.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe -direct-match $ff
simple_reviewed/dff2dffe/dff2dffe_unmap.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap
tee -o result.log dump
synth -top top
dff2dffe
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
tee -o result.log dump
synth -top top
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_direct_match.ys 0 → 100644
read_verilog ../top.v
proc
synth -top top
dff2dffe -direct-match $_DFF_P_
dff2dffe -unmap
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/dff2dffe_unmap_mince.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap-mince 2
tee -o result.log dump
synth -top top
dff2dffe
dff2dffe -unmap-mince 2
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/dff2dffe/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/dff2dffs/dff2dffs.ys 0 → 100644
read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs
select -assert-none t:$_DFF_N_
tee -o result.out stat
simple_reviewed/dff2dffs/dff2dffs_match_init.ys 0 → 100644
read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs -match-init
tee -o result.out stat
simple_reviewed/dff2dffs/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffs
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffns
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/dffsr2dff/dffsr2dff.ys 0 → 100644
read_verilog ../top.v
proc
dffsr2dff
techmap
dffsr2dff
design -reset
read_verilog ../top.v
synth -top top
dffsr2dff
flatten
opt
opt_rmdff
dffsr2dff
write_verilog synth.v
simple_reviewed/dffsr2dff/top.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffsr u_dffsr (
.clk (clk ),
.clr (1'b1),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/expose/expose_cut.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -cut
write_verilog synth.v
simple_reviewed/expose/expose_dff.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dff.ys 0 → 100644
read_verilog ../top_dff.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_dff_dffr.ys 0 → 100644
read_verilog ../top_dffr.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple_reviewed/expose/expose_evert.ys 0 → 100644
read_verilog ../top.v
expose -evert
synth -top top
expose -evert
proc
expose -evert
flatten
opt
opt_rmdff
expose -evert
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff.ys 0 → 100644
read_verilog ../top.v
proc
expose -evert-dff
synth -top top
expose -evert-dff
proc
flatten
opt
opt_rmdff
expose -evert-dff
write_verilog synth.v
simple_reviewed/expose/expose_evert_dff_shared.ys 0 → 100644
read_verilog ../top.v
proc
expose -evert-dff -shared
synth -top top
proc
flatten
opt
opt_rmdff
expose -evert-dff
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/expose/expose_evert_shared.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -evert -shared
expose -shared -evert
write_verilog synth.v
simple_reviewed/expose/expose_input.ys 0 → 100644
read_verilog ../top.v
synth -top top
expose -input
proc
flatten
opt
opt_rmdff
expose -input
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/expose/expose_sep.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -sep |
write_verilog synth.v
simple_reviewed/expose/expose_shared.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -shared
write_verilog synth.v
simple_reviewed/expose/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/expose/top_dff.v 0 → 100644
module dff
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk (clk),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/expose/top_dffr.v 0 → 100644
module dffr
( input d, clk, rst, output reg q );
always @( posedge clk )
if ( rst )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffr u_dffr (
.clk (clk),
.rst (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/extract/extract_args_to_perm_fail.pat 0 → 100644
ERROR: Arguments to -perm are not a valid permutation!
simple_reviewed/extract/extract_args_to_perm_fail.ys 0 → 100644
read_verilog ../top.v
extract -map top.v -perm u x u
simple_reviewed/extract/extract_cant_open_output_fail.ys 0 → 100644
read_verilog ../top.v
extract -mine tt/out
simple_reviewed/extract/extract_cell_attr.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -cell_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_compat.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -compat $dff a
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_constports.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -constports
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_param.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -ignore_param $dff param
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_ignore_parameters.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -ignore_parameters
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_map_and_mine_fail.pat 0 → 100644
ERROR: You cannot mix -map and -mine.
simple_reviewed/extract/extract_map_and_mine_fail.ys 0 → 100644
read_verilog ../top.v
extract -map top.v -mine out.ilang
simple_reviewed/extract/extract_map_design.ys 0 → 100644
read_verilog ../top.v
design -save top_test
extract -map %top_test
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_mine.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang
write_verilog synth.v
simple_reviewed/extract/extract_mine_and_map_fail.pat 0 → 100644
ERROR: You cannot mix -map and -mine.
simple_reviewed/extract/extract_mine_and_map_fail.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -map top.v
simple_reviewed/extract/extract_mine_cells_span.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_cells_span 3 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_limit_matches_per_module.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_limit_matches_per_module 5
write_verilog synth.v
simple_reviewed/extract/extract_mine_max_fanout.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_max_fanout 2
write_verilog synth.v
simple_reviewed/extract/extract_mine_min_freq.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_min_freq 10
write_verilog synth.v
simple_reviewed/extract/extract_mine_split.ys 0 → 100644
read_verilog ../top.v
extract -mine out.ilang -mine_split 2 2
write_verilog synth.v
simple_reviewed/extract/extract_missing_opt_fail.pat 0 → 100644
ERROR: Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.
simple_reviewed/extract/extract_nodefaultswaps.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -nodefaultswaps
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_perm.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -perm $dff D,CLK D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_swap.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -swap $dff D,CLK
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_verbose.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -verbose
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/extract_wire_attr.ys 0 → 100644
read_verilog ../top.v
extract -map ../top.v -wire_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple_reviewed/extract/out 0 → 100644
# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
autoidx 1
simple_reviewed/extract/top.ilang 0 → 100644
# Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC)
autoidx 143
simple_reviewed/extract/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/extract_counter/extract_counter.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_down.ys 0 → 100644
read_verilog ../top_down.v
synth_greenpak4
extract_counter
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_maxwidth.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
extract_counter -maxwidth 4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
extract_counter -pout X
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/extract_counter/extract_counter_pout_without_args_fail.ys 0 → 100644
read_verilog ../top_err.v
synth_greenpak4
extract_counter -pout
design -reset
read_verilog ../top_err.v
write_verilog synth.v
simple_reviewed/extract_counter/top.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
endmodule
simple_reviewed/extract_counter/top_down.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b11111111;
end else
out <= out - 1;
endmodule
simple_reviewed/extract_counter/top_err.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
//FORCE
endmodule
simple_reviewed/extract_counter/top_negative_reset.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (!reset) begin
out <= 8'b00000000;
end else
out <= out + 1;
endmodule
simple_reviewed/extract_counter/top_no_reset.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
initial out <= 0 ;
always @(posedge clk)
out <= out + 1;
endmodule
simple_reviewed/extract_counter/top_sync_reset.v 0 → 100644
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
endmodule
simple_reviewed/flowmap/flowmap.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap
select -assert-any t:$lut
write_verilog synth.v
simple_reviewed/flowmap/flowmap_cells.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -cells $dff top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_debug.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -debug top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_debug_relax.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -debug-relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_ffs.ys 0 → 100644
read_verilog ../top_ffs.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_latch.ys 0 → 100644
read_verilog ../top_latch.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_maxlut.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -maxlut 4 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_minlut.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -minlut 2 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_optarea.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -optarea 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_alpha.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -r-alpha 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_beta.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -r-beta 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_r_gamma.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -r-gamma 3 top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax_debug.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -relax -debug top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_relax_debug_relax.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap -relax -debug-relax top
write_verilog synth.v
simple_reviewed/flowmap/flowmap_top.ys 0 → 100644
read_verilog ../top.v
synth -top top
flowmap top
write_verilog synth.v
simple_reviewed/flowmap/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/flowmap/top_ffs.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/flowmap/top_latch.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple_reviewed/fsm/fsm.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt
fsm_opt
select -assert-count 1 t:$fsm
tee -o result.out dump
simple_reviewed/fsm/fsm_opt.ys 0 → 100644
read_verilog ../top_opt.v
proc
fsm_detect
fsm_extract
opt
fsm_opt
select -assert-count 1 t:$fsm
tee -o result.out dump
simple_reviewed/fsm/fsm_unreach.ys 0 → 100644
read_verilog ../top_unreach.v
proc
fsm_detect
fsm_extract
opt
fsm_opt
select -assert-count 1 t:$fsm
tee -o result.out dump
simple_reviewed/fsm/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple_reviewed/fsm/top_opt.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
input [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
simple_reviewed/fsm/top_unreach.v 0 → 100644
module top(clk, rst, a, b, c, x, y, z);
input clk, rst;
input [4:0] a;
input [4:0] b;
input [4:0] c;
output reg [4:0] x;
output reg [4:0] y;
output reg [4:0] z;
reg [3:0] state;
always @(posedge clk) begin
if (rst) begin
x <= 1;
y <= 2;
z <= 3;
state <= 1;
end else begin
case (state)
1: begin
x <= x;
y <= b;
z <= 1;
end
2: begin
x <= a;
y <= c;
z <= c;
if ((x) < (5'd3)) state <= 4;
if ((y) < (5'd3)) state <= 3;
end
3: begin
x <= y;
y <= a;
z <= y;
state <= 1;
end
4: begin
x <= b;
y <= 5'd1;
z <= 5'd2;
end
5: begin
x <= 5'd1;
y <= 5'd2;
z <= z;
end
6: begin
x <= 5'd1;
y <= 5'd2;
z <= z;
end
endcase
end
end
endmodule
simple_reviewed/fsm_command/fsm_command.ys 0 → 100644
read_verilog ../top.v
proc
fsm
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command_expand.ys 0 → 100644
read_verilog ../top.v
proc
fsm -expand
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_command_export.ys 0 → 100644
read_verilog ../top.v
proc
fsm -export
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encfile.ys 0 → 100644
read_verilog ../top.v
proc
fsm -encfile fsm.fsm
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_auto.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binary
fsm_map
fsm
fsm -encoding binary
fsm -encoding auto
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_binary.ys 0 → 100644
read_verilog ../top.v
proc
fsm -encoding binary
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_none.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binary
fsm_map
fsm
fsm -encoding binary
fsm -encoding none
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_one-hot.ys 0 → 100644
read_verilog ../top.v
proc
fsm -encoding one-hot
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_unknown.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binary
fsm_map
fsm
fsm -encoding binary
fsm -encoding unknown
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_encoding_user.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binary
fsm_map
fsm
fsm -encoding binary
fsm -encoding user
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_fm_set_fsm_file.ys 0 → 100644
read_verilog ../top.v
proc
fsm -fm_set_fsm_file file.file
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_fullexpand.ys 0 → 100644
read_verilog ../top.v
proc
fsm -fullexpand
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_nodetect.ys 0 → 100644
read_verilog ../top.v
proc
fsm -nodetect
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_nomap.ys 0 → 100644
read_verilog ../top.v
proc
fsm -nomap
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/fsm_norecode.ys 0 → 100644
read_verilog ../top.v
proc
fsm -norecode
stat
synth -top top
write_verilog synth.v
simple_reviewed/fsm_command/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple_reviewed/fsm_expand/fsm_expand.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_expand
opt
fsm_opt
select -assert-count 1 t:$fsm
simple_reviewed/fsm_expand/fsm_expand_full.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_expand -full
opt
fsm_opt
select -assert-count 1 t:$fsm
simple_reviewed/fsm_expand/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple_reviewed/fsm_export/fsm_export.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_export
opt
fsm_opt
select -assert-count 1 t:$fsm
simple_reviewed/fsm_export/fsm_export_couldnt_open_file_fail.pat 0 → 100644
ERROR: Could not open file "tt/fsm.kiss2" with write access.
simple_reviewed/fsm_export/fsm_export_couldnt_open_file_fail.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_export -o tt/fsm.kiss2
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_export/fsm_export_noauto.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_export -noauto
opt
fsm_opt
select -assert-count 1 t:$fsm
simple_reviewed/fsm_export/fsm_export_o.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_export -o fsm.kiss2
opt
fsm_opt
select -assert-count 1 t:$fsm
simple_reviewed/fsm_export/fsm_export_origenc.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_export -origenc
opt
fsm_opt
select -assert-count 1 t:$fsm
simple_reviewed/fsm_export/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple_reviewed/fsm_recode/fsm_recode.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_all_opt.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binary -fm_set_fsm_file file.file -encfile file.fsm
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_cant_open_encfile_fail.pat 0 → 100644
ERROR: Can't open encfile `tt/file.fsm' for writing: No such file or directory
simple_reviewed/fsm_recode/fsm_recode_cant_open_encfile_fail.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encfile tt/file.fsm
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_cant_open_fm_set_fsm_file_fail.pat 0 → 100644
ERROR: Can't open fm_set_fsm_file `tt/file.file' for writing: No such file or directory
simple_reviewed/fsm_recode/fsm_recode_cant_open_fm_set_fsm_file_fail.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -fm_set_fsm_file tt/file.file
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encfile.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encfile file.fsm
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_binary.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binary
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_binary_twice.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binary
fsm_recode -encoding binary
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_isnt_supported_fail.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding binari
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_encoding_one_hot.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -encoding one-hot
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/fsm_recode_fm_set_fsm_file.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
fsm_recode -fm_set_fsm_file file.file
opt
fsm_opt
select -assert-count 1 t:$fsm
synth -top top
write_verilog synth.v
simple_reviewed/fsm_recode/top.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple_reviewed/full_adder/full_adder.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_fa -fa -v
select -assert-count 1 t:$fa
simple_reviewed/full_adder/full_adder_b.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_fa -fa -b 12 top
select -assert-count 1 t:$fa
simple_reviewed/full_adder/full_adder_cascade.ys 0 → 100644
read_verilog ../top_cascade.v
synth -top top
extract_fa -fa -v
stat
select -assert-count 2 t:$fa
simple_reviewed/full_adder/full_adder_d.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_fa -fa -d 6 top
select -assert-count 1 t:$fa
simple_reviewed/full_adder/full_adder_invert.ys 0 → 100644
read_verilog ../top_invert.v
synth -top top
extract_fa -fa -v
select -assert-count 1 t:$fa
simple_reviewed/full_adder/full_adder_wo_opt.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_fa
select -assert-count 3 t:$fa
simple_reviewed/full_adder/half_adder.ys 0 → 100644
read_verilog ../top.v
proc
synth -top top
extract_fa -ha -v
select -assert-count 2 t:$fa
simple_reviewed/full_adder/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
assign {cout,A} = cin + y + x;
endmodule
simple_reviewed/full_adder/top_cascade.v 0 → 100644
module top
(
input x0,x1,
input y0,y1,
input cin,
output A0,A1,
output cout
);
wire cout0;
assign {cout0,A0} = cin + y0 + x0;
assign {cout,A1} = cout0 + y1 + x1;
endmodule
simple_reviewed/full_adder/top_invert.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
assign {cout,A} = ~(cin + y + x);
endmodule
simple_reviewed/hierarchy/hierarchy.ys 0 → 100644
read_verilog ../top.v
hierarchy
proc
hierarchy
opt
hierarchy
synth -top top
hierarchy
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_auto_top.ys 0 → 100644
read_verilog ../top.v
hierarchy -auto-top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_check.ys 0 → 100644
read_verilog ../top.v
hierarchy -check -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_chparam.ys 0 → 100644
read_verilog ../top.v
hierarchy -chparam x 1 -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_chparam_overwr.ys 0 → 100644
read_verilog ../top.v
hierarchy -chparam x 1 -chparam x 2 -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_generate.ys 0 → 100644
read_verilog ../top.v
hierarchy -generate dff adff adffn i@1:i o@2:o io@3:io
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_huge.ys 0 → 100644
read_verilog ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/SimDTM.v
proc
hierarchy -generate -check -simcheck -purge_lib -keep_positionals -keep_portwidths -nokeep_asserts -auto-top
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_keep_portwidths.ys 0 → 100644
read_verilog ../top.v
hierarchy -keep_portwidths -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_keep_positionals.ys 0 → 100644
read_verilog ../top.v
hierarchy -keep_positionals -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_libdir.ys 0 → 100644
read_verilog ../top.v
hierarchy -libdir libdir -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_module_not_found_fail.ys 0 → 100644
read_verilog ../top.v
hierarchy -top uu
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_no_top_module_fail.ys 0 → 100644
hierarchy -simcheck
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_nokeep_asserts.ys 0 → 100644
read_verilog ../top.v
hierarchy -nokeep_asserts -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_purge_lib.ys 0 → 100644
read_verilog ../top.v
hierarchy -purge_lib -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_simcheck.ys 0 → 100644
read_verilog ../top.v
hierarchy -simcheck -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_top.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/hierarchy_top_requires_args_fail.pat 0 → 100644
ERROR: Option -top requires an additional argument!
simple_reviewed/hierarchy/hierarchy_top_requires_args_fail.ys 0 → 100644
read_verilog ../top.v
hierarchy -top
synth -top top
write_verilog synth.v
simple_reviewed/hierarchy/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module adff
( inout d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
parameter S=0;
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
parameter Z=1'bZ;
initial begin
q = Z;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( d, clk, pre, clr, q );
parameter s=2;
parameter l=1;
input [s-1:l] d;
input clk, pre, clr;
output reg [s-1:l] q;
initial begin
q = 2'b11;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 2'b00;
else if ( !pre )
q <= 2'b11;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
wire a1,b11;
parameter x = 0;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr #(4) u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d ({a,a1} ),
.q ({b1,b11} )
);
defparam u_ndffnsnr.l = 0;
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/hierarchy/yosys_rocket/AsyncResetReg.v 0 → 100644
// See LICENSE.SiFive for license details.
/** This black-boxes an Async Reset
* Reg.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/reset.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
module AsyncResetReg (d, q, en, clk, rst);
parameter RESET_VALUE = 0;
input wire d;
output reg q;
input wire en;
input wire clk;
input wire rst;
// There is a lot of initialization
// here you don't normally find in Verilog
// async registers because of scenarios in which reset
// is not actually asserted cleanly at time 0,
// and we want to make sure to properly model
// that, yet Chisel codebase is absolutely intolerant
// of Xs.
`ifndef SYNTHESIS
initial begin
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
_RAND = {1{$random}};
q = _RAND[0];
`endif // RANDOMIZE
if (rst) begin
q = RESET_VALUE;
end
end
`endif
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= RESET_VALUE;
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg
simple_reviewed/hierarchy/yosys_rocket/EICG_wrapper.v 0 → 100644
/* verilator lint_off UNOPTFLAT */
module EICG_wrapper(
output out,
input en,
input in
);
reg en_latched /*verilator clock_enable*/;
always @(en or in) begin
if (!in) begin
en_latched = en;
end
end
assign out = en_latched && in;
endmodule
simple_reviewed/hierarchy/yosys_rocket/SimDTM.v 0 → 100644
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
/*
import "DPI-C" function int debug_tick
(
output bit debug_req_valid,
input bit debug_req_ready,
output int debug_req_bits_addr,
output int debug_req_bits_op,
output int debug_req_bits_data,
input bit debug_resp_valid,
output bit debug_resp_ready,
input int debug_resp_bits_resp,
input int debug_resp_bits_data
);
*/
module SimDTM(
input clk,
input reset,
output debug_req_valid,
input debug_req_ready,
output [ 6:0] debug_req_bits_addr,
output [ 1:0] debug_req_bits_op,
output [31:0] debug_req_bits_data,
input debug_resp_valid,
output debug_resp_ready,
input [ 1:0] debug_resp_bits_resp,
input [31:0] debug_resp_bits_data,
output [31:0] exit
);
assign debug_req_valid = 0;
assign debug_req_bits_addr = 0;
assign debug_req_bits_op = 0;
assign debug_req_bits_data = 0;
assign debug_resp_ready = 0;
assign exit = 0;
/*
bit r_reset;
wire #0.1 __debug_req_ready = debug_req_ready;
wire #0.1 __debug_resp_valid = debug_resp_valid;
wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp};
wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data;
bit __debug_req_valid;
int __debug_req_bits_addr;
int __debug_req_bits_op;
int __debug_req_bits_data;
bit __debug_resp_ready;
int __exit;
assign #0.1 debug_req_valid = __debug_req_valid;
assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
assign #0.1 debug_resp_ready = __debug_resp_ready;
assign #0.1 exit = __exit;
always @(posedge clk)
begin
r_reset <= reset;
if (reset || r_reset)
begin
__debug_req_valid = 0;
__debug_resp_ready = 0;
__exit = 0;
end
else
begin
__exit = debug_tick(
__debug_req_valid,
__debug_req_ready,
__debug_req_bits_addr,
__debug_req_bits_op,
__debug_req_bits_data,
__debug_resp_valid,
__debug_resp_ready,
__debug_resp_bits_resp,
__debug_resp_bits_data
);
end
end
*/
endmodule
simple_reviewed/hierarchy/yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v 0 → 100644
module tag_array_ext(
input RW0_clk,
input [5:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [351:0] RW0_wdata,
output [351:0] RW0_rdata
);
reg reg_RW0_ren;
reg [5:0] reg_RW0_addr;
reg [351:0] ram [63:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 64; initvar = initvar+1)
ram[initvar] = {11 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
if (RW0_wmask[0]) ram[RW0_addr][21:0] <= RW0_wdata[21:0];
if (RW0_wmask[1]) ram[RW0_addr][43:22] <= RW0_wdata[43:22];
if (RW0_wmask[2]) ram[RW0_addr][65:44] <= RW0_wdata[65:44];
if (RW0_wmask[3]) ram[RW0_addr][87:66] <= RW0_wdata[87:66];
if (RW0_wmask[4]) ram[RW0_addr][109:88] <= RW0_wdata[109:88];
if (RW0_wmask[5]) ram[RW0_addr][131:110] <= RW0_wdata[131:110];
if (RW0_wmask[6]) ram[RW0_addr][153:132] <= RW0_wdata[153:132];
if (RW0_wmask[7]) ram[RW0_addr][175:154] <= RW0_wdata[175:154];
if (RW0_wmask[8]) ram[RW0_addr][197:176] <= RW0_wdata[197:176];
if (RW0_wmask[9]) ram[RW0_addr][219:198] <= RW0_wdata[219:198];
if (RW0_wmask[10]) ram[RW0_addr][241:220] <= RW0_wdata[241:220];
if (RW0_wmask[11]) ram[RW0_addr][263:242] <= RW0_wdata[263:242];
if (RW0_wmask[12]) ram[RW0_addr][285:264] <= RW0_wdata[285:264];
if (RW0_wmask[13]) ram[RW0_addr][307:286] <= RW0_wdata[307:286];
if (RW0_wmask[14]) ram[RW0_addr][329:308] <= RW0_wdata[329:308];
if (RW0_wmask[15]) ram[RW0_addr][351:330] <= RW0_wdata[351:330];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [351:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[351:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module array_0_0_ext(
input W0_clk,
input [8:0] W0_addr,
input W0_en,
input [63:0] W0_data,
input [0:0] W0_mask,
input R0_clk,
input [8:0] R0_addr,
input R0_en,
output [63:0] R0_data
);
reg reg_R0_ren;
reg [8:0] reg_R0_addr;
reg [63:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][63:0] <= W0_data[63:0];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random, $random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random, $random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[63:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule
module tag_array_0_ext(
input RW0_clk,
input [5:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [335:0] RW0_wdata,
output [335:0] RW0_rdata
);
reg reg_RW0_ren;
reg [5:0] reg_RW0_addr;
reg [335:0] ram [63:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 64; initvar = initvar+1)
ram[initvar] = {11 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
if (RW0_wmask[0]) ram[RW0_addr][20:0] <= RW0_wdata[20:0];
if (RW0_wmask[1]) ram[RW0_addr][41:21] <= RW0_wdata[41:21];
if (RW0_wmask[2]) ram[RW0_addr][62:42] <= RW0_wdata[62:42];
if (RW0_wmask[3]) ram[RW0_addr][83:63] <= RW0_wdata[83:63];
if (RW0_wmask[4]) ram[RW0_addr][104:84] <= RW0_wdata[104:84];
if (RW0_wmask[5]) ram[RW0_addr][125:105] <= RW0_wdata[125:105];
if (RW0_wmask[6]) ram[RW0_addr][146:126] <= RW0_wdata[146:126];
if (RW0_wmask[7]) ram[RW0_addr][167:147] <= RW0_wdata[167:147];
if (RW0_wmask[8]) ram[RW0_addr][188:168] <= RW0_wdata[188:168];
if (RW0_wmask[9]) ram[RW0_addr][209:189] <= RW0_wdata[209:189];
if (RW0_wmask[10]) ram[RW0_addr][230:210] <= RW0_wdata[230:210];
if (RW0_wmask[11]) ram[RW0_addr][251:231] <= RW0_wdata[251:231];
if (RW0_wmask[12]) ram[RW0_addr][272:252] <= RW0_wdata[272:252];
if (RW0_wmask[13]) ram[RW0_addr][293:273] <= RW0_wdata[293:273];
if (RW0_wmask[14]) ram[RW0_addr][314:294] <= RW0_wdata[314:294];
if (RW0_wmask[15]) ram[RW0_addr][335:315] <= RW0_wdata[335:315];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [351:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[335:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module data_arrays_0_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [511:0] RW0_wdata,
output [511:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [511:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {16 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
if (RW0_wmask[0]) ram[RW0_addr][31:0] <= RW0_wdata[31:0];
if (RW0_wmask[1]) ram[RW0_addr][63:32] <= RW0_wdata[63:32];
if (RW0_wmask[2]) ram[RW0_addr][95:64] <= RW0_wdata[95:64];
if (RW0_wmask[3]) ram[RW0_addr][127:96] <= RW0_wdata[127:96];
if (RW0_wmask[4]) ram[RW0_addr][159:128] <= RW0_wdata[159:128];
if (RW0_wmask[5]) ram[RW0_addr][191:160] <= RW0_wdata[191:160];
if (RW0_wmask[6]) ram[RW0_addr][223:192] <= RW0_wdata[223:192];
if (RW0_wmask[7]) ram[RW0_addr][255:224] <= RW0_wdata[255:224];
if (RW0_wmask[8]) ram[RW0_addr][287:256] <= RW0_wdata[287:256];
if (RW0_wmask[9]) ram[RW0_addr][319:288] <= RW0_wdata[319:288];
if (RW0_wmask[10]) ram[RW0_addr][351:320] <= RW0_wdata[351:320];
if (RW0_wmask[11]) ram[RW0_addr][383:352] <= RW0_wdata[383:352];
if (RW0_wmask[12]) ram[RW0_addr][415:384] <= RW0_wdata[415:384];
if (RW0_wmask[13]) ram[RW0_addr][447:416] <= RW0_wdata[447:416];
if (RW0_wmask[14]) ram[RW0_addr][479:448] <= RW0_wdata[479:448];
if (RW0_wmask[15]) ram[RW0_addr][511:480] <= RW0_wdata[511:480];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [511:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[511:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule
module mem_ext(
input W0_clk,
input [26:0] W0_addr,
input W0_en,
input [63:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [26:0] R0_addr,
input R0_en,
output [63:0] R0_data
);
reg reg_R0_ren;
reg [26:0] reg_R0_addr;
reg [63:0] ram [134217727:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 134217728; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][7:0] <= W0_data[7:0];
if (W0_mask[1]) ram[W0_addr][15:8] <= W0_data[15:8];
if (W0_mask[2]) ram[W0_addr][23:16] <= W0_data[23:16];
if (W0_mask[3]) ram[W0_addr][31:24] <= W0_data[31:24];
if (W0_mask[4]) ram[W0_addr][39:32] <= W0_data[39:32];
if (W0_mask[5]) ram[W0_addr][47:40] <= W0_data[47:40];
if (W0_mask[6]) ram[W0_addr][55:48] <= W0_data[55:48];
if (W0_mask[7]) ram[W0_addr][63:56] <= W0_data[63:56];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random, $random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random, $random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[63:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule
module mem_0_ext(
input W0_clk,
input [8:0] W0_addr,
input W0_en,
input [63:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [8:0] R0_addr,
input R0_en,
output [63:0] R0_data
);
reg reg_R0_ren;
reg [8:0] reg_R0_addr;
reg [63:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][7:0] <= W0_data[7:0];
if (W0_mask[1]) ram[W0_addr][15:8] <= W0_data[15:8];
if (W0_mask[2]) ram[W0_addr][23:16] <= W0_data[23:16];
if (W0_mask[3]) ram[W0_addr][31:24] <= W0_data[31:24];
if (W0_mask[4]) ram[W0_addr][39:32] <= W0_data[39:32];
if (W0_mask[5]) ram[W0_addr][47:40] <= W0_data[47:40];
if (W0_mask[6]) ram[W0_addr][55:48] <= W0_data[55:48];
if (W0_mask[7]) ram[W0_addr][63:56] <= W0_data[63:56];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random, $random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random, $random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[63:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule
simple_reviewed/hierarchy/yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
simple_reviewed/hierarchy/yosys_rocket/plusarg_reader.v 0 → 100644
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),
// but Incisive demands them. These default values should never be used.
module plusarg_reader #(parameter FORMAT="borked=%d", DEFAULT=0) (
output [31:0] out
);
`ifdef SYNTHESIS
assign out = DEFAULT;
`else
reg [31:0] myplus;
assign out = myplus;
initial begin
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
end
`endif
endmodule
simple_reviewed/ice40_dsp/ice40_dsp.ys 0 → 100644
read_verilog ../top.v
proc
ice40_dsp
select -assert-count 1 t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_a_larger.ys 0 → 100644
read_verilog ../top_mult_a_larger.v
proc
ice40_dsp
stat
select -assert-none t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_acc.ys 0 → 100644
read_verilog ../top_mult_acc.v
proc
ice40_dsp
select -assert-count 1 t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_b_larger.ys 0 → 100644
read_verilog ../top_mult_b_larger.v
proc
ice40_dsp
stat
select -assert-none t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_out_larger.ys 0 → 100644
read_verilog ../top_mult_out_larger.v
proc
ice40_dsp
stat
select -assert-none t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/ice40_dsp_mult_signed.ys 0 → 100644
read_verilog ../top_mult_signed.v
proc
ice40_dsp
stat
select -assert-count 1 t:SB_MAC16
synth_ice40 -top top
simple_reviewed/ice40_dsp/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [31:0] P;
input [15:0] A;
input [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg [31:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input carryin,
output [31:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple_reviewed/ice40_dsp/top_mult_a_larger.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple_reviewed/ice40_dsp/top_mult_acc.v 0 → 100644
module top
(
input [7:0] dataa,
input [7:0] datab,
input clk, aclr, clken, sload,
output reg [15:0] adder_out
);
// Declare registers and wires
reg [15:0] dataa_reg, datab_reg;
reg sload_reg;
reg [15:0] old_result;
wire [15:0] multa;
// Store the results of the operations on the current data
assign multa = dataa_reg * datab_reg;
// Store the value of the accumulation (or clear it)
always @ (adder_out, sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
old_result <= adder_out;
end
// Clear or update data, as appropriate
always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 0;
datab_reg <= 0;
sload_reg <= 0;
adder_out <= 0;
end
else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
end
end
endmodule
simple_reviewed/ice40_dsp/top_mult_b_larger.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [15:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [15:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple_reviewed/ice40_dsp/top_mult_out_larger.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [15:0] A;
input [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple_reviewed/ice40_dsp/top_mult_signed.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg signed [31:0] P;
input signed [15:0] A;
input signed [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg signed [31:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input signed [15:0] a,
input signed [15:0] b,
input carryin,
output signed [31:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple_reviewed/inout_port/deminout.ys 0 → 100644
read_verilog ../top.v
deminout
simple_reviewed/inout_port/deminout_demote.ys 0 → 100644
read_verilog ../top_demote.v
deminout
tee -o result.out dump
simple_reviewed/inout_port/deminout_synth.ys 0 → 100644
read_verilog ../top.v
synth -top top
deminout
simple_reviewed/inout_port/deminout_synth_demote.ys 0 → 100644
read_verilog ../top_demote.v
synth -top top
deminout
simple_reviewed/inout_port/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
simple_reviewed/inout_port/top_demote.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
reg [1:0] io_buf;
assign io = io_buf;
always @(en or i)
io_buf[0] <= (en)? i : 1'bZ;
always @(en or i)
io_buf[1] <= (i)? en : 1'bZ;
assign o = (en)? io : 2'bZZ;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
simple_reviewed/iopadmap/iopadmap.pat 0 → 100644
cell \\IOBUFE $auto$iopadmap.cc
simple_reviewed/iopadmap/iopadmap.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result1.out dump
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
tee -o result.out dump
simple_reviewed/iopadmap/iopadmap_dont_map.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result1.out dump
iopadmap -widthparam wp
iopadmap -nameparam np
iopadmap -bits
iopadmap -inpad IBUF O:I
iopadmap -outpad IOBUFE O:IO
iopadmap -inoutpad IOBUFE O:IO
iopadmap -toutpad IOBUFE O:IO
iopadmap -tinoutpad IOBUFE O:IO
tee -o result.out dump
simple_reviewed/iopadmap/iopadmap_ignore.disable 0 → 100644
read_verilog ../top.v
proc
tee -o result1.out dump
iopadmap -ignore IBUF O:I -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
tee -o result.out dump
simple_reviewed/iopadmap/iopadmap_ignore.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result1.out dump
iopadmap -ignore IBUF O:I -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
tee -o result.out dump
simple_reviewed/iopadmap/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
reg [1:0] io_buf;
assign io = io_buf;
always @(en or i)
io_buf[0] <= (en)? i : 1'bZ;
always @(en or i)
io_buf[1] <= (i)? en : 1'bZ;
assign o = (en)? io : 2'bZZ;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
simple_reviewed/macc/macc.ys 0 → 100644
read_verilog ../top.v
proc
alumacc
maccmap -unmap
select -assert-count 1 t:$alu
simple_reviewed/macc/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
endmodule
simple_reviewed/memory/memory.ys 0 → 100644
read_verilog ../top.v
proc
memory
stat
simple_reviewed/memory/memory_bram_cant_open_rules_file_fail.ys 0 → 100644
read_verilog ../top.v
proc
memory_bram -rules uuu
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_bram_opt.ys 0 → 100644
read_verilog ../top.v
proc
memory -bram ../words.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_bram_syntax_error_in_rules_fail.ys 0 → 100644
read_verilog ../top.v
proc
memory_bram -rules ../rules.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_memx.ys 0 → 100644
read_verilog ../top.v
proc
memory_memx
select -assert-count 2 t:$memwr
select -assert-count 2 t:$memrd
simple_reviewed/memory/memory_memx_opt.ys 0 → 100644
read_verilog ../top.v
proc
memory -memx
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_nomap.ys 0 → 100644
read_verilog ../top.v
proc
memory -nomap
memory_map
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_nordff.ys 0 → 100644
read_verilog ../top.v
memory_nordff
proc
memory_nordff
memory_dff
memory_nordff
opt_clean
memory_nordff
memory_share
memory_nordff
opt_clean
memory_nordff
memory_collect
memory_nordff
memory_map
memory_nordff
memory_unpack
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_nordff_opt.ys 0 → 100644
read_verilog ../top.v
proc
memory -nordff
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_nordff_single_port.ys 0 → 100644
read_verilog ../top_single_port.v
memory_nordff
proc
memory_nordff
memory_dff
memory_nordff
opt_clean
memory_nordff
memory_share
memory_nordff
opt_clean
memory_nordff
memory_collect
memory_nordff
memory_map
memory_nordff
memory_unpack
simple_reviewed/memory/memory_share.ys 0 → 100644
read_verilog ../top.v
proc
memory_share
memory_dff
memory_share
opt_clean
memory_share
memory_nordff
opt_clean
memory_share
memory_collect
memory_share
memory_nordff
memory_share
memory_map
memory_share
memory
memory_share
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_single_port.ys 0 → 100644
read_verilog ../top_single_port.v
proc
memory
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/memory/memory_unpack.ys 0 → 100644
read_verilog ../top.v
proc
memory_unpack
memory_collect
memory_unpack
memory_memx
memory_unpack
memory
memory_unpack
select -assert-count 2 t:$memwr
select -assert-count 2 t:$memrd
simple_reviewed/memory/rules.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/memory/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/memory/top_single_port.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
simple_reviewed/muxcover/muxcover.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover
select -assert-count 17 t:$_MUX16_
simple_reviewed/muxcover/muxcover_4_8_16_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux4 -mux8 -mux16 -nodecode
select -assert-count 17 t:$_MUX16_
simple_reviewed/muxcover/muxcover_dmux.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -dmux=3
select -assert-count 17 t:$_MUX16_
simple_reviewed/muxcover/muxcover_mux16.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux16
select -assert-count 17 t:$_MUX16_
simple_reviewed/muxcover/muxcover_mux16_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux16 -nodecode
select -assert-count 17 t:$_MUX16_
simple_reviewed/muxcover/muxcover_mux2.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux2=336
select -assert-count 17 t:$_MUX16_
simple_reviewed/muxcover/muxcover_mux4.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux4
select -assert-count 85 t:$_MUX4_
simple_reviewed/muxcover/muxcover_mux4_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -mux4 -nodecode
select -assert-count 85 t:$_MUX4_
simple_reviewed/muxcover/muxcover_mux8.ys 0 → 100644
read_verilog ../top_mux8.v
synth -top top
muxcover -mux8
select -assert-count 9 t:$_MUX8_
simple_reviewed/muxcover/muxcover_mux8_nodecode.ys 0 → 100644
read_verilog ../top_mux8.v
synth -top top
muxcover -mux8 -nodecode
select -assert-count 9 t:$_MUX8_
simple_reviewed/muxcover/muxcover_nodecode.ys 0 → 100644
read_verilog ../top.v
synth -top top
muxcover -nodecode
select -assert-count 17 t:$_MUX16_
simple_reviewed/muxcover/top.v 0 → 100644
module top (
input [7:0] S,
input [255:0] D,
output M256
);
assign M256 = D[S];
endmodule
simple_reviewed/muxcover/top_mux8.v 0 → 100644
module top (
input [5:0] S,
input [63:0] D,
output M256
);
assign M256 = D[S];
endmodule
simple_reviewed/nlutmap/nlutmap.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 2:5
nlutmap
select -assert-none t:$lut
simple_reviewed/nlutmap/nlutmap_assert.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 4
nlutmap -luts 10,20,30,40 -assert
select -assert-count 2 t:$lut
simple_reviewed/nlutmap/nlutmap_error_fail.pat 0 → 100644
ERROR: Insufficient number of LUTs to map all logic cells!
simple_reviewed/nlutmap/nlutmap_error_fail.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 5
nlutmap -luts 6 -assert
tee -o result.log dump
write_verilog synth.v
simple_reviewed/nlutmap/nlutmap_luts.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 4
nlutmap -luts 10,20,30,40
select -assert-count 2 t:$lut
simple_reviewed/nlutmap/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire p,r,s;
xor (p,x,y);
xor (A,p,cin);
and(r,p,cin);
and(s,x,y);
or(cout,r,s);
endmodule
simple_reviewed/opt/opt.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_clkinv.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -clkinv
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_fast.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -fast
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 9 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_fine.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -fine
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_full.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -full
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 5 t:$mux
select -assert-count 3 t:$or
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$or t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_keepdc.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -keepdc
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_mux_bool.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -mux_bool
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 5 t:$mux
select -assert-count 3 t:$or
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$or t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_mux_undef.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -mux_undef
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 7 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_purge.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -purge
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_sat.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -sat
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_share_all.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -share_all
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/opt_undriven.ys 0 → 100644
read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt -undriven
stat
select -assert-count 1 t:$dff
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
simple_reviewed/opt/top.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
input [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
simple_reviewed/opt_demorgan/opt_demorgan.ys 0 → 100644
read_verilog ../top.v
techmap -autoproc
extract_reduce
opt_demorgan top
stat
simple_reviewed/opt_demorgan/opt_demorgan_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
techmap -autoproc
extract_reduce
opt_demorgan top
stat
simple_reviewed/opt_demorgan/top.v 0 → 100644
module dffr
( input d, clk, rst, output reg q );
always @( posedge clk )
if ( rst )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffr u_dffr (
.clk (clk),
.rst (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/opt_demorgan/top_reduce.v 0 → 100644
module top
(
input x,
input [2:0] y,
input [2:0] cin,
output A,
output cout,
output control
);
wire A1,cout1;
wire [2:0] n_y;
wire [2:0] n_cin;
// initial begin
// A = 0;
// cout = 0;
// end
assign n_y[0] = ~y[0];
assign n_y[1] = y[1];
assign n_y[2] = ~y[2];
assign n_cin[0] = ~cin[0];
assign n_cin[1] = cin[1];
assign n_cin[2] = ~cin[2];
assign A1 = n_y + &(~cin);
assign cout1 = cin ? |n_y : ^A;
assign A = A1|y~&(~cin)~^A1;
assign cout = cout1&cin~|(~y);
assign control = x & y & cin;
endmodule
simple_reviewed/opt_expr/opt_expr.ys 0 → 100644
read_verilog ../top.v
synth -top top
opt_expr
proc
opt_expr
flatten
opt
stat
opt_expr
stat
simple_reviewed/opt_expr/opt_expr_keepdc.ys 0 → 100644
read_verilog ../top.v
synth -top top
opt_expr
proc
opt_expr
flatten
opt
stat
opt_expr -keepdc
stat
simple_reviewed/opt_expr/top.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( negedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b
);
dffsr u_dffsr (
.clk (clk ),
`ifndef BUG
.clr (clr),
.pre (pre),
`else
.clr (1'b1),
.pre (1'b0),
`endif
.d (a ),
.q (b )
);
endmodule
simple_reviewed/opt_lut/opt_lut.ys 0 → 100644
read_verilog ../top.v
synth_ice40
opt_lut
simple_reviewed/opt_lut/opt_lut_dlogic.ys 0 → 100644
read_verilog ../top.v
synth_ice40
opt_lut -dlogic $_ANDNOT_:A=I0
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/opt_lut/opt_lut_limit.ys 0 → 100644
read_verilog ../top.v
synth_ice40
opt_lut -limit 2
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/opt_lut/opt_lut_limit_0.ys 0 → 100644
read_verilog ../top.v
synth_ice40
opt_lut -limit 0
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/opt_lut/opt_lut_macc.ys 0 → 100644
read_verilog ../top_ice40.v
synth_ice40
opt_lut
simple_reviewed/opt_lut/top.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p,
output [47:0] pw
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
MACC u_MACC_1 (
.P (pw),
.A (a),
.B (b ),
.CARRYIN (~carryin ),
.CLK (~clk),
.RST (~rst)
);
endmodule
simple_reviewed/opt_lut/top_ice40.v 0 → 100644
module top(
input [8:0] a,
input [8:0] b,
output [8:0] o1,
output [2:0] o2,
input [2:0] c,
input [2:0] d,
output [2:0] o3,
output [2:0] o4,
input s
);
assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);
endmodule
simple_reviewed/opt_merge_reduce/opt_merge.ys 0 → 100644
read_verilog -formal ../top.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/opt_merge_nomux.ys 0 → 100644
read_verilog -formal ../top.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge -nomux
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/opt_merge_share_all.ys 0 → 100644
read_verilog -formal ../top.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge -share_all
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/opt_merge_share_all_2.ys 0 → 100644
read_verilog -formal ../top2.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge -share_all
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
simple_reviewed/opt_merge_reduce/top.v 0 → 100644
module top
(
input x,
input [2:0] y,
input [2:0] cin,
output A,
output cout,
output control
);
wire A1,cout1;
wire [2:0] n_y;
wire [2:0] n_cin;
// initial begin
// A = 0;
// cout = 0;
// end
assign n_y[0] = ~y[0];
assign n_y[1] = y[1];
assign n_y[2] = ~y[2];
assign n_cin[0] = ~cin[0];
assign n_cin[1] = cin[1];
assign n_cin[2] = ~cin[2];
assign A1 = n_y + &(~cin);
assign cout1 = cin ? |n_y : ^A;
assign A = A1|y~&(~cin)~^A1;
assign cout = cout1&cin~|(~y);
assign control = x & y & cin;
endmodule
simple_reviewed/opt_merge_reduce/top2.v 0 → 100644
`ifdef FORMAL
`define assume(_expr_) assume(_expr_)
`else
`define assume(_expr_)
`endif
module top(input clk, input [4:0] addr, output reg [31:0] data, output clk_o);
reg [31:0] mem [0:31];
always @(posedge clk)
data <= mem[addr];
reg [31:0] used_addr = 0;
reg [31:0] used_dbits = 0;
reg initstate = 1;
always @(posedge clk) begin
initstate <= 1;
if (!initstate) begin
//`assume(data != 0);
//`assume((used_dbits & data) == 0);
end
end
assign clk_o = clk;
endmodule
simple_reviewed/opt_rmdff/dff.ys 0 → 100644
read_verilog ../top.v
proc
opt
opt_rmdff
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_async.ys 0 → 100644
read_verilog ../top_async.v
proc
dff2dffe
#opt
opt_rmdff
synth -top top
proc
flatten
#opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_ff.ys 0 → 100644
read_verilog ../top_async.v
proc
clk2fflogic
#opt
opt_rmdff
synth -top top
proc
flatten
#opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_keepdc.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff -keepdc
write_verilog synth.v
simple_reviewed/opt_rmdff/dff_sat.ys 0 → 100644
read_verilog ../top.v
synth -top top
proc
flatten
opt
opt_rmdff -sat
write_verilog synth.v
simple_reviewed/opt_rmdff/dffc.ys 0 → 100644
read_verilog ../top_dffc.v
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffcp.ys 0 → 100644
read_verilog ../top_dffcp.v
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffcp_d0.ys 0 → 100644
read_verilog ../top_dff_d0.v
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffr.ys 0 → 100644
read_verilog ../top_dffr.v
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/dffsr.ys 0 → 100644
read_verilog ../top_dffsr.v
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/latsr.ys 0 → 100644
read_verilog ../top_lat.v
synth -top top
proc
flatten
opt
opt_rmdff
write_verilog synth.v
simple_reviewed/opt_rmdff/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffs
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffns
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/opt_rmdff/top_async.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (1'b1),
.pre (pre),
.d (1'b0 ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (1'b0),
.d (1'b0 ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (1'b1),
.d (1'b0 ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (1'b1),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (1'b0 ),
.q (b4 )
);
endmodule
simple_reviewed/opt_rmdff/top_dff_d0.v 0 → 100644
module dff (clk, d, q);
input clk;
input d;
output reg q;
always @(posedge clk)
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk (clk ),
.d (1'b0 ),
.q (b )
);
endmodule
simple_reviewed/opt_rmdff/top_dffc.v 0 → 100644
module dffcp
( input d, clk, pre, clr, output reg q );
always @( posedge clk)
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
input c,
output b
);
dffcp u_dffcp (
.clk (clk ),
.clr (c ),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/opt_rmdff/top_dffcp.v 0 → 100644
module dffcp
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, posedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffcp u_dffcp (
.clk (clk ),
.clr (1'b0),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/opt_rmdff/top_dffr.v 0 → 100644
module dffr
( input d, clk, rst, output reg q );
always @( posedge clk )
if ( rst )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffr u_dffr (
.clk (clk),
.rst (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/opt_rmdff/top_dffsr.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
dffsr u_dffsr (
.clk (clk ),
.clr (1'b1),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/opt_rmdff/top_lat.v 0 → 100644
module latsr
( input d, clk, pre, clr, output reg q );
always @(*)
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module top (
input clk,
input a,
output b
);
latsr u_latsr (
.clk (clk ),
.clr (1'b1),
.pre (1'b1),
.d (a ),
.q (b )
);
endmodule
simple_reviewed/paramap/paramap.ys 0 → 100644
read_verilog ../top.v
proc
synth_ecp5
paramap -tocase INIT t:LUT4
tee -o result.out dump
simple_reviewed/paramap/top.v 0 → 100644
module top (
input clock,
input [3:0] dinA, dinB,
input [2:0] opcode,
output reg [3:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule
simple_reviewed/prep/prep.ys 0 → 100644
read_verilog ../top.v
prep
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_auto_top.ys 0 → 100644
read_verilog ../top.v
prep -auto-top
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_error_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
simple_reviewed/prep/prep_error_fail.ys 0 → 100644
read_verilog ../top.v
select dffe
prep
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_flatten.ys 0 → 100644
read_verilog ../top.v
prep -flatten
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_ifx.ys 0 → 100644
read_verilog ../top.v
prep -ifx
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_memx.ys 0 → 100644
read_verilog ../top.v
prep -memx
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_nokeepdc.ys 0 → 100644
read_verilog ../top.v
prep -nokeepdc
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_nomem.ys 0 → 100644
read_verilog ../top.v
prep -nomem
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_nordff.ys 0 → 100644
read_verilog ../top.v
prep -nordff
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_rdff.ys 0 → 100644
read_verilog ../top.v
prep -rdff
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_run.ys 0 → 100644
read_verilog ../top.v
prep -run begin:check
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_run_begin.ys 0 → 100644
read_verilog ../top.v
prep -run begin
synth -top top
write_verilog synth.v
simple_reviewed/prep/prep_top.ys 0 → 100644
read_verilog ../top.v
prep -top top
synth -top top
write_verilog synth.v
simple_reviewed/prep/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/proc_arst/proc_arst.ys 0 → 100644
read_verilog ../top.v
proc_arst
synth -top top
write_verilog synth.v
simple_reviewed/proc_arst/proc_arst_global_rst.ys 0 → 100644
read_verilog ../top.v
proc_arst -global_arst top/rst
synth -top top
write_verilog synth.v
simple_reviewed/proc_arst/proc_arst_global_rst_a.ys 0 → 100644
read_verilog ../top_reduce.v
proc_arst -global_arst a
synth -top top
write_verilog synth.v
simple_reviewed/proc_arst/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
simple_reviewed/proc_arst/top_no_rst.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,arst
);
output x;
reg x;
input clk;
input rst;
input [1:0] arst;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (arst)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
simple_reviewed/proc_arst/top_reduce.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input [2:0] rst;
input [1:0] a;
wire rst_or;
assign rst_or = |rst;
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
simple_reviewed/reduce/reduce.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_reduce
select -assert-count 1 t:$reduce_or
select -assert-count 1 t:$reduce_xor
simple_reviewed/reduce/reduce_allow_off_chain.ys 0 → 100644
read_verilog ../top.v
synth -top top
extract_reduce -allow-off-chain
select -assert-count 1 t:$reduce_or
select -assert-count 1 t:$reduce_xor
simple_reviewed/reduce/top.v 0 → 100644
module top
(
input [7:0] x,
output o_and,
output o_or,
output o_xor,
output o_nand,
output o_nor,
output o_xnor
);
assign o_and = &x;
assign o_or = |x;
assign o_xor = ^x;
assign o_nand = ~&x;
assign o_nor = ~|x;
assign o_xnor = ~^x;
endmodule
simple_reviewed/share/share.ys 0 → 100644
read_verilog ../top.v
proc
share
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive.ys 0 → 100644
read_verilog ../top.v
proc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive_macc.ys 0 → 100644
read_verilog ../top_macc.v
proc
flatten
alumacc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_aggressive_shr.ys 0 → 100644
read_verilog ../top_shr.v
proc
share -aggressive
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast.ys 0 → 100644
read_verilog ../top.v
proc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast_macc.ys 0 → 100644
read_verilog ../top_macc.v
proc
flatten
alumacc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fast_shr.ys 0 → 100644
read_verilog ../top_shr.v
proc
share -fast
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force.ys 0 → 100644
read_verilog ../top.v
proc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force_fsm.disable 0 → 100644
read_verilog ../top_fsm.v
proc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force_macc.ys 0 → 100644
read_verilog ../top_macc.v
proc
#flatten
alumacc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_force_shr.ys 0 → 100644
read_verilog ../top_shr.v
proc
share -force
synth -top top
write_verilog synth.v
simple_reviewed/share/share_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
share
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit.ys 0 → 100644
read_verilog ../top.v
proc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit_macc.ys 0 → 100644
read_verilog ../top_macc.v
proc
flatten
alumacc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_limit_shr.ys 0 → 100644
read_verilog ../top_shr.v
proc
share -limit 1
synth -top top
write_verilog synth.v
simple_reviewed/share/share_macc.ys 0 → 100644
read_verilog ../top_macc.v
proc
alumacc
share
synth -top top
write_verilog synth.v
simple_reviewed/share/share_shr.ys 0 → 100644
read_verilog ../top_shr.v
proc
share
synth -top top
write_verilog synth.v
simple_reviewed/share/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/share/top_fsm.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
simple_reviewed/share/top_macc.v 0 → 100644
module MACC (P, A, B, CARRYIN, CLK, RST);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK)
begin
if(!RST)
mult_reg <= 'b0;
else
mult_reg <= A * B;
end
always@(posedge CLK)
begin
if(!RST)
P <= 'b0;
else
P <= mult_reg + CARRYIN;
end
endmodule
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p,
output [47:0] pw
);
MACC u_MACC (
.P (p),
.A (a),
.B (b ),
.CARRYIN (carryin ),
.CLK (clk),
.RST (rst)
);
MACC u_MACC_1 (
.P (pw),
.A (a),
.B (b ),
.CARRYIN (~carryin ),
.CLK (~clk),
.RST (~rst)
);
endmodule
simple_reviewed/share/top_shr.v 0 → 100644
module top (
out,
out1,
clk,
in
);
output [7:0] out;
output [7:0] out1;
input signed clk, in;
reg signed [7:0] out;
reg signed [7:0] out1;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
always @(posedge clk)
begin
out1 <= out1 >> 1;
out1[7] <= in;
end
endmodule
simple_reviewed/shregmap/shregmap.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4
shregmap
simple_reviewed/shregmap/shregmap_clkpol_any.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -clkpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_clkpol_neg.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -clkpol neg
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_clkpol_pos.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -clkpol pos
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_any.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -enpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_any_or_none.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol any_or_none
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_neg.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol neg
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_none.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol none
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_enpol_pos.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -enpol pos
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_init.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -init
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_keep_after.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -keep_after 5
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_keep_before.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -keep_before 3
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -match \GP_DFF
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match_clkpol_fail.pat 0 → 100644
ERROR: Options -clkpol and -match are exclusive!
simple_reviewed/shregmap/shregmap_match_clkpol_fail.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -match -clkpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match_enpol_fail.pat 0 → 100644
ERROR: Options -enpol and -match are exclusive!
simple_reviewed/shregmap/shregmap_match_enpol_fail.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -match foobar -enpol any
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_match_params_fail.pat 0 → 100644
ERROR: Options -params and -match are exclusive!
simple_reviewed/shregmap/shregmap_match_params_fail.ys 0 → 100644
read_verilog ../top.v
shregmap -params -match 2:2
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_maxlen.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -maxlen 10
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_minlen.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -minlen 4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_params.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -params
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_resetable.ys 0 → 100644
read_verilog ../top_resetable.v
synth_greenpak4
shregmap
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_tech.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_zinit.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -zinit
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/shregmap_zinit_init_fail.pat 0 → 100644
ERROR: Options -zinit and -init are exclusive!
simple_reviewed/shregmap/shregmap_zinit_init_fail.ys 0 → 100644
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
shregmap -tech greenpak4 -zinit -init
design -reset
read_verilog ../top.v
write_verilog synth.v
simple_reviewed/shregmap/simplemap.ys 0 → 100644
read_verilog ../top.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/shregmap/simplemap_slice_concat.ys 0 → 100644
read_verilog ../top.v
synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/shregmap/simplemap_top.ys 0 → 100644
read_verilog ../top.v
prep
dff2dffe
simplemap top
synth
write_verilog synth.v
simple_reviewed/shregmap/top.v 0 → 100644
module top (
out,
clk,
in
);
output [7:0] out;
input clk, in;
reg [7:0] out;
always @(posedge clk)
begin
out <= out << 1;
out[0] <= in;
end
endmodule
simple_reviewed/shregmap/top_resetable.v 0 → 100644
module top
#(parameter N=8)
(
input wire clk, reset,
input wire s_in,
output wire s_out
);
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
always @(posedge clk, negedge reset)
begin
if (~reset)
r_reg <= 0;
else
r_reg <= r_next;
end
assign r_next = {s_in, r_reg[N-1:1]};
assign s_out = r_reg[0];
endmodule
simple_reviewed/simplemap/simplemap.ys 0 → 100644
read_verilog ../top.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_mem.ys 0 → 100644
read_verilog ../top_mem_slice_concat.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
prep
simplemap
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_splice_concat.ys 0 → 100644
read_verilog ../top.v
synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_splice_concat_mem.ys 0 → 100644
read_verilog ../top_mem_slice_concat.v
synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_splice_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
synth
splice
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_top.ys 0 → 100644
read_verilog ../top.v
prep
dff2dffe
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_top_mem.ys 0 → 100644
read_verilog ../top_mem_slice_concat.v
prep
dff2dffe
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/simplemap_top_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
prep
simplemap top
synth
write_verilog synth.v
simple_reviewed/simplemap/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/simplemap/top_mem_slice_concat.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/simplemap/top_reduce.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input [0:0] rst;
input [0:0] a;
wire rst_or;
assign rst_or = |rst;
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
simple_reviewed/submod/submod.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_copy.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -copy
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_error_fail.pat 0 → 100644
ERROR: More than one module selected: \top \fsm2
simple_reviewed/submod/submod_error_fail.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -name fsm -name fsm2
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_mem.ys 0 → 100644
read_verilog ../top_mem.v
memory_memx
proc
submod
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_name.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -copy -name a top
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_no_hier.ys 0 → 100644
read_verilog ../top.v
proc
submod
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_no_proc.ys 0 → 100644
read_verilog ../top.v
submod
synth -top top
write_verilog synth.v
simple_reviewed/submod/submod_top.ys 0 → 100644
read_verilog ../top.v
proc
hierarchy
submod -copy top
synth -top top
write_verilog synth.v
simple_reviewed/submod/top.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
inout [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
simple_reviewed/submod/top_err.v 0 → 100644
module fsm (
clock,
reset,
req,
gnt
);
input clock,reset;
inout [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module fsm2 (
clock,
reset,
req,
gnt
);
input clock,reset;
inout [1:0] req ;
output [1:0] gnt ;
wire clock,reset;
wire [1:0] req ;
reg [1:0] gnt ;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101,GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case(state)
IDLE : if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1 : if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2 : if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g ;
wire [1:0] r ;
fsm u_fsm ( .clock(clk),
.reset(rst),
.req(r),
.gnt(g));
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
simple_reviewed/submod/top_mem.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/synth/synth.ys 0 → 100644
read_verilog ../top.v
synth
write_verilog synth.v
simple_reviewed/synth/synth_abc9.ys 0 → 100644
read_verilog ../top.v
synth -abc9 -lut 5
write_verilog synth.v
simple_reviewed/synth/synth_abc9_no_lut_fail.pat 0 → 100644
ERROR: ABC9 flow only supported for FPGA synthesis (using '-lut' option)
simple_reviewed/synth/synth_abc9_no_lut_fail.ys 0 → 100644
read_verilog ../top.v
synth -abc9
write_verilog synth.v
simple_reviewed/synth/synth_auto_top.ys 0 → 100644
read_verilog ../top.v
synth -auto-top
write_verilog synth.v
simple_reviewed/synth/synth_encfile.ys 0 → 100644
read_verilog ../top.v
synth -encfile enc.file
write_verilog synth.v
simple_reviewed/synth/synth_error_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
simple_reviewed/synth/synth_error_fail.ys 0 → 100644
read_verilog ../top.v
select adff
synth
write_verilog synth.v
simple_reviewed/synth/synth_flatten.ys 0 → 100644
read_verilog ../top.v
synth -flatten
write_verilog synth.v
simple_reviewed/synth/synth_lut.ys 0 → 100644
read_verilog ../top.v
synth -lut 5
write_verilog synth.v
simple_reviewed/synth/synth_noabc.ys 0 → 100644
read_verilog ../top.v
synth -noabc
write_verilog synth.v
simple_reviewed/synth/synth_noabc_lut.ys 0 → 100644
read_verilog ../top.v
synth -noabc -lut 3
write_verilog synth.v
simple_reviewed/synth/synth_noalumacc.ys 0 → 100644
read_verilog ../top.v
synth -noalumacc
write_verilog synth.v
simple_reviewed/synth/synth_nofsm.ys 0 → 100644
read_verilog ../top.v
synth -nofsm
write_verilog synth.v
simple_reviewed/synth/synth_nordff.ys 0 → 100644
read_verilog ../top.v
synth -nordff
write_verilog synth.v
simple_reviewed/synth/synth_noshare.ys 0 → 100644
read_verilog ../top.v
synth -noshare
write_verilog synth.v
simple_reviewed/synth/synth_run.ys 0 → 100644
read_verilog ../top.v
synth -run begin
write_verilog synth.v
simple_reviewed/synth/synth_run_full.ys 0 → 100644
read_verilog ../top.v
synth -run begin:check
write_verilog synth.v
simple_reviewed/synth/synth_top.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/synth/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/techmap/techmap.ys 0 → 100644
read_verilog ../top.v
proc
techmap
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_assert.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
techmap -assert -map +/techmap.v +/simlib.v
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_autoproc.ys 0 → 100644
read_verilog ../top.v
techmap -autoproc
write_verilog synth.v
simple_reviewed/techmap/techmap_d.ys 0 → 100644
read_verilog ../top.v
proc
techmap -D U
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_extern.ys 0 → 100644
read_verilog ../top.v
proc
techmap -extern
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_i.ys 0 → 100644
read_verilog ../top.v
proc
techmap -I techmap
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_map.ys 0 → 100644
read_verilog ../top.v
proc
techmap -map +/techmap.v
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_max_iter.ys 0 → 100644
read_verilog ../top.v
proc
techmap -max_iter 2
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_recursive.ys 0 → 100644
read_verilog ../top.v
proc
techmap -recursive
synth
write_verilog synth.v
simple_reviewed/techmap/techmap_wb.ys 0 → 100644
read_verilog ../top.v
techmap -wb
write_verilog synth.v
simple_reviewed/techmap/top.v 0 → 100644
(* \\keep_hierarchy *) module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
(* \\techmap_simplemap *)module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
(* \\techmap_maccmap *)module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
(* \\top *)module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/test_pmgen/test_pmgen_eqpmux.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -eqpmux
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_eqpmux.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate eqpmux
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_ice40_dsp.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate ice40_dsp
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_peepopt_muldiv.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate peepopt-muldiv
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_peepopt_shiftmul.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate peepopt-shiftmul
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_reduce.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate reduce
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_xilinx_srl_fixed.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate xilinx_srl.fixed
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_generate_xilinx_srl_variable.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate xilinx_srl.variable
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_reduce_chain.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -reduce_chain
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/test_pmgen_reduce_tree.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log test_pmgen -reduce_tree
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
simple_reviewed/test_pmgen/top.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
simple_reviewed/tribuf/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tribuf/top_logic.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tribuf/tribuf.ys 0 → 100644
read_verilog ../top.v
tribuf
tribuf
proc
tribuf
select -assert-count 1 t:$tribuf
synth -top top
tribuf
simple_reviewed/tribuf/tribuf_logic_top.ys 0 → 100644
read_verilog ../top_logic.v
tribuf -logic tristate
synth -top top
tribuf -logic tristate
select -assert-none t:$tribuf
simple_reviewed/tribuf/tribuf_merge_logic_top.ys 0 → 100644
read_verilog ../top_logic.v
tribuf -logic tristate
tribuf -merge tristate
synth -top top
tribuf -merge -logic tristate
select -assert-none t:$tribuf
simple_reviewed/tribuf/tribuf_merge_top.ys 0 → 100644
read_verilog ../top.v
tribuf -merge tristate
select -assert-count 1 t:$tribuf
synth -top top
tribuf -merge tristate
simple_reviewed/tribuf/tribuf_top.ys 0 → 100644
read_verilog ../top.v
proc
tribuf tristate
select -assert-count 1 t:$tribuf
synth -top top
write_verilog synth.v
simple_reviewed/tristate/top.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tristate/top_case.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
always @(en or i)
begin
case (en)
1:o <= i;
default :o <= 1'bZ;
endcase
end
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tristate/top_const_0.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (1'b0 ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tristate/top_const_1.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (1'b1 ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tristate/top_const_data.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (1'b0 ),
.o (b )
);
endmodule
simple_reviewed/tristate/top_if.v 0 → 100644
module tribuf (en, i, o);
input en;
input i;
output reg o;
always @*
begin
if (en)
o = i;
else
o = 1'bZ;
end
endmodule
module top (
input en,
input a,
output b
);
tribuf u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tristate/top_proc_asmt.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output o;
assign o = (en)? i : 1'bZ;
endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule
simple_reviewed/tristate/tristate.ys 0 → 100644
read_verilog ../top.v
synth -top top
stat
simple_reviewed/tristate/tristate_case.ys 0 → 100644
read_verilog ../top_case.v
synth -top top
stat
simple_reviewed/tristate/tristate_const_0.ys 0 → 100644
read_verilog ../top_const_0.v
synth -top top
stat
simple_reviewed/tristate/tristate_const_1.ys 0 → 100644
read_verilog ../top_const_1.v
synth -top top
stat
simple_reviewed/tristate/tristate_const_data.ys 0 → 100644
read_verilog ../top_const_data.v
synth -top top
stat
simple_reviewed/tristate/tristate_if.ys 0 → 100644
read_verilog ../top_if.v
synth -top top
stat
simple_reviewed/tristate/tristate_proc_asmt.ys 0 → 100644
read_verilog ../top_proc_asmt.v
synth -top top
stat
simple_reviewed/uniquify/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 1'bZ;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 1;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/uniquify/uniquify.ys 0 → 100644
read_verilog ../top.v
synth -top top
uniquify
tee -o result.out dump
simple_reviewed/wreduce/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
assign {cout,A} = cin + y + x;
endmodule
simple_reviewed/wreduce/top_div.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
assign {cout,A} = cin % y / x;
endmodule
simple_reviewed/wreduce/top_mem.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
simple_reviewed/wreduce/top_mul.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
assign {cout,A} = cin * y * x;
endmodule
simple_reviewed/wreduce/top_reduce.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input [2:0] rst;
input [1:0] a;
wire rst_or;
assign rst_or = |rst;
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
simple_reviewed/wreduce/wreduce.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_div.ys 0 → 100644
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_keepdc.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_keepdc_div.ys 0 → 100644
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_keepdc_mem.ys 0 → 100644
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_keepdc_mul.ys 0 → 100644
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_keepdc_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_mem.ys 0 → 100644
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
design -reset
read_verilog ../top_mem.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_div.ys 0 → 100644
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_keepdc.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_keepdc_div.ys 0 → 100644
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_keepdc_mem.ys 0 → 100644
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_keepdc_mul.ys 0 → 100644
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_keepdc_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_mem.ys 0 → 100644
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_mul.ys 0 → 100644
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_memx_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_mul.ys 0 → 100644
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/wreduce/wreduce_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
design -reset
read_verilog ../top.v
synth -top top
write_verilog -noexpr -norename synth.v
simple_reviewed/zinit/synth.v 0 → 100644
/* Generated by Yosys 0.8+492 (git sha1 2058c7c5, gcc 8.3.0-6ubuntu1~18.10 -Og -fPIC) */
(* cells_not_processed = 1 *)
(* src = "../top.v:1" *)
module adff(d, clk, clr, q);
(* src = "../top.v:6" *)
wire _0_;
(* src = "../top.v:3" *)
wire _1_;
(* src = "../top.v:2" *)
input clk;
(* src = "../top.v:2" *)
input clr;
(* src = "../top.v:2" *)
input d;
(* init = 1'h0 *)
(* src = "../top.v:2" *)
output q;
reg q = 1'h0;
always @(posedge clk or posedge clr)
if (clr)
q <= 1'h0;
else
q <= d;
assign _1_ = 1'h0;
assign _0_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:17" *)
module adffn(d, clk, clr, q);
(* src = "../top.v:22" *)
wire _0_;
(* src = "../top.v:19" *)
wire _1_;
(* src = "../top.v:23" *)
wire _2_;
(* src = "../top.v:18" *)
input clk;
(* src = "../top.v:18" *)
input clr;
(* src = "../top.v:18" *)
input d;
(* init = 1'h0 *)
(* src = "../top.v:18" *)
output q;
reg q = 1'h0;
assign _2_ = ! (* src = "../top.v:23" *) clr;
always @(posedge clk or negedge clr)
if (!clr)
q <= 1'h0;
else
q <= d;
assign _1_ = 1'h0;
assign _0_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:33" *)
module dffe(d, clk, en, q);
(* src = "../top.v:38" *)
wire _0_;
(* src = "../top.v:35" *)
wire _1_;
wire _2_;
wire _3_;
wire _4_;
(* src = "../top.v:34" *)
input clk;
(* src = "../top.v:34" *)
input d;
(* src = "../top.v:34" *)
input en;
(* init = 1'h0 *)
(* src = "../top.v:34" *)
output q;
reg q = 1'h0;
assign _2_ = en != 1'h0;
always @(posedge clk)
if (_2_)
q <= _3_;
assign _3_ = _4_ ? (* src = "../top.v:39" *) d : 1'hx;
assign _1_ = 1'h0;
assign _4_ = en;
assign _0_ = _3_;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:47" *)
module dffsr(d, clk, pre, clr, q);
(* src = "../top.v:52" *)
wire _00_;
(* src = "../top.v:49" *)
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
(* src = "../top.v:48" *)
input clk;
(* src = "../top.v:48" *)
input clr;
(* src = "../top.v:48" *)
input d;
(* src = "../top.v:48" *)
input pre;
(* init = 1'h0 *)
(* src = "../top.v:48" *)
output q;
assign _02_ = ~ 1'h1;
assign _03_ = ~ 1'h0;
assign _04_ = pre ? 1'h1 : 1'h0;
assign _05_ = clr ? 1'h0 : _04_;
assign _06_ = pre ? _02_ : 1'h0;
assign _07_ = clr ? _03_ : _06_;
reg [0:0] _14_ = 1'h0;
always @(posedge clk, posedge _05_, posedge _07_)
if (_07_) _14_[0] <= 1'b0;
else if (_05_) _14_[0] <= 1'b1;
else _14_[0] <= d;
assign q = _14_;
assign _01_ = 1'h0;
assign _00_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:65" *)
module ndffnsnr(d, clk, pre, clr, q);
(* src = "../top.v:70" *)
wire _00_;
(* src = "../top.v:67" *)
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
(* src = "../top.v:71" *)
wire _10_;
(* src = "../top.v:77" *)
wire _11_;
(* src = "../top.v:66" *)
input clk;
(* src = "../top.v:66" *)
input clr;
(* src = "../top.v:66" *)
input d;
(* src = "../top.v:66" *)
input pre;
(* init = 1'h0 *)
(* src = "../top.v:66" *)
output q;
assign _02_ = ~ 1'h1;
assign _03_ = ~ 1'h0;
assign _04_ = _08_ ? 1'h1 : 1'h0;
assign _05_ = _09_ ? 1'h0 : _04_;
assign _06_ = _08_ ? _02_ : 1'h0;
assign _07_ = _09_ ? _03_ : _06_;
assign _08_ = ~ pre;
assign _09_ = ~ clr;
assign _10_ = ! (* src = "../top.v:71" *) clr;
assign _11_ = ! (* src = "../top.v:77" *) pre;
reg [0:0] _22_ = 1'h0;
always @(negedge clk, posedge _05_, posedge _07_)
if (_07_) _22_[0] <= 1'b0;
else if (_05_) _22_[0] <= 1'b1;
else _22_[0] <= d;
assign q = _22_;
assign _01_ = 1'h0;
assign _00_ = d;
endmodule
(* cells_not_processed = 1 *)
(* src = "../top.v:83" *)
module top(clk, clr, pre, a, b, b1, b2, b3, b4);
(* src = "../top.v:87" *)
input a;
(* src = "../top.v:88" *)
output b;
(* src = "../top.v:88" *)
output b1;
(* src = "../top.v:88" *)
output b2;
(* src = "../top.v:88" *)
output b3;
(* src = "../top.v:88" *)
output b4;
(* src = "../top.v:84" *)
input clk;
(* src = "../top.v:85" *)
input clr;
(* src = "../top.v:86" *)
input pre;
(* module_not_derived = 32'd1 *)
(* src = "../top.v:107" *)
adff u_adff (
.clk(clk),
.clr(clr),
.d(a),
.q(b2)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:114" *)
adffn u_adffn (
.clk(clk),
.clr(clr),
.d(a),
.q(b3)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:121" *)
dffe u_dffe (
.clk(clk),
.d(a),
.en(clr),
.q(b4)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:91" *)
dffsr u_dffsr (
.clk(clk),
.clr(clr),
.d(a),
.pre(pre),
.q(b)
);
(* module_not_derived = 32'd1 *)
(* src = "../top.v:99" *)
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.d(a),
.pre(pre),
.q(b1)
);
endmodule
simple_reviewed/zinit/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 1'bX;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 1'bZ;
end
always @( posedge clk, posedge en )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 1'bx;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple_reviewed/zinit/zinit.ys 0 → 100644
read_verilog ../top.v
synth -top top
zinit
tee -o result.log dump
write_verilog synth.v
simple_reviewed/zinit/zinit_failed_to_handle_fail.pat 0 → 100644
ERROR: Failed to handle init bit \\_22_ = 1'0.
simple_reviewed/zinit/zinit_failed_to_handle_fail.ys 0 → 100644
read_verilog ../synth.v
zinit
tee -o result.log dump
write_verilog synth.v
simple_reviewed/zinit/zinit_singleton.ys 0 → 100644
read_verilog ../top.v
synth -top top
zinit -all
tee -o result.log dump
write_verilog synth.v
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment