Minor fixes

backends_reviewed/write_smv/top_fulladder.v

@@ -13,15 +13,11 @@ module top
     cout = 0;
  end
 
-`ifndef BUG
 always @(posedge x) begin
     A <=  y + cin;
 end
 always @(negedge x) begin
     cout <=  y + A;
 end
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule

backends_reviewed/write_xaiger/top.v

@@ -21,7 +21,6 @@ module top
     end
  end
 
-`ifndef BUG
 always @(posedge x) begin
     if ($initstate)
         A <= 0;
@@ -36,8 +35,5 @@ always @(negedge x) begin
     assert(ASSERT);
     assert(s_eventually ASSERT);
 end
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule

backends_reviewed/write_xaiger/top_cant_find_top.v

@@ -21,7 +21,7 @@ module top
     end
  end
 
-`ifndef BUG
+
 always @(posedge x) begin
     if ($initstate)
         A <= 0;
@@ -36,9 +36,6 @@ always @(negedge x) begin
     assert(ASSERT);
     assert(s_eventually ASSERT);
 end
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule
 

backends_reviewed/write_xaiger/top_fulladder.v

@@ -13,15 +13,12 @@ module top
     cout = 0;
  end
 
-`ifndef BUG
+
 always @(posedge x) begin
     A <=  y + cin;
 end
 always @(negedge x) begin
     cout <=  y + A;
 end
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule

backends_reviewed/write_xaiger/top_mem.v

@@ -16,11 +16,7 @@ module top
 	// Port A
 	always @ (posedge clka)
 	begin
-`ifndef BUG        
 		if (we_a)
-`else        
-		if (we_b) 
-`endif
 		begin
 			ram[addr_a] <= data_a;
 			q_a <= data_a;
@@ -34,11 +30,7 @@ module top
 	// Port B
 	always @ (posedge clkb)
 	begin
-`ifndef BUG        
 		if (we_b)
-`else        
-		if (we_a) 
-`endif
 		begin
 			ram[addr_b] <= data_b;
 			q_b <= data_b;