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yosys-tests
Commit 96573b52 by Eddie Hung
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Add TEST14 with Xilinx examples from UG901

parent 2a40011a
Showing with 125 additions and 32 deletions
architecture/run.sh
......@@ -54,10 +54,11 @@ elif [ "$1" = "synth_sf2" ]; then
elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_xilinx_srl" ]; then
iverilog -DTEST1 synth1.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
for i in {2..13}; do
iverilog -DTEST1 synth1.v -o testbench ../testbench.v -I.. ../top.v ../lfsr.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
for i in {2..14}; do
run
iverilog -DTEST$i synth$i.v -o testbench ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
yosys -ql yosys.log -p "script ../yosys.ys TEST$i"
iverilog -DTEST$i synth$i.v -o testbench ../testbench.v -I.. ../top.v ../lfsr.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
done
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
......
architecture/scripts/synth_xilinx_srl.ys
script ../test1.ys
design -reset
script ../test2.ys
design -reset
script ../test3.ys
design -reset
script ../test4.ys
design -reset
script ../test5.ys
design -reset
script ../test6.ys
design -reset
script ../test7.ys
design -reset
script ../test8.ys
design -reset
script ../test9.ys
design -reset
script ../test10.ys
design -reset
script ../test11.ys
design -reset
script ../test12.ys
design -reset
script ../test13.ys
script ../yosys.ys TEST1
architecture/synth_xilinx_srl/test12.ys
read_verilog -icells -DTEST12 ../top.v
read_verilog ../lfsr.v
synth_xilinx
rename -top synth
cd synth;
write_verilog -selected synth12.v
cd synth; cd lfsr[0].sr; flatten; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
cd synth; cd lfsr[1].sr; flatten; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
......@@ -136,6 +135,7 @@ cd synth; cd lfsr[126].sr; flatten; select t:FD* -assert-max 3; select t:SRL* -a
cd synth; cd lfsr[127].sr; flatten; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
cd synth; cd lfsr[128].sr; flatten; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
cd synth; cd lfsr[129].sr; flatten; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
cd synth; cd lfsr[130].sr; flatten; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
cd synth; flatten
clean -purge
......
architecture/synth_xilinx_srl/test14.ys 0 → 100644
read_verilog -icells -DTEST14 ../top.v
read_verilog ../ug901.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth14.v
# Check that non chain users block SRLs
cd synth; cd sr0; select t:SRLC32E -assert-count 1
cd synth; cd sr1; select t:SRLC32E -assert-count 1
cd synth; cd sr2; select t:SRLC32E -assert-count 1
architecture/synth_xilinx_srl/top.v
......@@ -61,6 +61,12 @@ generate
shift_reg #(.depth(128), .output_xor(1)) sr_fixed_length_other_users_xor(clk, a[2], r, /*l*/, z[2], /* state */);
shift_reg #(.depth(128), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0), .output_xor(1)) sr_var_length_other_users_xor(clk, a[3], e, l[$clog2(128)-1:0], z[3], /* state */);
assign z[`N-1:4] = 'b0; // Suppress no driver warning
`elsif TEST14
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
shift_registers_0 sr0 (.clk(clk), .clken(e), .SI(a[0]), .SO(z[0]));
shift_registers_1 sr1 (.clk(clk), .clken(e), .SI(a[1]), .SO(z[1]));
dynamic_shift_register_1 sr2 (.CLK(clk), .CE(e), .SEL(l[4:0]), .SI(a[2]), .DO(z[2]));
assign z[`N-1:3] = 'b0; // Suppress no driver warning
`endif
endgenerate
endmodule
......@@ -171,5 +177,3 @@ generate
end
endgenerate
endmodule
`include "lfsr.v"
architecture/synth_xilinx_srl/ug901.v 0 → 100644
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 8-bit Shift Register
// Rising edge clock
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk)
begin
if (clken)
shreg <= {shreg[WIDTH-2:0], SI};
end
assign SO = shreg[WIDTH-1];
endmodule
// 32-bit Shift Register
// Rising edge clock
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
integer i;
always @(posedge clk)
begin
if (clken)
begin
for (i = 0; i < WIDTH-1; i = i+1)
shreg[i+1] <= shreg[i];
shreg[0] <= SI;
end
end
assign SO = shreg[WIDTH-1];
endmodule
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
input [SELWIDTH-1:0] SEL;
output DO;
localparam DATAWIDTH = 2**SELWIDTH;
reg [DATAWIDTH-1:0] data;
assign DO = data[SEL];
always @(posedge CLK)
begin
if (CE == 1'b1)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
architecture/synth_xilinx_srl/yosys.ys 0 → 100644
TEST1:
script ../test1.ys
TEST2:
script ../test2.ys
TEST3:
script ../test3.ys
TEST4:
script ../test4.ys
TEST5:
script ../test5.ys
TEST6:
script ../test6.ys
TEST7:
script ../test7.ys
TEST8:
script ../test8.ys
TEST9:
script ../test9.ys
TEST10:
script ../test10.ys
TEST11:
script ../test11.ys
TEST12:
script ../test12.ys
TEST13:
script ../test13.ys
TEST14:
script ../test14.ys
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