Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
Commits
944233e0
Unverified
Commit
944233e0
authored
Apr 15, 2020
by
Miodrag Milanović
Committed by
GitHub
Apr 15, 2020
Browse files
Options
Browse Files
Download
Plain Diff
Merge pull request #89 from YosysHQ/qbfsat
Qbfsat
parents
29d19df1
dccd674c
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
1 additions
and
1 deletions
+1
-1
misc/qbfsat/qbfsat_solnfile3.ys
+1
-1
No files found.
misc/qbfsat/qbfsat_solnfile3.ys
View file @
944233e0
...
@@ -3,7 +3,7 @@ logger -expect log "Eval result: \\out = 8'00001000." 1
...
@@ -3,7 +3,7 @@ logger -expect log "Eval result: \\out = 8'00001000." 1
read_verilog -formal <<EOT
read_verilog -formal <<EOT
module const_mul(out);
module const_mul(out);
wire [7:0] h;
wire [7:0] h
= $anyconst
;
output [7:0] out;
output [7:0] out;
assign out = h[7]? h[6:0] * 3 : h[6:0] * 4;
assign out = h[7]? h[6:0] * 3 : h[6:0] * 4;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment