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yosys-tests
Commit 8e545596 by Eddie Hung
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Rename -minmuxf to -widemux

parent f05e498e
Showing with 1 additions and 1 deletions
architecture/synth_xilinx_mux/run-test.sh
...@@ -22,7 +22,7 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm ...@@ -22,7 +22,7 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
python3 generate_small.py python3 generate_small.py
python3 generate_large.py python3 generate_large.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'synth_xilinx -abc9 -minmuxf 5' -l ../../../../../techlibs/xilinx/cells_sim.v" ${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'synth_xilinx -abc9 -widemux 5' -l ../../../../../techlibs/xilinx/cells_sim.v"
python3 ../assert_area.py > assert_area.ys python3 ../assert_area.py > assert_area.ys
yosys -q assert_area.ys yosys -q assert_area.ys
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