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lvzhengyang
yosys-tests
Commits
894bcf1a
Commit
894bcf1a
authored
Jan 03, 2020
by
Miodrag Milanovic
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bram -> lutram
parent
db934e4d
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architecture/synth_anlogic/anlogic_determine_init_eqn.ys
+1
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architecture/synth_ecp5/ecp5_ffinit.ys
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architecture/synth_anlogic/anlogic_determine_init_eqn.ys
View file @
894bcf1a
...
...
@@ -5,7 +5,7 @@ flatten
tribuf -logic
deminout
synth -run coarse
memory_bram -rules +/anlogic/
d
rams.txt
memory_bram -rules +/anlogic/
lut
rams.txt
techmap -map +/anlogic/drams_map.v
#anlogic_determine_init
opt -fast -mux_undef -undriven -fine
...
...
architecture/synth_ecp5/ecp5_ffinit.ys
View file @
894bcf1a
...
...
@@ -5,7 +5,7 @@ flatten
tribuf -logic
deminout
synth -run coarse
memory_bram -rules +/ecp5/
bram
.txt
memory_bram -rules +/ecp5/
lutrams
.txt
techmap -map +/ecp5/brams_map.v
opt -fast -mux_undef -undriven -fine
techmap -map +/techmap.v -map +/ecp5/arith_map.v
...
...
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