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yosys-tests
Commit 88bf0406 by Eddie Hung
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Merge remote-tracking branch 'origin/master' into more_bigsim

parents fc235516 e5dabce1
Showing with 4861 additions and 1286 deletions
architecture/Makefile
......@@ -71,6 +71,7 @@ $(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_b
$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
$(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
endif
#greenpak4
......
architecture/run.sh
......@@ -2,7 +2,6 @@
set -x
test -d $1
test -f scripts/$2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
......@@ -25,7 +24,6 @@ if echo "$1" | grep ".*_error"; then
expected_string="ERROR: Invalid Xilinx -family setting: "
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo FAIL > ${1}_${2}.status
else
......@@ -39,9 +37,15 @@ else
if [ -f ../run-test.sh ]; then
../run-test.sh
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
touch .stamp
exit 0
exit
else
test -f scripts/$2.ys
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
......
architecture/synth_xilinx_mux/assert_area.py 0 → 100755
#!/usr/bin/python3
import glob
import re
import os
re_mux = re.compile(r'mux_(index|case|if_bal|if_unbal)_(\d+)_(\d+)\.v')
area = {}
# 1 2 3 4 5 6 F7 F8
area[2] = [ 0, 0, 1, 0, 0, 0, 0, 0 ]
area[3] = [ 0, 0, 0, 0, 1, 0, 0, 0 ]
area[4] = [ 0, 0, 0, 0, 0, 0, 2, 1 ]
area[5] = [ 0, 0, 1, 0, 0, 0, 2, 1 ]
area[7] = [ 0, 0, 3, 0, 0, 0, 2, 1 ]
area[8] = [ 0, 0, 4, 0, 0, 0, 2, 1 ]
area[9] = [ 0, 0, 3, 0, 1, 0, 2, 1 ]
area[15] = [ 0, 0, 0, 0, 1, 3, 2, 1 ]
area[16] = [ 0, 0, 0, 0, 0, 4, 2, 1 ]
area[17] = [ 0, 0, 1, 0, 0, 4, 2, 1 ]
area[31] = [ 0, 0, 1, 0, 1, 7, 4, 2 ]
area[32] = [ 0, 0, 1, 0, 0, 8, 4, 2 ]
area[33] = [ 0, 0, 0, 0, 1, 8, 4, 2 ]
area[63] = [ 0, 0, 0, 0, 1,15,10, 5 ]
area[64] = [ 0, 0, 0, 0, 0,16,10, 5 ]
area[65] = [ 0, 0, 1, 0, 0,16,10, 5 ]
area[127] = [ 0, 0, 4, 0, 1,31,18, 9 ]
area[128] = [ 0, 0, 4, 0, 0,32,18, 9 ]
area[129] = [ 0, 0, 3, 0, 1,32,18, 9 ]
area[255] = [ 0, 0, 0, 0, 1,67,34,17 ]
area[256] = [ 0, 0, 0, 0, 0,68,34,17 ]
area[257] = [ 0, 0, 1, 0, 0,68,34,17 ]
for fn in glob.glob('*.v'):
m = re_mux.match(fn)
if not m: continue
N,W = map(int, m.group(2,3))
assert N in area
bn,_ = os.path.splitext(fn)
with open(fn, 'a') as f:
assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd; %s";
endmodule
`endif
''' % '; '.join(assert_area), file=f)
architecture/synth_xilinx_mux/run-test.sh 0 → 100755
#!/bin/bash
set -e
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/generate.py -O generate_small.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/common.py -O common.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
python3 generate_small.py
python3 generate_large.py
python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \
synth_xilinx -abc9 -widemux 4; \
design -copy-from __test *; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
# Spot tests for -widemux thresholds
set +e
../../../../../yosys -qp "synth_xilinx -widemux 1" 2> /dev/null
if [ $? -eq 0 ]; then
echo "Expected error"
exit 1
fi
set -e
../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 1 t:MUXF7" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-count 6 t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 6 t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 9; select -assert-none t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 8; select -assert-none t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 7; select -assert-count 15 t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 6; select -assert-count 15 t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 18; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 17; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 16; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 15; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
architecture/synth_xilinx_srl/generate.py
#!/usr/bin/python3
import re, glob
N = 131
def assert_static_area(fp, i, name):
if i < 3:
srl32,srl16,fd = (0,0,i)
else:
srl32 = i // 32
if (i % 32) == 0:
srl16 = 0
fd = 0
elif (i % 32) == 1:
srl16 = 0
fd = 1
elif (i % 32) <= 17:
srl16 = 1
fd = (i % 32) - 16
else:
srl32 += 1
srl16 = 0
fd = 0
fp.write('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; cd {3}_{4}; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
'''.format(fd, srl16, srl32, name, i))
def assert_dynamic_area(fp, i, name):
if i < 3:
srl32,srl16,fd = (0,0,i)
lut3 = 1 if i > 1 else 0
lut5 = 0
else:
srl32 = i // 32
if (i % 128) == 0 or (i % 32) == 0:
srl16 = 0
fd = 0
elif (i % 128) == 1:
srl16 = 0
fd = 1
elif (i % 32) <= 16:
srl16 = 1
fd = 0
else:
srl32 += 1
srl16 = 0
fd = 0
lut3 = 1 if i > 128 and i < 257 else 0
lut5 = 1 if i > 256 else 0
muxf8 = (srl32+srl16) // 4
if ((srl32 + srl16) % 4) == 0:
muxf7 = muxf8 * 2
elif ((srl32 + srl16) % 4) == 3:
muxf8 += 1
muxf7 = muxf8 * 2
else:
muxf7 = (srl32+srl16) // 2
fp.write('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd; select t:FD* -assert-count {0}; select t:SRL16E -assert-count {1}; select t:SRLC32E -assert-count {2}; select t:MUXF7 -assert-count {3}; select t:MUXF8 -assert-count {4}; select t:LUT3 -assert-count {5}; select t:LUT5 -assert-count {6}; cd {7}_{8}; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT3 t:LUT5 %% %n t:* %i -assert-none";
endmodule
`endif
'''.format(fd, srl16, srl32, muxf7, muxf8, lut3, lut5, name, i))
# Test 1: pos_clk_no_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test1_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test1_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -20,11 +87,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test1')
# Test 2: pos_clk_with_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test2_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test2_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -39,11 +108,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test2')
# Test 3: pos_clk_with_enable_with_init_inferred
for i in range(1,N+1):
with open('test3_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test3_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -65,11 +136,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test3')
# Test 4: neg_clk_no_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test4_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test4_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -84,11 +157,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test4')
# Test 5: neg_clk_no_enable_no_init_inferred
for i in range(1,N+1):
with open('test5_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test5_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -107,11 +182,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test5')
# Test 6: neg_clk_with_enable_with_init_inferred
for i in range(1,N+1):
with open('test6_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test6_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -133,11 +210,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test6')
# Test 10: pos_clk_no_enable_no_init_not_inferred_var_len
for i in range(1,N+1):
with open('test10_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test10_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -154,11 +233,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_dynamic_area(fp, i, 'test10')
# Test 11: neg_clk_with_enable_with_init_inferred_var_len
for i in range(1,N+1):
with open('test11_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test11_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -180,11 +261,30 @@ generate
endgenerate
endmodule
'''.format(i))
assert_dynamic_area(fp, i, 'test11')
import lfsr_area
re_lfsr = re.compile(r'lfsr_(\d+)\.v')
for fn in glob.glob('lfsr_*.v'):
m = re_lfsr.match(fn)
if not m: continue
W = int(m.group(1))
with open(fn, 'a') as f:
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "%s";
endmodule
`endif
''' % lfsr_area.area[W], file=f)
# Test 15: pos_clk_no_enable_no_init_not_inferred
for i in range(128+1,128+N+1):
with open('test15_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test15_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -199,11 +299,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_static_area(fp, i, 'test15')
# Test 16: neg_clk_with_enable_with_init_inferred_var_len
for i in range(128+1,128+N+1):
with open('test16_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test16_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -225,11 +327,13 @@ generate
endgenerate
endmodule
'''.format(i))
assert_dynamic_area(fp, i, 'test16')
# Test 18: neg_clk_with_enable_with_init_inferred2
for i in range(1,N+1):
with open('test18_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test18_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
......@@ -237,7 +341,7 @@ generate
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
//initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(negedge clk) if (e) int[d][w] <= i[w];
......@@ -250,11 +354,13 @@ generate
assign q = int[depth-1];
endgenerate
endmodule'''.format(i))
assert_static_area(fp, i, 'test18')
# Test 19: pos_clk_with_enable_no_init_inferred2_var_len
for i in range(1,N+1):
with open('test19_%d.v' % i, 'w') as fp:
fp.write('''
(* top *)
module test19_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
......@@ -275,3 +381,4 @@ generate
assign q = int[l];
endgenerate
endmodule'''.format(i))
assert_dynamic_area(fp, i, 'test19')
architecture/synth_xilinx_srl/lfsr.ys deleted 100644 → 0
design -reset; read_verilog lfsr_3.out/lfsr_3_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-count 0; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_4.out/lfsr_4_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_5.out/lfsr_5_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_6.out/lfsr_6_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_7.out/lfsr_7_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_8.out/lfsr_8_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_9.out/lfsr_9_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_10.out/lfsr_10_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_11.out/lfsr_11_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_12.out/lfsr_12_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_13.out/lfsr_13_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_14.out/lfsr_14_syn0.v; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_15.out/lfsr_15_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_16.out/lfsr_16_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_17.out/lfsr_17_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_18.out/lfsr_18_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_19.out/lfsr_19_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_20.out/lfsr_20_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_21.out/lfsr_21_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_22.out/lfsr_22_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_23.out/lfsr_23_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_24.out/lfsr_24_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_25.out/lfsr_25_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_26.out/lfsr_26_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_27.out/lfsr_27_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_28.out/lfsr_28_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_29.out/lfsr_29_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_30.out/lfsr_30_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_31.out/lfsr_31_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_32.out/lfsr_32_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_33.out/lfsr_33_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_34.out/lfsr_34_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_35.out/lfsr_35_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_36.out/lfsr_36_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_37.out/lfsr_37_syn0.v; select t:FD* -assert-count 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_38.out/lfsr_38_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_39.out/lfsr_39_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_40.out/lfsr_40_syn0.v; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_41.out/lfsr_41_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_42.out/lfsr_42_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_43.out/lfsr_43_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_44.out/lfsr_44_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_45.out/lfsr_45_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_46.out/lfsr_46_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_47.out/lfsr_47_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_48.out/lfsr_48_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_49.out/lfsr_49_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_50.out/lfsr_50_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_51.out/lfsr_51_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_52.out/lfsr_52_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_53.out/lfsr_53_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_54.out/lfsr_54_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_55.out/lfsr_55_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_56.out/lfsr_56_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_57.out/lfsr_57_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_58.out/lfsr_58_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_59.out/lfsr_59_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_60.out/lfsr_60_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_61.out/lfsr_61_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_62.out/lfsr_62_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_63.out/lfsr_63_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_64.out/lfsr_64_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_65.out/lfsr_65_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_66.out/lfsr_66_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_67.out/lfsr_67_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_68.out/lfsr_68_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_69.out/lfsr_69_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_70.out/lfsr_70_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_71.out/lfsr_71_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_72.out/lfsr_72_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_73.out/lfsr_73_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_74.out/lfsr_74_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_75.out/lfsr_75_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_76.out/lfsr_76_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_77.out/lfsr_77_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_78.out/lfsr_78_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_79.out/lfsr_79_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_80.out/lfsr_80_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_81.out/lfsr_81_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_82.out/lfsr_82_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_83.out/lfsr_83_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_84.out/lfsr_84_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_85.out/lfsr_85_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_86.out/lfsr_86_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_87.out/lfsr_87_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_88.out/lfsr_88_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_89.out/lfsr_89_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_90.out/lfsr_90_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_91.out/lfsr_91_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_92.out/lfsr_92_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_93.out/lfsr_93_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_94.out/lfsr_94_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_95.out/lfsr_95_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_96.out/lfsr_96_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_97.out/lfsr_97_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_98.out/lfsr_98_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_99.out/lfsr_99_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_100.out/lfsr_100_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_101.out/lfsr_101_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_102.out/lfsr_102_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_103.out/lfsr_103_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_104.out/lfsr_104_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_105.out/lfsr_105_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_106.out/lfsr_106_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_107.out/lfsr_107_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_108.out/lfsr_108_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_109.out/lfsr_109_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_110.out/lfsr_110_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_111.out/lfsr_111_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_112.out/lfsr_112_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_113.out/lfsr_113_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_114.out/lfsr_114_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_115.out/lfsr_115_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_116.out/lfsr_116_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_117.out/lfsr_117_syn0.v; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_118.out/lfsr_118_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_119.out/lfsr_119_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_120.out/lfsr_120_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_121.out/lfsr_121_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_122.out/lfsr_122_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_123.out/lfsr_123_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_124.out/lfsr_124_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_125.out/lfsr_125_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_126.out/lfsr_126_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_127.out/lfsr_127_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_128.out/lfsr_128_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_129.out/lfsr_129_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_130.out/lfsr_130_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_131.out/lfsr_131_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_132.out/lfsr_132_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_133.out/lfsr_133_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_134.out/lfsr_134_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_135.out/lfsr_135_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_136.out/lfsr_136_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_137.out/lfsr_137_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_138.out/lfsr_138_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_139.out/lfsr_139_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_140.out/lfsr_140_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_141.out/lfsr_141_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_142.out/lfsr_142_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_143.out/lfsr_143_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_144.out/lfsr_144_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_145.out/lfsr_145_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_146.out/lfsr_146_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_147.out/lfsr_147_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_148.out/lfsr_148_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_149.out/lfsr_149_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_150.out/lfsr_150_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_151.out/lfsr_151_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_152.out/lfsr_152_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_153.out/lfsr_153_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_154.out/lfsr_154_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_155.out/lfsr_155_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_156.out/lfsr_156_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_157.out/lfsr_157_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_158.out/lfsr_158_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_159.out/lfsr_159_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_160.out/lfsr_160_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_161.out/lfsr_161_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_162.out/lfsr_162_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_163.out/lfsr_163_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_164.out/lfsr_164_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_165.out/lfsr_165_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_166.out/lfsr_166_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_167.out/lfsr_167_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_168.out/lfsr_168_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/lfsr_area.py 0 → 100644
area = {
3: "cd lfsr_3; select t:FD* -assert-max 3; select t:SRL* -assert-count 0; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
4: "cd lfsr_4; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
5: "cd lfsr_5; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
6: "cd lfsr_6; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
7: "cd lfsr_7; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
8: "cd lfsr_8; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
9: "cd lfsr_9; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
10: "cd lfsr_10; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
11: "cd lfsr_11; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
12: "cd lfsr_12; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
13: "cd lfsr_13; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
14: "cd lfsr_14; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
15: "cd lfsr_15; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
16: "cd lfsr_16; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
17: "cd lfsr_17; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
18: "cd lfsr_18; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
19: "cd lfsr_19; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
20: "cd lfsr_20; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
21: "cd lfsr_21; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
22: "cd lfsr_22; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
23: "cd lfsr_23; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
24: "cd lfsr_24; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
25: "cd lfsr_25; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
26: "cd lfsr_26; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
27: "cd lfsr_27; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
28: "cd lfsr_28; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
29: "cd lfsr_29; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
30: "cd lfsr_30; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
31: "cd lfsr_31; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
32: "cd lfsr_32; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
33: "cd lfsr_33; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
34: "cd lfsr_34; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
35: "cd lfsr_35; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
36: "cd lfsr_36; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
37: "cd lfsr_37; select t:FD* -assert-count 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
38: "cd lfsr_38; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
39: "cd lfsr_39; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
40: "cd lfsr_40; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
41: "cd lfsr_41; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
42: "cd lfsr_42; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
43: "cd lfsr_43; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
44: "cd lfsr_44; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
45: "cd lfsr_45; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
46: "cd lfsr_46; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
47: "cd lfsr_47; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
48: "cd lfsr_48; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
49: "cd lfsr_49; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
50: "cd lfsr_50; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
51: "cd lfsr_51; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
52: "cd lfsr_52; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
53: "cd lfsr_53; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
54: "cd lfsr_54; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
55: "cd lfsr_55; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
56: "cd lfsr_56; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
57: "cd lfsr_57; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
58: "cd lfsr_58; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
59: "cd lfsr_59; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
60: "cd lfsr_60; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
61: "cd lfsr_61; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
62: "cd lfsr_62; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
63: "cd lfsr_63; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
64: "cd lfsr_64; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
65: "cd lfsr_65; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
66: "cd lfsr_66; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
67: "cd lfsr_67; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
68: "cd lfsr_68; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
69: "cd lfsr_69; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
70: "cd lfsr_70; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
71: "cd lfsr_71; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
72: "cd lfsr_72; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
73: "cd lfsr_73; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
74: "cd lfsr_74; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
75: "cd lfsr_75; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
76: "cd lfsr_76; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
77: "cd lfsr_77; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
78: "cd lfsr_78; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
79: "cd lfsr_79; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
80: "cd lfsr_80; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
81: "cd lfsr_81; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
82: "cd lfsr_82; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
83: "cd lfsr_83; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
84: "cd lfsr_84; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
85: "cd lfsr_85; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
86: "cd lfsr_86; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
87: "cd lfsr_87; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
88: "cd lfsr_88; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
89: "cd lfsr_89; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
90: "cd lfsr_90; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
91: "cd lfsr_91; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
92: "cd lfsr_92; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
93: "cd lfsr_93; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
94: "cd lfsr_94; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
95: "cd lfsr_95; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
96: "cd lfsr_96; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
97: "cd lfsr_97; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
98: "cd lfsr_98; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
99: "cd lfsr_99; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
100: "cd lfsr_100; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
101: "cd lfsr_101; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
102: "cd lfsr_102; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
103: "cd lfsr_103; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
104: "cd lfsr_104; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
105: "cd lfsr_105; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
106: "cd lfsr_106; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
107: "cd lfsr_107; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
108: "cd lfsr_108; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
109: "cd lfsr_109; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
110: "cd lfsr_110; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
111: "cd lfsr_111; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
112: "cd lfsr_112; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
113: "cd lfsr_113; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
114: "cd lfsr_114; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
115: "cd lfsr_115; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
116: "cd lfsr_116; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
117: "cd lfsr_117; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
118: "cd lfsr_118; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
119: "cd lfsr_119; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
120: "cd lfsr_120; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
121: "cd lfsr_121; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
122: "cd lfsr_122; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
123: "cd lfsr_123; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
124: "cd lfsr_124; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
125: "cd lfsr_125; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
126: "cd lfsr_126; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
127: "cd lfsr_127; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
128: "cd lfsr_128; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
129: "cd lfsr_129; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
130: "cd lfsr_130; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
131: "cd lfsr_131; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
132: "cd lfsr_132; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
133: "cd lfsr_133; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
134: "cd lfsr_134; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
135: "cd lfsr_135; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
136: "cd lfsr_136; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
137: "cd lfsr_137; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
138: "cd lfsr_138; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
139: "cd lfsr_139; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
140: "cd lfsr_140; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
141: "cd lfsr_141; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
142: "cd lfsr_142; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
143: "cd lfsr_143; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
144: "cd lfsr_144; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
145: "cd lfsr_145; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
146: "cd lfsr_146; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
147: "cd lfsr_147; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
148: "cd lfsr_148; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
149: "cd lfsr_149; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
150: "cd lfsr_150; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
151: "cd lfsr_151; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
152: "cd lfsr_152; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
153: "cd lfsr_153; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
154: "cd lfsr_154; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
155: "cd lfsr_155; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
156: "cd lfsr_156; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
157: "cd lfsr_157; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
158: "cd lfsr_158; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
159: "cd lfsr_159; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
160: "cd lfsr_160; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
161: "cd lfsr_161; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
162: "cd lfsr_162; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
163: "cd lfsr_163; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
164: "cd lfsr_164; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
165: "cd lfsr_165; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
166: "cd lfsr_166; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
167: "cd lfsr_167; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
168: "cd lfsr_168; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none",
}
architecture/synth_xilinx_srl/run-test.sh
#!/bin/bash
set -e
shopt -s extglob
OPTIND=1
......@@ -22,10 +23,19 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm
python3 generate_lfsr.py
python3 ../generate.py
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx -retime' -l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../*.ys .
for ys in *.ys; do
yosys -q $ys
done
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx -retime; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
architecture/synth_xilinx_srl/test1.ys deleted 100644 → 0
design -reset; read_verilog test1_1.out/test1_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_2.out/test1_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_3.out/test1_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_4.out/test1_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_5.out/test1_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_6.out/test1_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_7.out/test1_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_8.out/test1_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_9.out/test1_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_10.out/test1_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_11.out/test1_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_12.out/test1_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_13.out/test1_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_14.out/test1_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_15.out/test1_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_16.out/test1_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_17.out/test1_17_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_18.out/test1_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_19.out/test1_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_20.out/test1_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_21.out/test1_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_22.out/test1_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_23.out/test1_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_24.out/test1_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_25.out/test1_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_26.out/test1_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_27.out/test1_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_28.out/test1_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_29.out/test1_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_30.out/test1_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_31.out/test1_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_32.out/test1_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_33.out/test1_33_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_34.out/test1_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_35.out/test1_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_36.out/test1_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_37.out/test1_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_38.out/test1_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_39.out/test1_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_40.out/test1_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_41.out/test1_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_42.out/test1_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_43.out/test1_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_44.out/test1_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_45.out/test1_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_46.out/test1_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_47.out/test1_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_48.out/test1_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_49.out/test1_49_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_50.out/test1_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_51.out/test1_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_52.out/test1_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_53.out/test1_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_54.out/test1_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_55.out/test1_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_56.out/test1_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_57.out/test1_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_58.out/test1_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_59.out/test1_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_60.out/test1_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_61.out/test1_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_62.out/test1_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_63.out/test1_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_64.out/test1_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_65.out/test1_65_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_66.out/test1_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_67.out/test1_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_68.out/test1_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_69.out/test1_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_70.out/test1_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_71.out/test1_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_72.out/test1_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_73.out/test1_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_74.out/test1_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_75.out/test1_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_76.out/test1_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_77.out/test1_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_78.out/test1_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_79.out/test1_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_80.out/test1_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_81.out/test1_81_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_82.out/test1_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_83.out/test1_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_84.out/test1_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_85.out/test1_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_86.out/test1_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_87.out/test1_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_88.out/test1_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_89.out/test1_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_90.out/test1_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_91.out/test1_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_92.out/test1_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_93.out/test1_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_94.out/test1_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_95.out/test1_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_96.out/test1_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_97.out/test1_97_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_98.out/test1_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_99.out/test1_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_100.out/test1_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_101.out/test1_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_102.out/test1_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_103.out/test1_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_104.out/test1_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_105.out/test1_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_106.out/test1_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_107.out/test1_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_108.out/test1_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_109.out/test1_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_110.out/test1_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_111.out/test1_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_112.out/test1_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_113.out/test1_113_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_114.out/test1_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_115.out/test1_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_116.out/test1_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_117.out/test1_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_118.out/test1_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_119.out/test1_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_120.out/test1_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_121.out/test1_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_122.out/test1_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_123.out/test1_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_124.out/test1_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_125.out/test1_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_126.out/test1_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_127.out/test1_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_128.out/test1_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_129.out/test1_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_130.out/test1_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_131.out/test1_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test10.ys deleted 100644 → 0
design -reset; read_verilog test10_1.out/test10_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_2.out/test10_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_3.out/test10_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_4.out/test10_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_5.out/test10_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_6.out/test10_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_7.out/test10_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_8.out/test10_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_9.out/test10_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_10.out/test10_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_11.out/test10_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_12.out/test10_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_13.out/test10_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_14.out/test10_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_15.out/test10_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_16.out/test10_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_17.out/test10_17_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_18.out/test10_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_19.out/test10_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_20.out/test10_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_21.out/test10_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_22.out/test10_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_23.out/test10_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_24.out/test10_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_25.out/test10_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_26.out/test10_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_27.out/test10_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_28.out/test10_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_29.out/test10_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_30.out/test10_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_31.out/test10_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_32.out/test10_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_33.out/test10_33_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_34.out/test10_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_35.out/test10_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_36.out/test10_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_37.out/test10_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_38.out/test10_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_39.out/test10_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_40.out/test10_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_41.out/test10_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_42.out/test10_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_43.out/test10_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_44.out/test10_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_45.out/test10_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_46.out/test10_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_47.out/test10_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_48.out/test10_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_49.out/test10_49_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_50.out/test10_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_51.out/test10_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_52.out/test10_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_53.out/test10_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_54.out/test10_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_55.out/test10_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_56.out/test10_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_57.out/test10_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_58.out/test10_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_59.out/test10_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_60.out/test10_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_61.out/test10_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_62.out/test10_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_63.out/test10_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_64.out/test10_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_65.out/test10_65_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_66.out/test10_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_67.out/test10_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_68.out/test10_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_69.out/test10_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_70.out/test10_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_71.out/test10_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_72.out/test10_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_73.out/test10_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_74.out/test10_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_75.out/test10_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_76.out/test10_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_77.out/test10_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_78.out/test10_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_79.out/test10_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_80.out/test10_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_81.out/test10_81_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_82.out/test10_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_83.out/test10_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_84.out/test10_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_85.out/test10_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_86.out/test10_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_87.out/test10_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_88.out/test10_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_89.out/test10_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_90.out/test10_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_91.out/test10_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_92.out/test10_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_93.out/test10_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_94.out/test10_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_95.out/test10_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_96.out/test10_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_97.out/test10_97_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_98.out/test10_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_99.out/test10_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_100.out/test10_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_101.out/test10_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_102.out/test10_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_103.out/test10_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_104.out/test10_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_105.out/test10_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_106.out/test10_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_107.out/test10_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_108.out/test10_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_109.out/test10_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_110.out/test10_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_111.out/test10_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_112.out/test10_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_113.out/test10_113_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_114.out/test10_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_115.out/test10_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_116.out/test10_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_117.out/test10_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_118.out/test10_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_119.out/test10_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_120.out/test10_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_121.out/test10_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_122.out/test10_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_123.out/test10_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_124.out/test10_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_125.out/test10_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_126.out/test10_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_127.out/test10_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_128.out/test10_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_129.out/test10_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_130.out/test10_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_131.out/test10_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test11.ys deleted 100644 → 0
design -reset; read_verilog test11_1.out/test11_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_2.out/test11_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_3.out/test11_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_4.out/test11_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_5.out/test11_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_6.out/test11_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_7.out/test11_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_8.out/test11_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_9.out/test11_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_10.out/test11_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_11.out/test11_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_12.out/test11_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_13.out/test11_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_14.out/test11_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_15.out/test11_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_16.out/test11_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_17.out/test11_17_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_18.out/test11_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_19.out/test11_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_20.out/test11_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_21.out/test11_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_22.out/test11_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_23.out/test11_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_24.out/test11_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_25.out/test11_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_26.out/test11_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_27.out/test11_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_28.out/test11_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_29.out/test11_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_30.out/test11_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_31.out/test11_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_32.out/test11_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_33.out/test11_33_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_34.out/test11_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_35.out/test11_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_36.out/test11_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_37.out/test11_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_38.out/test11_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_39.out/test11_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_40.out/test11_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_41.out/test11_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_42.out/test11_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_43.out/test11_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_44.out/test11_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_45.out/test11_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_46.out/test11_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_47.out/test11_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_48.out/test11_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_49.out/test11_49_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_50.out/test11_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_51.out/test11_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_52.out/test11_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_53.out/test11_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_54.out/test11_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_55.out/test11_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_56.out/test11_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_57.out/test11_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_58.out/test11_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_59.out/test11_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_60.out/test11_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_61.out/test11_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_62.out/test11_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_63.out/test11_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_64.out/test11_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_65.out/test11_65_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_66.out/test11_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_67.out/test11_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_68.out/test11_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_69.out/test11_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_70.out/test11_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_71.out/test11_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_72.out/test11_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_73.out/test11_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_74.out/test11_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_75.out/test11_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_76.out/test11_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_77.out/test11_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_78.out/test11_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_79.out/test11_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_80.out/test11_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_81.out/test11_81_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_82.out/test11_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_83.out/test11_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_84.out/test11_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_85.out/test11_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_86.out/test11_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_87.out/test11_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_88.out/test11_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_89.out/test11_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_90.out/test11_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_91.out/test11_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_92.out/test11_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_93.out/test11_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_94.out/test11_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_95.out/test11_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_96.out/test11_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_97.out/test11_97_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_98.out/test11_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_99.out/test11_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_100.out/test11_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_101.out/test11_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_102.out/test11_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_103.out/test11_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_104.out/test11_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_105.out/test11_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_106.out/test11_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_107.out/test11_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_108.out/test11_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_109.out/test11_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_110.out/test11_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_111.out/test11_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_112.out/test11_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_113.out/test11_113_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_114.out/test11_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_115.out/test11_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_116.out/test11_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_117.out/test11_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_118.out/test11_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_119.out/test11_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_120.out/test11_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_121.out/test11_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_122.out/test11_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_123.out/test11_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_124.out/test11_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_125.out/test11_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_126.out/test11_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_127.out/test11_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_128.out/test11_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_129.out/test11_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_130.out/test11_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_131.out/test11_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test13.ys deleted 100644 → 0
# Check that non chain users block SRLs
design -reset; read_verilog test13a.out/test13a_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13b.out/test13b_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13c.out/test13c_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13d.out/test13d_syn0.v; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test13a.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_port
(* top *)
module test13a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
......@@ -15,3 +16,9 @@ generate
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13a; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test13b.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_port
(* top *)
module test13b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
......@@ -22,3 +23,9 @@ generate
assign state = int[0];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13b; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test13c.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_xor
(* top *)
module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
......@@ -15,3 +16,9 @@ generate
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13c; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test13d.v
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_xor
module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
(* top *)
module test13d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
......@@ -22,3 +23,9 @@ generate
assign state = {depth{^int[0]}};
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test13d; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test15.ys deleted 100644 → 0
design -reset; read_verilog test15_129.out/test15_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_130.out/test15_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_131.out/test15_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_132.out/test15_132_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_133.out/test15_133_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_134.out/test15_134_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_135.out/test15_135_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_136.out/test15_136_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_137.out/test15_137_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_138.out/test15_138_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_139.out/test15_139_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_140.out/test15_140_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_141.out/test15_141_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_142.out/test15_142_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_143.out/test15_143_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_144.out/test15_144_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_145.out/test15_145_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_146.out/test15_146_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_147.out/test15_147_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_148.out/test15_148_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_149.out/test15_149_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_150.out/test15_150_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_151.out/test15_151_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_152.out/test15_152_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_153.out/test15_153_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_154.out/test15_154_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_155.out/test15_155_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_156.out/test15_156_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_157.out/test15_157_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_158.out/test15_158_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_159.out/test15_159_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_160.out/test15_160_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_161.out/test15_161_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_162.out/test15_162_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_163.out/test15_163_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_164.out/test15_164_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_165.out/test15_165_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_166.out/test15_166_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_167.out/test15_167_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_168.out/test15_168_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_169.out/test15_169_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_170.out/test15_170_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_171.out/test15_171_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_172.out/test15_172_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_173.out/test15_173_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_174.out/test15_174_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_175.out/test15_175_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_176.out/test15_176_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_177.out/test15_177_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_178.out/test15_178_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_179.out/test15_179_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_180.out/test15_180_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_181.out/test15_181_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_182.out/test15_182_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_183.out/test15_183_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_184.out/test15_184_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_185.out/test15_185_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_186.out/test15_186_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_187.out/test15_187_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_188.out/test15_188_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_189.out/test15_189_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_190.out/test15_190_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_191.out/test15_191_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_192.out/test15_192_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_193.out/test15_193_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_194.out/test15_194_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_195.out/test15_195_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_196.out/test15_196_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_197.out/test15_197_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_198.out/test15_198_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_199.out/test15_199_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_200.out/test15_200_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_201.out/test15_201_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_202.out/test15_202_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_203.out/test15_203_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_204.out/test15_204_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_205.out/test15_205_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_206.out/test15_206_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_207.out/test15_207_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_208.out/test15_208_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_209.out/test15_209_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_210.out/test15_210_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_211.out/test15_211_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_212.out/test15_212_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_213.out/test15_213_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_214.out/test15_214_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_215.out/test15_215_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_216.out/test15_216_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_217.out/test15_217_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_218.out/test15_218_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_219.out/test15_219_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_220.out/test15_220_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_221.out/test15_221_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_222.out/test15_222_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_223.out/test15_223_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_224.out/test15_224_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_225.out/test15_225_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_226.out/test15_226_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_227.out/test15_227_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_228.out/test15_228_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_229.out/test15_229_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_230.out/test15_230_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_231.out/test15_231_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_232.out/test15_232_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_233.out/test15_233_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_234.out/test15_234_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_235.out/test15_235_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_236.out/test15_236_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_237.out/test15_237_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_238.out/test15_238_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_239.out/test15_239_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_240.out/test15_240_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_241.out/test15_241_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_242.out/test15_242_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_243.out/test15_243_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_244.out/test15_244_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_245.out/test15_245_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_246.out/test15_246_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_247.out/test15_247_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_248.out/test15_248_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_249.out/test15_249_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_250.out/test15_250_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_251.out/test15_251_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_252.out/test15_252_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_253.out/test15_253_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_254.out/test15_254_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_255.out/test15_255_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_256.out/test15_256_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_257.out/test15_257_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_258.out/test15_258_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_259.out/test15_259_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test16.ys deleted 100644 → 0
design -reset; read_verilog test16_129.out/test16_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_130.out/test16_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_131.out/test16_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_132.out/test16_132_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_133.out/test16_133_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_134.out/test16_134_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_135.out/test16_135_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_136.out/test16_136_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_137.out/test16_137_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_138.out/test16_138_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_139.out/test16_139_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_140.out/test16_140_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_141.out/test16_141_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_142.out/test16_142_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_143.out/test16_143_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_144.out/test16_144_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_145.out/test16_145_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_146.out/test16_146_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_147.out/test16_147_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_148.out/test16_148_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_149.out/test16_149_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_150.out/test16_150_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_151.out/test16_151_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_152.out/test16_152_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_153.out/test16_153_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_154.out/test16_154_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_155.out/test16_155_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_156.out/test16_156_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_157.out/test16_157_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_158.out/test16_158_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_159.out/test16_159_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_160.out/test16_160_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_161.out/test16_161_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_162.out/test16_162_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_163.out/test16_163_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_164.out/test16_164_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_165.out/test16_165_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_166.out/test16_166_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_167.out/test16_167_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_168.out/test16_168_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_169.out/test16_169_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_170.out/test16_170_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_171.out/test16_171_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_172.out/test16_172_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_173.out/test16_173_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_174.out/test16_174_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_175.out/test16_175_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_176.out/test16_176_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_177.out/test16_177_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_178.out/test16_178_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_179.out/test16_179_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_180.out/test16_180_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_181.out/test16_181_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_182.out/test16_182_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_183.out/test16_183_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_184.out/test16_184_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_185.out/test16_185_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_186.out/test16_186_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_187.out/test16_187_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_188.out/test16_188_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_189.out/test16_189_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_190.out/test16_190_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_191.out/test16_191_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_192.out/test16_192_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_193.out/test16_193_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_194.out/test16_194_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_195.out/test16_195_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_196.out/test16_196_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_197.out/test16_197_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_198.out/test16_198_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_199.out/test16_199_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_200.out/test16_200_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_201.out/test16_201_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_202.out/test16_202_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_203.out/test16_203_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_204.out/test16_204_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_205.out/test16_205_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_206.out/test16_206_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_207.out/test16_207_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_208.out/test16_208_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_209.out/test16_209_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_210.out/test16_210_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_211.out/test16_211_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_212.out/test16_212_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_213.out/test16_213_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_214.out/test16_214_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_215.out/test16_215_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_216.out/test16_216_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_217.out/test16_217_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_218.out/test16_218_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_219.out/test16_219_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_220.out/test16_220_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_221.out/test16_221_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_222.out/test16_222_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_223.out/test16_223_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_224.out/test16_224_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_225.out/test16_225_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_226.out/test16_226_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_227.out/test16_227_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_228.out/test16_228_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_229.out/test16_229_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_230.out/test16_230_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_231.out/test16_231_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_232.out/test16_232_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_233.out/test16_233_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_234.out/test16_234_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_235.out/test16_235_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_236.out/test16_236_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_237.out/test16_237_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_238.out/test16_238_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_239.out/test16_239_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_240.out/test16_240_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_241.out/test16_241_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_242.out/test16_242_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_243.out/test16_243_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_244.out/test16_244_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_245.out/test16_245_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_246.out/test16_246_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_247.out/test16_247_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_248.out/test16_248_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_249.out/test16_249_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_250.out/test16_250_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_251.out/test16_251_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_252.out/test16_252_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_253.out/test16_253_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_254.out/test16_254_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_255.out/test16_255_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_256.out/test16_256_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_257.out/test16_257_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT5 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_258.out/test16_258_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT5 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_259.out/test16_259_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT5 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test17.ys deleted 100644 → 0
design -reset; read_verilog test17a.out/test17a_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17b.out/test17b_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17c.out/test17c_syn0.v; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17d.out/test17d_syn0.v; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;
design -reset; read_verilog test17e.out/test17e_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
architecture/synth_xilinx_srl/test17a.v
// Check inference even when not in vector
(* top *)
module test17a (input clk, input i, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
......@@ -13,3 +14,9 @@ generate
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17a; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17b.v
// Check inference even when not in vector
module test17a (input clk, input i, input e, output q);
(* top *)
module test17b (input clk, input i, input e, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17b; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17c.v
// Check inference even when keep attribute specified
(* top *)
module test17c (input clk, input i, input e, output q);
generate
reg a1, a2, a3;
......@@ -8,3 +9,9 @@ generate
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17c; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17d.v
// Check inference even when keep attribute specified
(* top *)
module test17d (input clk, input i, input e, output q);
generate
reg a1, a2;
......@@ -9,3 +10,9 @@ generate
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17d; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test17e.v
// Check inference even when keep attribute specified
module test17d (input clk, input i, input e, output q);
(* top *)
module test17e (input clk, input i, input e, output q);
generate
reg a1, a2;
(* blah *) reg a3;
......@@ -11,3 +12,9 @@ generate
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17e; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;";
endmodule
`endif
architecture/synth_xilinx_srl/test18.ys deleted 100644 → 0
design -reset; read_verilog test18_1.out/test18_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_2.out/test18_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_3.out/test18_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_4.out/test18_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_5.out/test18_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_6.out/test18_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_7.out/test18_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_8.out/test18_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_9.out/test18_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_10.out/test18_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_11.out/test18_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_12.out/test18_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_13.out/test18_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_14.out/test18_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_15.out/test18_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_16.out/test18_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_17.out/test18_17_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_18.out/test18_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_19.out/test18_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_20.out/test18_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_21.out/test18_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_22.out/test18_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_23.out/test18_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_24.out/test18_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_25.out/test18_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_26.out/test18_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_27.out/test18_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_28.out/test18_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_29.out/test18_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_30.out/test18_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_31.out/test18_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_32.out/test18_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_33.out/test18_33_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_34.out/test18_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_35.out/test18_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_36.out/test18_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_37.out/test18_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_38.out/test18_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_39.out/test18_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_40.out/test18_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_41.out/test18_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_42.out/test18_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_43.out/test18_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_44.out/test18_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_45.out/test18_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_46.out/test18_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_47.out/test18_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_48.out/test18_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_49.out/test18_49_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_50.out/test18_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_51.out/test18_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_52.out/test18_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_53.out/test18_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_54.out/test18_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_55.out/test18_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_56.out/test18_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_57.out/test18_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_58.out/test18_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_59.out/test18_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_60.out/test18_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_61.out/test18_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_62.out/test18_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_63.out/test18_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_64.out/test18_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_65.out/test18_65_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_66.out/test18_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_67.out/test18_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_68.out/test18_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_69.out/test18_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_70.out/test18_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_71.out/test18_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_72.out/test18_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_73.out/test18_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_74.out/test18_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_75.out/test18_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_76.out/test18_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_77.out/test18_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_78.out/test18_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_79.out/test18_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_80.out/test18_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_81.out/test18_81_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_82.out/test18_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_83.out/test18_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_84.out/test18_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_85.out/test18_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_86.out/test18_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_87.out/test18_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_88.out/test18_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_89.out/test18_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_90.out/test18_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_91.out/test18_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_92.out/test18_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_93.out/test18_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_94.out/test18_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_95.out/test18_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_96.out/test18_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_97.out/test18_97_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_98.out/test18_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_99.out/test18_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_100.out/test18_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_101.out/test18_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_102.out/test18_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_103.out/test18_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_104.out/test18_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_105.out/test18_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_106.out/test18_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_107.out/test18_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_108.out/test18_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_109.out/test18_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_110.out/test18_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_111.out/test18_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_112.out/test18_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_113.out/test18_113_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_114.out/test18_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_115.out/test18_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_116.out/test18_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_117.out/test18_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_118.out/test18_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_119.out/test18_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_120.out/test18_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_121.out/test18_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_122.out/test18_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_123.out/test18_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_124.out/test18_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_125.out/test18_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_126.out/test18_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_127.out/test18_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_128.out/test18_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_129.out/test18_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_130.out/test18_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_131.out/test18_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test19.ys deleted 100644 → 0
design -reset; read_verilog test19_1.out/test19_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_2.out/test19_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_3.out/test19_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_4.out/test19_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_5.out/test19_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_6.out/test19_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_7.out/test19_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_8.out/test19_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_9.out/test19_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_10.out/test19_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_11.out/test19_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_12.out/test19_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_13.out/test19_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_14.out/test19_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_15.out/test19_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_16.out/test19_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_17.out/test19_17_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_18.out/test19_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_19.out/test19_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_20.out/test19_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_21.out/test19_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_22.out/test19_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_23.out/test19_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_24.out/test19_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_25.out/test19_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_26.out/test19_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_27.out/test19_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_28.out/test19_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_29.out/test19_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_30.out/test19_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_31.out/test19_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_32.out/test19_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_33.out/test19_33_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_34.out/test19_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_35.out/test19_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_36.out/test19_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_37.out/test19_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_38.out/test19_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_39.out/test19_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_40.out/test19_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_41.out/test19_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_42.out/test19_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_43.out/test19_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_44.out/test19_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_45.out/test19_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_46.out/test19_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_47.out/test19_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_48.out/test19_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_49.out/test19_49_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_50.out/test19_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_51.out/test19_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_52.out/test19_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_53.out/test19_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_54.out/test19_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_55.out/test19_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_56.out/test19_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_57.out/test19_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_58.out/test19_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_59.out/test19_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_60.out/test19_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_61.out/test19_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_62.out/test19_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_63.out/test19_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_64.out/test19_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_65.out/test19_65_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_66.out/test19_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_67.out/test19_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_68.out/test19_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_69.out/test19_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_70.out/test19_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_71.out/test19_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_72.out/test19_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_73.out/test19_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_74.out/test19_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_75.out/test19_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_76.out/test19_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_77.out/test19_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_78.out/test19_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_79.out/test19_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_80.out/test19_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_81.out/test19_81_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_82.out/test19_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_83.out/test19_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_84.out/test19_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_85.out/test19_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_86.out/test19_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_87.out/test19_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_88.out/test19_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_89.out/test19_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_90.out/test19_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_91.out/test19_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_92.out/test19_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_93.out/test19_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_94.out/test19_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_95.out/test19_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_96.out/test19_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_97.out/test19_97_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_98.out/test19_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_99.out/test19_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_100.out/test19_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_101.out/test19_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_102.out/test19_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_103.out/test19_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_104.out/test19_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_105.out/test19_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_106.out/test19_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_107.out/test19_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_108.out/test19_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_109.out/test19_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_110.out/test19_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_111.out/test19_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_112.out/test19_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_113.out/test19_113_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_114.out/test19_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_115.out/test19_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_116.out/test19_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_117.out/test19_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_118.out/test19_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_119.out/test19_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_120.out/test19_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_121.out/test19_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_122.out/test19_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_123.out/test19_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_124.out/test19_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_125.out/test19_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_126.out/test19_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_127.out/test19_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_128.out/test19_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_129.out/test19_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_130.out/test19_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_131.out/test19_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test20.v
(* top *)
module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
......@@ -18,3 +19,9 @@ generate
assign z = int[depth-1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test20; select t:FD* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test20.ys deleted 100644 → 0
design -reset; read_verilog test20.out/test20_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test21.ys deleted 100644 → 0
# Check that retiming does not infer shift registers
design -reset; read_verilog test21a.out/test21a_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
design -reset; read_verilog test21b.out/test21b_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
architecture/synth_xilinx_srl/test21a.v
(* top *)
module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
genvar d;
wire [depth:0] int;
......@@ -9,3 +10,9 @@ module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i,
endgenerate
assign q = int[depth];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21a; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture/synth_xilinx_srl/test21b.v
(* top *)
module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
reg [depth-1:0] int;
......@@ -14,3 +15,9 @@ module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i,
assign q = int[depth-1];
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21b; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture/synth_xilinx_srl/test6.ys deleted 100644 → 0
design -reset; read_verilog test6_1.out/test6_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_2.out/test6_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_3.out/test6_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_4.out/test6_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_5.out/test6_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_6.out/test6_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_7.out/test6_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_8.out/test6_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_9.out/test6_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_10.out/test6_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_11.out/test6_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_12.out/test6_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_13.out/test6_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_14.out/test6_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_15.out/test6_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_16.out/test6_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_17.out/test6_17_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_18.out/test6_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_19.out/test6_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_20.out/test6_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_21.out/test6_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_22.out/test6_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_23.out/test6_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_24.out/test6_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_25.out/test6_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_26.out/test6_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_27.out/test6_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_28.out/test6_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_29.out/test6_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_30.out/test6_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_31.out/test6_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_32.out/test6_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_33.out/test6_33_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_34.out/test6_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_35.out/test6_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_36.out/test6_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_37.out/test6_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_38.out/test6_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_39.out/test6_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_40.out/test6_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_41.out/test6_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_42.out/test6_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_43.out/test6_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_44.out/test6_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_45.out/test6_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_46.out/test6_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_47.out/test6_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_48.out/test6_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_49.out/test6_49_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_50.out/test6_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_51.out/test6_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_52.out/test6_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_53.out/test6_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_54.out/test6_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_55.out/test6_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_56.out/test6_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_57.out/test6_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_58.out/test6_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_59.out/test6_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_60.out/test6_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_61.out/test6_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_62.out/test6_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_63.out/test6_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_64.out/test6_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_65.out/test6_65_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_66.out/test6_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_67.out/test6_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_68.out/test6_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_69.out/test6_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_70.out/test6_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_71.out/test6_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_72.out/test6_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_73.out/test6_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_74.out/test6_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_75.out/test6_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_76.out/test6_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_77.out/test6_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_78.out/test6_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_79.out/test6_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_80.out/test6_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_81.out/test6_81_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_82.out/test6_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_83.out/test6_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_84.out/test6_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_85.out/test6_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_86.out/test6_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_87.out/test6_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_88.out/test6_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_89.out/test6_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_90.out/test6_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_91.out/test6_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_92.out/test6_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_93.out/test6_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_94.out/test6_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_95.out/test6_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_96.out/test6_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_97.out/test6_97_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_98.out/test6_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_99.out/test6_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_100.out/test6_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_101.out/test6_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_102.out/test6_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_103.out/test6_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_104.out/test6_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_105.out/test6_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_106.out/test6_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_107.out/test6_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_108.out/test6_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_109.out/test6_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_110.out/test6_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_111.out/test6_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_112.out/test6_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_113.out/test6_113_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_114.out/test6_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_115.out/test6_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_116.out/test6_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_117.out/test6_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_118.out/test6_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_119.out/test6_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_120.out/test6_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_121.out/test6_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_122.out/test6_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_123.out/test6_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_124.out/test6_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_125.out/test6_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_126.out/test6_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_127.out/test6_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_128.out/test6_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_129.out/test6_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_130.out/test6_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_131.out/test6_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test7.ys deleted 100644 → 0
# Check that shift registers with resets are not inferred into SRLs
design -reset; read_verilog test7a.out/test7a_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7b.out/test7b_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7c.out/test7c_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7d.out/test7d_syn0.v; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test7a.v
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset
(* top *)
module test7a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -13,3 +14,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7a; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test7b.v
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset
(* top *)
module test7b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -20,3 +21,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7b; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test7c.v
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
(* top *)
module test7c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -15,3 +16,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7c; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test7d.v
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
(* top *)
module test7d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -20,3 +21,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test7d; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test8.v
// Check multi-bit works
// pos_clk_no_enable_no_init_not_inferred_N_width
(* top *)
module test8 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
......@@ -13,3 +14,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test8; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test8.ys deleted 100644 → 0
# Check that wide shift registers are not a problem
read_verilog test8.out/test8_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test9.v
// Check multi-bit works
// neg_clk_no_enable_with_init_with_inferred_N_width
(* top *)
module test9 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
......@@ -20,3 +21,9 @@ generate
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test9; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test9.ys deleted 100644 → 0
read_verilog test9.out/test9_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/ug901.ys deleted 100644 → 0
design -reset; read_verilog ug901a.out/ug901a_syn0.v; select t:SRLC32E -assert-count 1
design -reset; read_verilog ug901b.out/ug901b_syn0.v; select t:SRLC32E -assert-count 1
design -reset; read_verilog ug901c.out/ug901c_syn0.v; select t:SRLC32E -assert-count 1
architecture/synth_xilinx_srl/ug901a.v
......@@ -5,6 +5,7 @@
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
(* top *)
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
......@@ -17,3 +18,9 @@ begin
end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_0; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/ug901b.v
......@@ -5,6 +5,7 @@
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
(* top *)
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
......@@ -23,3 +24,8 @@ end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/ug901c.v
......@@ -3,6 +3,7 @@
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
(* top *)
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
......@@ -17,3 +18,9 @@ always @(posedge CLK)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd dynamic_shift_register_1; select t:SRLC32E -assert-count 1; select t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
backends/Makefile
......@@ -35,7 +35,7 @@ $(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor
$(eval $(call template,write_btor_pmux,write_btor_pmux))
$(eval $(call template,write_btor_and_or,write_btor_and_or))
$(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type write_btor_no_driver))
$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type))
#write_edif
$(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
......@@ -76,7 +76,7 @@ $(eval $(call template,write_simplec_error,write_simplec_no_c_model write_simple
#write_smt2
$(eval $(call template,write_smt2,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_logic,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest))
$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest))
$(eval $(call template,write_smt2_fsm,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_init_assert,write_smt2_init_assert))
$(eval $(call template,write_smt2_reduce,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
......
backends/run.sh
......@@ -33,8 +33,6 @@ if echo "$1" | grep ".*_error"; then
expected_string="ERROR: No top module found."
elif [ "$2" = "write_btor_unsupported_cell_type" ]; then
expected_string="ERROR: Unsupported cell type: "
elif [ "$2" = "write_btor_no_driver" ]; then
expected_string="ERROR: No driver for signal bit "
elif [ "$2" = "write_edif_cyclic_dependency" ]; then
expected_string="ERROR: Cyclic dependency between modules found! Cycle includes module "
elif [ "$2" = "write_edif_constant_nodes" ]; then
......
backends/scripts/write_btor.ys
......@@ -8,6 +8,7 @@ synth -top top
write_btor btor1.btor
design -reset
read_verilog -sv ../top.v
proc_prune
proc_init
proc_mux
proc_dff
......
backends/scripts/write_btor_no_driver.ys deleted 100644 → 0
read_verilog ../top.v
memory
write_btor btor.btor
backends/scripts/write_btor_s.ys
......@@ -7,6 +7,7 @@ synth -top top
write_btor -s btor1.btor
design -reset
read_verilog -sv ../top.v
proc_prune
proc_init
proc_mux
proc_dff
......
backends/scripts/write_btor_v.ys
......@@ -7,6 +7,7 @@ synth -top top
write_btor -v btor1.btor
design -reset
read_verilog -sv ../top.v
proc_prune
proc_init
proc_mux
proc_dff
......
frontends/Makefile
......@@ -27,6 +27,7 @@ $(eval $(call template,read_blif_mux,read_blif read_blif_attr read_blif_buf read
$(eval $(call template,read_blif_pmux,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_tri,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_eblif,read_blif_eblif))
$(eval $(call template,read_blif_error, read_blif_syntax_error read_blif_duplicate_defenition ))
#read_ilang
$(eval $(call template,read_ilang,read_ilang read_ilang_selected))
......@@ -34,6 +35,7 @@ $(eval $(call template,read_ilang_fsm,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_mem,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_mux,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_error,read_ilang_parse_error))
#read_json
$(eval $(call template,read_json,read_json))
......@@ -42,6 +44,7 @@ $(eval $(call template,read_json_logic,read_json))
$(eval $(call template,read_json_mem,read_json_mem))
$(eval $(call template,read_json_mux,read_json))
$(eval $(call template,read_json_tri,read_json))
$(eval $(call template,read_json_error, read_json_nonstring_key read_json_nonarray_bits_attr read_json_unexpected_eof read_json_invalid_direction read_json_no_bits read_json_no_direction read_json_unexpected_char ))
#read_liberty read_liberty_lib
$(eval $(call template,read_liberty,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
......@@ -55,6 +58,7 @@ $(eval $(call template,read_liberty_latch,read_liberty read_liberty_nooverwrite
$(eval $(call template,read_liberty_latch_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_diff_inv,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_tri,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_error, read_liberty_invalid_bus_type read_liberty_unsupp_type_for_bus read_liberty_bus_interface_only_in_lib_mode read_liberty_latch_has_no_data_in read_liberty_miss_func_on_output read_liberty_ff_has_no_next_stage_attr read_liberty_parse_error_in_function read_liberty_cant_resolve_wire_name read_liberty_missing_direction read_liberty_cant_open_input_file read_liberty_redefenition_of_module ))
#read_aiger
$(eval $(call template,read_aiger,read_aiger read_aiger_proc read_aiger_ascii read_aiger_module read_aiger_clk read_aiger_clk_module ))
......@@ -62,6 +66,7 @@ $(eval $(call template,read_aiger_latch,read_aiger_aig))
$(eval $(call template,read_aiger_logic,read_aiger_aig))
$(eval $(call template,read_aiger_ff,read_aiger_aig))
$(eval $(call template,read_aiger_mult,read_aiger_aig))
$(eval $(call template,read_aiger_error, read_aiger_cant_interpret_first_char read_aiger_unsup_aiger_file read_aiger_invalid_aiger_header read_aiger_cant_interpret_as_input read_aiger_cant_interpret_as_and read_aiger_bad_state_property read_aiger_invalid_reset_literal read_aiger_duplicate_definition ))
#read
# read_vhdl87 read_vhdl93 read_vhdl2k read_vhdl2008 read_vhdl - ERROR: This version of Yosys is built without Verific support.
......@@ -72,9 +77,11 @@ $(eval $(call template,read_verilog,read_verilog read_verilog_assert_assumes rea
#verilog_defaults
$(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push verilog_defaults_pop verilog_defaults_clear))
$(eval $(call template,verilog_defaults_error,verilog_defaults_missing_arg verilog_defaults_extra_arg))
#verilog_defines
$(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
$(eval $(call template,verilog_defines_error,verilog_defines_extra_arg))
#verilog_lexer
$(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))
......
frontends/read_aiger_error/aiger_ff1.aiger 0 → 100755
aaga 7 2 1 2 4
2
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_aiger_error/aiger_ff2.aiger 0 → 100755
aag 7 2 1 2 4 a
2
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_aiger_error/aiger_ff3.aiger 0 → 100755
aag 7 2 1 2 4
2 s
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_aiger_error/aiger_ff4.aiger 0 → 100755
aag 7 2 1 2 4
2
4
6 8
6
7f
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_blif_error/blif_e1.blif 0 → 100755
# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
.modell top
.inputs C S[0] S[1]
.outputs Y[0] Y[1] Y[2] Y[3]
.names $false
.names $true
1
.names $undef
.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
.names $false $1\Y[3:0][0]
1 1
.names $false $1\Y[3:0][1]
1 1
.names $false $1\Y[3:0][2]
1 1
.names $false $1\Y[3:0][3]
1 1
.names $procmux$3_Y[0] $0\Y[3:0][0]
1 1
.names $procmux$3_Y[1] $0\Y[3:0][1]
1 1
.names $procmux$3_Y[2] $0\Y[3:0][2]
1 1
.names $procmux$3_Y[3] $0\Y[3:0][3]
1 1
.end
frontends/read_blif_error/blif_seg_fault.blif 0 → 100755
# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
.model top
.inputs C S[0] S[1]
.outputs Y[0] Y[1] Y[2] Y[3]
.names $false
.names $true
1
.names $undef
.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
.names $false $1\Y[3:0][0]
1 1
.names
1 1
.names $false $1\Y[3:0][2]
1 1
.names $false $1\Y[3:0][3]
1 1
.names $procmux$3_Y[0] $0\Y[3:0][0]
1 1
.names $procmux$3_Y[1] $0\Y[3:0][1]
1 1
.names $procmux$3_Y[2] $0\Y[3:0][2]
1 1
.names $procmux$3_Y[3] $0\Y[3:0][3]
1 1
.end
frontends/read_blif_error/eblif_seg_fault.eblif 0 → 100755
.model top
.names a b
.inputs a
.outputs b
.conn a b
.names a b c
11 1
.cname $my_and_gate
.latch a_and_b dff_q re clk 0
.attr my_design.v:42
.end
frontends/read_blif_error/top.v 0 → 100755
module top(C, S, Y);
input C;
input [1:0] S;
output reg [3:0] Y;
initial Y = 0;
always @(posedge C) begin
case (S)
2'b00: Y <= 4'b0001;
2'b01: Y <= 4'b0010;
2'b10: Y <= 4'b0100;
2'b11: Y <= 4'b1000;
endcase
end
endmodule
frontends/read_ilang_error/file.il 0 → 100644
autoidx 15
attribute \cells_not_processed 1
attribute \src "top.v:1"
module \top
attribute \src "top.v:17"
wire $0\B[0:0]
attribute \src "top.v:19"
attribute \unused_bits "1"
wire width 2 $and$top.v:19$4_Y
attribute \src "top.v:18"
wire $logic_and$top.v:18$2_Y
attribute \src "top.v:20"
wire $logic_and$top.v:20$6_Y
attribute \src "top.v:20"
wire $logic_not$top.v:20$5_Y
attribute \src "top.v:18"
wire $logic_or$top.v:18$3_Y
attribute \src "top.v:20"
wire $logic_or$top.v:20$7_Y
attribute \src "top.v:21"
attribute \unused_bits "1"
wire width 2 $or$top.v:21$8_Y
wire $procmux$10_Y
attribute \src "top.v:8"
wire input 5 \A
attribute \init 1'0
attribute \src "top.v:9"
wire output 6 \B
attribute \src "top.v:6"
wire input 4 \clk
attribute \src "top.v:3"
wire width 2 input 1 \x
attribute \src "top.v:4"
wire width 2 input 2 \y
attribute \src "top.v:5"
wire width 2 input 3 \z
attribute \src "top.v:19"
cell $and $and$top.v:19$4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \z
connect \Y $and$top.v:19$4_Y
end
attribute \src "top.v:18"
cell $logic_and $logic_and$top.v:18$2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \y
connect \B \z
connect \Y $logic_and$top.v:18$2_Y
end
attribute \src "top.v:20"
cell $logic_and $logic_and$top.v:20$6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \y
connect \B $logic_not$top.v:20$5_Y
connect \Y $logic_and$top.v:20$6_Y
end
attribute \src "top.v:20"
cell $logic_not $logic_not$top.v:20$5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \z
connect \Y $logic_not$top.v:20$5_Y
end
attribute \src "top.v:18"
cell $logic_or $logic_or$top.v:18$3
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:18$2_Y
connect \Y $logic_or$top.v:18$3_Y
end
attribute \src "top.v:20"
cell $logic_or $logic_or$top.v:20$7
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:20$6_Y
connect \Y $logic_or$top.v:20$7_Y
end
attribute \src "top.v:21"
cell $or $or$top.v:21$8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \x
connect \Y $or$top.v:21$8_Y
end
attribute \src "top.v:17"
cell $dff $procdff$14
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D $0\B[0:0]
connect \Q \B
end
attribute \src "top.v:18"
cell $mux $procmux$10
parameter \WIDTH 1
connect \A \B
connect \B $and$top.v:19$4_Y [0]
connect \S $logic_or$top.v:18$3_Y
connect \Y $procmux$10_Y
end
attribute \src "top.v:20"
cell $mux $procmux$12
parameter \WIDTH 1
connect \A $procmux$10_Y
connect \B $or$top.v:21$8_Y [0]
connect \S $logic_or$top.v:20$7_Y
connect \Y $0\B[0:0]
end
end
frontends/read_ilang_error/ilang.ilang 0 → 100644
# Generated by Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
autoidx 15
attribute \cells_not_processed 1
attribute \src "top.v:1"
module \top
attribute \src "top.v:17"
wire $0\B[0:0]
attribute \src "top.v:19"
attribute \unused_bits "1"
wire width 2 $and$top.v:19$4_Y
attribute \src "top.v:18"
wire $logic_and$top.v:18$2_Y
attribute \src "top.v:20"
wire $logic_and$top.v:20$6_Y
attribute \src "top.v:20"
wire $logic_not$top.v:20$5_Y
attribute \src "top.v:18"
wire $logic_or$top.v:18$3_Y
attribute \src "top.v:20"
wire $logic_or$top.v:20$7_Y
attribute \src "top.v:21"
attribute \unused_bits "1"
wire width 2 $asdfasdfasfor$top.v:21$8_Y
wire $procmux$10_Y
attribute \src "top.v:8"
wire input 5 \A
attribute \init 1'0
attribute \src "top.v:9"
wire output 6 \B
attribute \src "top.v:6"
wire input 4 \clk
attribute \src "top.v:3"
wire width 2 input 1 \x
attribute \src "top.v:4"
wire width 2 input 2 \y
attribute \src "top.v:5"
wire width 2 input 3 \z
attribute \src "top.v:19"
cell $and $and$top.v:19$4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \z
connect \Y $and$top.v:19$4_Y
end
attribute \src "top.v:18"
cell $logic_and $logic_and$top.v:18$2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \y
connect \B \z
connect \Y $logic_and$top.v:18$2_Y
end
attribute \src "top.v:20"
cell $logic_and $logic_and$top.v:20$6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \y
connect \B $logic_not$top.v:20$5_Y
connect \Y $logic_and$top.v:20$6_Y
end
attribute \src "top.v:20"
cell $logic_not $logic_not$top.v:20$5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \z
connect \Y $logic_not$top.v:20$5_Y
end
attribute \src "top.v:18"
cell $logic_or $logic_or$top.v:18$3
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:18$2_Y
connect \Y $logic_or$top.v:18$3_Y
end
attribute \src "top.v:20"
cell $logic_or $logic_or$top.v:20$7
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:20$6_Y
connect \Y $logic_or$top.v:20$7_Y
end
attribute \src "top.v:21"
cell $or $or$top.v:21$8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \x
connect \Y $or$top.v:21$8_Y
end
attribute \src "top.v:17"
cell $dff $procdff$14
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D $0\B[0:0]
connect \Q \B
end
attribute \src "top.v:18"
cell $mux $procmux$10
parameter \WIDTH 1
connect \A \B
connect \B $and$top.v:19$4_Y [0]
connect \S $logic_or$top.v:18$3_Y
connect \Y $procmux$10_Y
end
attribute \src "top.v:20"
cell $mux $procmux$12
parameter \WIDTH 1
connect \A $procmux$10_Y
connect \B $or$top.v:21$8_Y [0]
connect \S $logic_or$top.v:20$7_Y
connect \Y $0\B[0:0]
end
end
frontends/read_ilang_error/testbench.v 0 → 100644
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_comb out_test(.A(patt_B), .B(B));
endmodule
frontends/read_ilang_error/top.v 0 → 100644
module top
(
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_json_error/json1.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"directisson": "inpusdfsdft",
"bitsss": [ a ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:21"
}
},
"A": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
}
frontends/read_json_error/json2.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"directisson": "inpusdfsdft",
"bitsss": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:21"
}
},
"A": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
}
frontends/read_json_error/json3.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"direction": "input",
"bitsss": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:21"
}
},
"A": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
}
frontends/read_json_error/json4.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"direction": "insdfasdfput",
"bits": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:21"
}
},
"A": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
}
frontends/read_json_error/json5.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"direction": "input",
"bits": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:21"
}
},
"A": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
frontends/read_json_error/json6.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"direction": "input",
"bits": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:21"
}
},
"A": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hide_name": 0,
"bissts": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
}
frontends/read_json_error/json7.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"direction": "input",
"bits": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": 8,
"attributes": {
"src": "top.v:21"
}
},
"A": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hisssde_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
}
frontends/read_json_error/json8.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"direction": "input",
"bits": [ 2 ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
"direction": "output",
"bits": [ 5 ]
},
"cout": {
"direction": "output",
"bits": [ 6 ]
}
},
"cells": {
"$add$top.v:18$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:18"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "top.v:21"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
"src": "top.v:20"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "top.v:17"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
"netnames": {
"$0\\A[0:0]": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:17"
}
},
"$0\\cout[0:0]": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:20"
}
},
"$1\\A[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$1\\cout[0:0]": {
"hide_name": 1,
"bits": [ "0" ],
"attributes": {
"src": "top.v:11"
}
},
"$add$top.v:18$2_Y": {
"hide_name": 1,
"bits": [ 7 ],
"attributes": {
"src": "top.v:18"
}
},
"$add$top.v:21$4_Y": {
"hide_name": 1,
"bits": [ 8 ],
"attributes": {
"src": "top.v:21"
}
},
3: {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"init": 0,
"src": "top.v:7"
}
},
"cin": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "top.v:5"
}
},
"cout": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"init": 0,
"src": "top.v:8"
}
},
"x": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "top.v:3"
}
},
"y": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "top.v:4"
}
}
}
}
}
}
frontends/read_liberty_error/lib.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib1.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : 2 ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib2.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!s)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib3.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A*)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib4.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/libff.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "dff";
ff("IQ", "IQN") {
clocked_on : " CLK ";
clear : " CLR ";
}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_error/liblat.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
clear : "CLR" ;}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_error/liblat1.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
data_in : "D" ;
clear : "CLR" ;}
type ( BUS4 ) {
base_type : arraysss ;
data_type : bit ;
bit_width : 4 ;
bit_from : 0 ;
bit_to : 3 ;
downto :false ;
}
bus(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_error/liblat2.lib 0 → 100644
library (ExamBus) {
date : "May 14, 2002";
revision : 2002.05;
bus_naming_style :"%s[%d]";/* Optional; this is the
default */
type (bus4) {
base_type : array;/* Required */
data_type : bit;/* Required if base_type is array */
bit_width : 4;/* Optional; default is 1 */
bit_from : 0;/* Optional MSB; defaults to 0 */
bit_to : 3;/* Optional LSB; defaults to 0 */
downto : false;/* Optional; defaults to false */
}
cell (bused_cell) {
area : 10;
bus (A) {
bus_type : bus4;
direction : input;
capacitance : 3;
pin (A[0:2]) {
capacitance : 2;
}
pin (A[3]) {
capacitance : 2.5;
}
}
bus (B) {
bus_type : bus4;
capacitance : 2;
}
pin (E) {
direction : input ;
capacitance : 2 ;
}
bus(X) {
bus_type : bus4;
direction : output;
capacitance : 1;
pin (X[0:3]) {
function : "A & B’";
timing() {
related_pin : "A B";
/* A[0] and B[0] are related to X[0],
A[1] and B[1] are related to X[1], etc. */
}
}
}
bus (Y) {
bus_type : bus4;
direction : output;
capacitance : 1;
pin (Y[0:3]) {
function : "B";
three_state : "!E";
timing () {
related_pin : "A[0:3] B E";
}
internal_power() {
when: "E" ;
related_pin : B ;
power() {
}
}
internal_power() {
related_pin : B ;
power() {
}
}
}
}
bus (Z) {
bus_type : bus4;
direction : output;
pin (Z[0:1]) {
function : "!A[0:1]";
timing () {
related_pin : "A[0:1]";
}
internal_power() {
related_pin : "A[0:1]";
power() {
}
}
}
pin (Z[2]) {
function : "A[2]";
timing () {
related_pin : "A[2]";
}
internal_power() {
related_pin : "A[0:1]";
power() {
}
}
}
pin (Z[3]) {
function : "!A[3]";
timing () {
related_pin : "A[3]";
}
internal_power() {
related_pin : "A[0:1]";
power() {
}
}
}
}
pin_opposite("Y[0:1]","Z[0:1]");
/* Y[0] is opposite to Z[0], etc. */
pin_equal("Y[2:3] Z[2:3]");
/* Y[2], Y[3], Z[2], and Z[3] are equal */
cell (bused_cell2) {
area : 20;
bus (A) {
bus_type : bus41;
direction : input;
capacitance : 1;
pin (A[0:3]) {
capacitance : 2;
}
pin (A[3]) {
capacitance : 2.5;
}
}
bus (B) {
bus_type : bus4;
direction : input;
capacitance : 2;
}
pin (E) {
direction : input ;
capacitance : 2 ;
bus(X) {
bus_type : bus4;
direction : output;
capacitance : 1;
pin (X[0:3]) {
function : "A & B’";
timing() {
related_pin : "A B";
/* A[0] and B[0] are related to X[0],
A[1] and B[1] are related to X[1], etc. */
}
}
}
}
regression/issue_00449/testbench.v → frontends/read_liberty_error/testbench.v
module testbench;
reg clk;
reg a;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
#5 a = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
#5 a = ~a;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
top uut (
.A(a),
.Y(b)
);
assert_X b_test(.clk(clk), .A(b));
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/run.sh
......@@ -10,34 +10,120 @@ cd $1/work_$2
touch .start
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
# cases where 'syntax error' or other errors are expected
if echo "$1" | grep ".*_error"; then
expected_string=""
#Change checked string for check other errors
if [ "$2" = "read_aiger_cant_interpret_first_char" ]; then
expected_string="ERROR: Line 80: cannot interpret first character"
elif [ "$2" = "read_aiger_unsup_aiger_file" ]; then
expected_string="ERROR: Unsupported AIGER file!"
elif [ "$2" = "read_aiger_invalid_aiger_header" ]; then
expected_string="ERROR: Invalid AIGER header"
elif [ "$2" = "read_aiger_cant_interpret_as_input" ]; then
expected_string="ERROR: Line 2 cannot be interpreted as an input!"
elif [ "$2" = "read_aiger_cant_interpret_as_and" ]; then
expected_string="ERROR: Line 6 cannot be interpreted as an AND!"
elif [ "$2" = "read_aiger_bad_state_property" ]; then
expected_string="ERROR: Line 4 cannot be interpreted as a bad state property!"
elif [ "$2" = "read_aiger_invalid_reset_literal" ]; then
expected_string="ERROR: Line 1 has invalid reset literal for latch!"
elif [ "$2" = "read_aiger_duplicate_definition" ]; then
expected_string="ERROR: Duplicate definition of module top!"
elif [ "$2" = "read_blif_syntax_error" ]; then
expected_string="ERROR: Syntax error in line"
elif [ "$2" = "read_blif_duplicate_defenition" ]; then
expected_string="ERROR: Duplicate definition of module "
elif [ "$2" = "read_ilang_parse_error" ]; then
expected_string="ERROR: Parser error in line "
elif [ "$2" = "read_json_nonstring_key" ]; then
expected_string="ERROR: Unexpected non-string key in JSON dict."
elif [ "$2" = "read_json_nonarray_bits_attr" ]; then
expected_string=" has non-array bits attribute."
elif [ "$2" = "read_json_unexpected_eof" ]; then
expected_string="ERROR: Unexpected EOF in JSON file."
elif [ "$2" = "read_json_invalid_direction" ]; then
expected_string="ERROR: JSON port node 'x' has invalid 'insdfasdfput' direction attribute."
elif [ "$2" = "read_json_no_bits" ]; then
expected_string=" has no bits attribute."
elif [ "$2" = "read_json_no_direction" ]; then
expected_string=" has no direction attribute."
elif [ "$2" = "read_json_unexpected_char" ]; then
expected_string="ERROR: Unexpected character in JSON file: "
elif [ "$2" = "verilog_defaults_missing_arg" ]; then
expected_string="ERROR: Command syntax error: Missing argument."
elif [ "$2" = "verilog_defaults_extra_arg" ]; then
expected_string="ERROR: Command syntax error: Extra argument."
elif [ "$2" = "verilog_defines_extra_arg" ]; then
expected_string="ERROR: Command syntax error: Extra argument."
elif [ "$2" = "read_liberty_invalid_bus_type" ]; then
expected_string="ERROR: Missing or invalid direction for bus B on cell bused_cell."
elif [ "$2" = "read_liberty_unsupp_type_for_bus" ]; then
expected_string="ERROR: Unknown or unsupported type for bus interface D on cell top."
elif [ "$2" = "read_liberty_bus_interface_only_in_lib_mode" ]; then
expected_string="ERROR: Error in cell top: bus interfaces are only supported in -lib mode."
elif [ "$2" = "read_liberty_latch_has_no_data_in" ]; then
expected_string="ERROR: Latch cell top has no data_in and/or enable attribute."
elif [ "$2" = "read_liberty_miss_func_on_output" ]; then
expected_string="ERROR: Missing function on output Y of cell top."
elif [ "$2" = "read_liberty_ff_has_no_next_stage_attr" ]; then
expected_string="ERROR: FF cell top has no next_state and/or clocked_on attribute."
elif [ "$2" = "read_liberty_parse_error_in_function" ]; then
expected_string="ERROR: Parser error in function expr "
elif [ "$2" = "read_liberty_cant_resolve_wire_name" ]; then
expected_string="ERROR: Can't resolve wire name s."
elif [ "$2" = "read_liberty_missing_direction" ]; then
expected_string="ERROR: Missing or invalid direction for pin A on cell top."
elif [ "$2" = "read_liberty_cant_open_input_file" ]; then
expected_string="ERROR: Can't open input file \`../libbbb.lib' for reading: No such file or directory"
elif [ "$2" = "read_liberty_redefenition_of_module" ]; then
expected_string="ERROR: Re-definition of cell/module top!"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo FAIL > ${1}_${2}.status
else
if grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
fi
else
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
sed -i 's/reg =/dummy =/' ./synth.v
fi
sed -i 's/reg =/dummy =/' ./synth.v
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
else
else
COMMON_PREFIX=/usr/local/share/yosys
fi
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
fi
if ! vvp -N testbench > testbench.log 2>&1; then
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
else
echo PASS > ${1}_${2}.status
fi
fi
touch .stamp
frontends/scripts/read_aiger_bad_state_property.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch1.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_cant_interpret_as_and.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff4.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_cant_interpret_as_input.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff3.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_cant_interpret_first_char.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger1.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_duplicate_definition.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_invalid_aiger_header.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff2.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_invalid_reset_literal.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch2.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_unsup_aiger_file.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff1.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_blif_duplicate_defenition.ys 0 → 100755
read_verilog ../top.v
synth -top top
write_blif blif1.blif
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_syntax_error.ys 0 → 100755
read_blif ../blif_e1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_ilang_parse_error.ys 0 → 100644
read_ilang ../ilang.ilang
dump -n -o file1.il
write_verilog synth.v
frontends/scripts/read_json_invalid_direction.ys 0 → 100644
read_json ../json4.json
write_verilog synth.v
frontends/scripts/read_json_no_bits.ys 0 → 100644
read_json ../json3.json
write_verilog synth.v
frontends/scripts/read_json_no_direction.ys 0 → 100644
read_json ../json2.json
write_verilog synth.v
frontends/scripts/read_json_nonarray_bits_attr.ys 0 → 100644
read_json ../json7.json
write_verilog synth.v
frontends/scripts/read_json_nonstring_key.ys 0 → 100644
read_json ../json8.json
write_verilog synth.v
frontends/scripts/read_json_unexpected_char.ys 0 → 100644
read_json ../json1.json
write_verilog synth.v
frontends/scripts/read_json_unexpected_eof.ys 0 → 100644
read_json ../json5.json
write_verilog synth.v
frontends/scripts/read_liberty_bus_interface_only_in_lib_mode.ys 0 → 100644
read_liberty ../liblat1.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_cant_open_input_file.ys 0 → 100644
read_liberty ../libbbb.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_cant_resolve_wire_name.ys 0 → 100644
read_liberty ../lib2.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_ff_has_no_next_stage_attr.ys 0 → 100644
read_liberty ../libff.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_invalid_bus_type.ys 0 → 100644
read_liberty -lib ../liblat2.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_latch_has_no_data_in.ys 0 → 100644
read_liberty ../liblat.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_miss_func_on_output.ys 0 → 100644
read_liberty ../lib4.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_missing_direction.ys 0 → 100644
read_liberty ../lib1.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_parse_error_in_function.ys 0 → 100644
read_liberty ../lib3.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_redefenition_of_module.ys 0 → 100644
read_liberty ../lib.lib
read_liberty ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_unsupp_type_for_bus.ys 0 → 100644
read_liberty -lib ../liblat1.lib
synth -top top
write_verilog synth.v
frontends/scripts/verilog_defaults_extra_arg.ys 0 → 100644
verilog_defaults -push -pop
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defaults_missing_arg.ys 0 → 100644
verilog_defaults
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defines_extra_arg.ys 0 → 100644
verilog_defines -aa
read_verilog
proc
write_verilog synth.v
frontends/verilog_defaults_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defaults_error/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_defaults_error/top1.v 0 → 100644
module top1 (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
endmodule
frontends/verilog_defines_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defines_error/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
regression/Makefile
......@@ -355,8 +355,8 @@ $(eval $(call template,issue_00873,issue_00873))
#issue_00888
$(eval $(call template,issue_00888,issue_00888))
#pr_00896
$(eval $(call template,pr_00896,pr_00896))
#issue_00896
$(eval $(call template,issue_00896,issue_00896))
#issue_00922
$(eval $(call template,issue_00922,issue_00922))
......@@ -406,6 +406,70 @@ $(eval $(call template,issue_00993,issue_00993))
#issue_00997
$(eval $(call template,issue_00997,issue_00997))
#issue_01002
$(eval $(call template,issue_01002,issue_01002))
#issue_01016
$(eval $(call template,issue_01016,issue_01016))
#issue_01022
$(eval $(call template,issue_01022,issue_01022))
#issue_01023
$(eval $(call template,issue_01023,issue_01023))
#issue_01033
$(eval $(call template,issue_01033,issue_01033))
#issue_01034
$(eval $(call template,issue_01034,issue_01034))
#issue_01040
$(eval $(call template,issue_01040,issue_01040))
#issue_01047
$(eval $(call template,issue_01047,issue_01047))
#issue_01063
$(eval $(call template,issue_01063,issue_01063))
#issue_01065
$(eval $(call template,issue_01065,issue_01065))
#issue_01070
$(eval $(call template,issue_01070,issue_01070))
#issue_01084
$(eval $(call template,issue_01084,issue_01084))
#issue_01091
$(eval $(call template,issue_01091,issue_01091))
#issue_01093
$(eval $(call template,issue_01093,issue_01093))
#issue_01115
$(eval $(call template,issue_01115,issue_01115))
#issue_01118
$(eval $(call template,issue_01118,issue_01118))
#issue_01128
$(eval $(call template,issue_01128,issue_01128))
#issue_01131
$(eval $(call template,issue_01131,issue_01131))
#issue_01132
$(eval $(call template,issue_01132,issue_01132))
#issue_01135
$(eval $(call template,issue_01135,issue_01135))
#issue_01144
$(eval $(call template,issue_01144,issue_01144))
.PHONY: all clean
regression/issue_01002/top.v 0 → 100644
module onehot(i_in, o_out);
parameter LG = 7;
localparam WID = (1<<LG);
//
input wire [WID-1:0] i_in;
output reg [LG-1:0] o_out;
//
integer N;
always @(*)
begin
o_out = 0;
for(N=0; N<WID; N=N+1)
begin
if (i_in[N])
o_out = o_out | N[LG-1:0];
end
end
endmodule
regression/issue_01016/top.v 0 → 100644
module mux_x(clk, in, en, out);
input clk, in, en;
output out;
assign out = en ? in : 1'bx;
endmodule // latchx
regression/issue_01022/top.v 0 → 100644
module test(
output logic [31:0] b
);
assign b = '1;
endmodule
regression/issue_01023/top.v 0 → 100644
module mux_case_5_1(i, s, o);
input [4:0] i;
output o;
input [2:0] s;
\$shiftx #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'sd0),
.Y_WIDTH(32'd1)
) _34_ (
.A(i[4]),
.B(),
.Y(o)
);
endmodule
regression/issue_01033/top.v 0 → 100644
module dram(input [3:0] i, output [4:0] o);
`ifdef UNPACKED
reg val [0:0];
`else
reg [0:0] val;
`endif
initial val[0] = 1'h1;
assign o = i + val[0];
endmodule
regression/issue_01034/top.v 0 → 100644
module dram(input [3:0] i, output [4:0] o);
`ifdef UNPACKED
reg val [0:0];
`else
reg [0:0] val;
`endif
initial val[0] = 1'h1;
assign o = i + val[0];
endmodule
regression/issue_01040/top.v 0 → 100644
module dut_sub(input clk, input [32:2] a, output [32:2] a_l);
always @(posedge clk) a_l <= a;
endmodule // dut_sub
module dut(input clk, input[32:2] a, output [32:2] a_l);
dut_sub sub(.clk(clk), .a(a), .a_l(a_l));
endmodule // dut
regression/issue_01047/top.v 0 → 100644
module top (y, w);
output y;
input [2:0] w;
assign y = 1'b1 >> (w * (3'b110));
endmodule
regression/issue_01063/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
endmodule
module middle
(
input x,
input y,
output o
);
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
regression/issue_01065/top.v 0 → 100644
module top(input clk);
wire ce = 1'b1;
reg q = 1'b0;
always @(posedge clk)
if (ce) q <= 1'b0;
(* keep *)
unknown_module u(.i(q));
endmodule
regression/issue_01070/top.v 0 → 100644
module top(input clk, d, output reg q);
wire ce = 1'b1;
always @(negedge clk)
if (ce) q <= d;
endmodule
regression/issue_01084/top.v 0 → 100644
module top;
initial
if (0) $error("ASDF");
endmodule
regression/issue_01091/top.v 0 → 100644
module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {{W{{1'bx}}}};
if (s[0] == 1'b0)
if (s[1] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[1] == 1'b0)
o <= i[2*W+:W];
end
endmodule
regression/issue_01093/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
regression/issue_01115/top.v 0 → 100644
module top(input clk, output [32:0] o);
assign o = 'bx;
endmodule
regression/issue_01118/top.v 0 → 100644
module top(output [3:0] o);
generate
genvar i;
for (i = 3; i >= 0; i = i-1) begin
assign o[i] = 1'b0;
end
endgenerate
endmodule
regression/issue_01128/top.v 0 → 100644
module test (
input i,
output o
);
wire w1;
wire w2;
assign w1 = ~i;
assign w2 = w1;
assign o = ~w2;
endmodule
regression/issue_01131/top.v 0 → 100644
module minimal;
reg [7:0] q;
initial begin
q <= '81;
end
endmodule
regression/issue_01132/top.v 0 → 100644
module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
o <= {{W{{1'bx}}}};
if (s[0] == 1'b0)
if (s[1] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[1] == 1'b0)
o <= i[2*W+:W];
end
endmodule
regression/issue_01135/top.v 0 → 100644
module top(input [7:0] i, output o);
always @*
case (i[6:3])
4: o <= i[0];
3: o <= i[2];
7: o <= i[3];
default: o <= 1'b0;
endcase
endmodule
regression/issue_01144/top.v 0 → 100644
module top(input clk, d, output q);
specify
// Fails:
(posedge clk => (q +: d)) = (3,1);
(/*posedge*/ clk => (q +: d)) = (3,1);
(posedge clk *> (q +: d)) = (3,1);
(/*posedge*/ clk *> (q +: d)) = (3,1);
// Works:
(/*posedge*/ clk => q) = (3,1);
(/*posedge*/ clk *> q) = (3,1);
endspecify
endmodule
regression/run.sh
......@@ -22,7 +22,11 @@ if [ "$1" = "issue_00089" ] ||\
[ "$1" = "issue_00603" ] ||\
[ "$1" = "issue_00635" ] ||\
[ "$1" = "issue_00763" ] ||\
[ "$1" = "issue_00814" ]; then
[ "$1" = "issue_00814" ] ||\
[ "$1" = "issue_01063" ] ||\
[ "$1" = "issue_01093" ] ||\
[ "$1" = "issue_01131" ] ||\
[ "$1" = "issue_01144" ]; then
expected_string="syntax error"
#Change checked string for check other errors
......@@ -38,6 +42,12 @@ if [ "$1" = "issue_00089" ] ||\
expected_string="Invalid nesting"
elif [ "$1" = "issue_00814" ]; then
expected_string="is implicitly declared"
elif [ "$1" = "issue_01063" ]; then
expected_string="Gate cell u_mid8 not found in module top."
elif [ "$1" = "issue_01093" ]; then
expected_string="ERROR: Design has no top module, use the 'hierarchy' command to specify one."
elif [ "$1" = "issue_01131" ]; then
expected_string="ERROR: Value conversion failed"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
......@@ -94,7 +104,24 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00982" ] ||\
[ "$1" = "issue_00987" ] ||\
[ "$1" = "issue_00993" ] ||\
[ "$1" = "issue_00997" ]; then
[ "$1" = "issue_00997" ] ||\
[ "$1" = "issue_01002" ] ||\
[ "$1" = "issue_01016" ] ||\
[ "$1" = "issue_01022" ] ||\
[ "$1" = "issue_01023" ] ||\
[ "$1" = "issue_01033" ] ||\
[ "$1" = "issue_01034" ] ||\
[ "$1" = "issue_01040" ] ||\
[ "$1" = "issue_01047" ] ||\
[ "$1" = "issue_01065" ] ||\
[ "$1" = "issue_01070" ] ||\
[ "$1" = "issue_01084" ] ||\
[ "$1" = "issue_01091" ] ||\
[ "$1" = "issue_01115" ] ||\
[ "$1" = "issue_01118" ] ||\
[ "$1" = "issue_01128" ] ||\
[ "$1" = "issue_01132" ] ||\
[ "$1" = "issue_01135" ]; then
expected_string=""
expected="1"
......@@ -182,6 +209,43 @@ elif [ "$1" = "issue_00502" ] ||\
expected_string="_DFF_P_ 1"
elif [ "$1" = "issue_00997" ]; then
expected_string="h0"
elif [ "$1" = "issue_01002" ]; then
expected_string="Estimated number of LCs: 95"
elif [ "$1" = "issue_01016" ]; then
expected_string="cell \$mux \$ternary\$../top.v:5"
elif [ "$1" = "issue_01022" ]; then
expected_string="connect \\\b 32'11111111111111111111111111111111"
elif [ "$1" = "issue_01023" ]; then
expected_string="Continuing TECHMAP pass"
elif [ "$1" = "issue_01033" ]; then
expected_string="RAM64X1D "
expected="0"
elif [ "$1" = "issue_01034" ]; then
expected_string="FDRE "
expected="0"
elif [ "$1" = "issue_01040" ]; then
expected_string=".subckt dut_sub a\[2\]=a\[2\] a\[3\]=a\[3\] a\[4\]=a\[4\] a\[5\]=a\[5\] a\[6\]=a\[6\]"
elif [ "$1" = "issue_01047" ]; then
expected_string="assign y = ~(w\[0\] | w\[1\]);"
elif [ "$1" = "issue_01065" ]; then
expected_string="Driver-driver conflict for"
expected="0"
elif [ "$1" = "issue_01070" ]; then
expected_string="cell \$_DFF_N_"
elif [ "$1" = "issue_01084" ]; then
expected_string="Successfully finished Verilog frontend"
elif [ "$1" = "issue_01091" ]; then
expected_string="\$_MUX4_ 1"
elif [ "$1" = "issue_01115" ]; then
expected_string="connect \\\o 33'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
elif [ "$1" = "issue_01118" ]; then
expected_string="connect \\\o \[0\] 1'0"
elif [ "$1" = "issue_01128" ]; then
expected_string="\$_BUF_ 1"
elif [ "$1" = "issue_01132" ]; then
expected_string="\$_MUX4_ 1"
elif [ "$1" = "issue_01135" ]; then
expected_string="\$pmux 1"
fi
yosys -ql yosys.log ../../scripts/$2.ys;
......@@ -227,7 +291,7 @@ else
[ "$1" = "issue_00589" ] ||\
[ "$1" = "issue_00628" ]; then
iverilog_adds="$TECHLIBS_PREFIX/ice40/cells_sim.v"
elif [ "$1" = "pr_00896" ]; then
elif [ "$1" = "issue_00896" ]; then
iverilog_adds="$TECHLIBS_PREFIX/ecp5/cells_sim.v"
fi
......@@ -237,6 +301,13 @@ else
touch .stamp
exit 0
fi
# cases where we do not run iverilog
if [ "$1" = "issue_00449" ]; then
echo PASS > ${1}_${2}.status
touch .stamp
exit 0
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
if [ $? != 0 ] ; then
......
regression/scripts/issue_00444.ys
read_verilog -formal ../top.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
......
regression/scripts/issue_01002.ys 0 → 100644
read -sv ../top.v
hierarchy -top onehot -chparam LG 7
tee -a result.log synth_xilinx
regression/scripts/issue_01016.ys 0 → 100644
read_verilog -sv ../top.v
proc
wreduce -keepdc
tee -a result.log dump
regression/scripts/issue_01022.ys 0 → 100644
read_verilog -sv ../top.v
tee -a result.log dump
regression/scripts/issue_01023.ys 0 → 100644
read_verilog -icells ../top.v
tee -a result.log techmap
regression/scripts/issue_01033.ys 0 → 100644
read_verilog ../top.v
tee -a result.log synth_xilinx
regression/scripts/issue_01034.ys 0 → 100644
read_verilog ../top.v
tee -a result.log synth_xilinx -nodram
regression/scripts/issue_01040.ys 0 → 100644
read_verilog ../top.v
synth
write_blif result.log
regression/scripts/issue_01047.ys 0 → 100644
read -formal ../top.v
synth
write_verilog -noattr result.log
regression/scripts/issue_01063.ys 0 → 100644
read -formal ../top.v
proc
fmcombine top u_mid1 u_mid8
regression/scripts/issue_01065.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log opt -fast
regression/scripts/issue_01070.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
simplemap
opt
opt_rmdff
stat
tee -o result.log dump
regression/scripts/issue_01084.ys 0 → 100644
tee -o result.log read_verilog ../top.v
regression/scripts/issue_01091.ys 0 → 100644
read_verilog ../top.v
proc
opt
techmap
muxcover -nopartial
tee -o result.log stat
regression/scripts/issue_01093.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log sim
regression/scripts/issue_01115.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log dump
regression/scripts/issue_01118.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log dump
regression/scripts/issue_01128.ys 0 → 100644
read_verilog ../top.v
insbuf
# select just the $_BUF_ from w1 to w2 as @buf
select -set buf w:w1 %coe1 w:w1 %d
# set the keep attribute for the $_BUF_ from w1 to w2
setattr -set keep 1 @buf
opt_clean
tee -o result.log stat
regression/scripts/issue_01131.ys 0 → 100644
tee -o result.log read_verilog ../top.v
regression/scripts/issue_01132.ys 0 → 100644
read_verilog ../top.v
proc; opt; wreduce; simplemap; muxcover -mux4=150
tee -o result.log stat
regression/scripts/issue_01135.ys 0 → 100644
read_verilog ../top.v
proc; pmux2shiftx -norange; opt -full
tee -o result.log stat
regression/scripts/issue_01144.ys 0 → 100644
read_verilog ../top.v
tee -o result.log stat
simple/scripts/opt_merge_share_all.ys
read_verilog -formal ../top.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
......
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