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yosys-tests
Unverified Commit 823bc5ba by Miodrag Milanović Committed by GitHub
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Merge pull request #24 from YosysHQ/xc7srl 

Supporting tests for Xilinx SRLs -- YosysHQ/yosys#914
parents 61f5ba72 3f4c2bbe
Showing with 1933 additions and 9 deletions
Makefile
......@@ -8,6 +8,10 @@ else
export YOSYS_NOVERIFIC=1
endif
ifeq ($(ENABLE_HEAVY_TESTS),1)
export ENABLE_HEAVY_TESTS=1
endif
all: $(addsuffix /.stamp,$(SUBDIRS))
echo; find * -name "*.status" | sort | xargs grep -H . | sed 's,^, ,; s,.status:,\t,; s,PASS,pass,;' | expand -t100; echo
touch .stamp
......
architecture/Makefile
......@@ -69,6 +69,9 @@ $(eval $(call template,synth_sf2_error,synth_sf2_fully_selected ))
#xilinx
$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl))
$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
endif
#greenpak4
$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
......
architecture/run.sh
......@@ -14,7 +14,7 @@ touch .start
if echo "$1" | grep ".*_error"; then
expected_string=""
#Change checked string for check other errors
# Change checked string for check other errors
if echo "$2" | grep ".*_fully_selected"; then
expected_string="ERROR: This command only operates on fully selected designs!"
elif [ "$2" = "synth_greenpak4_invalid_part" ]; then
......@@ -37,12 +37,17 @@ if echo "$1" | grep ".*_error"; then
fi
else
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
if [ -f ../run-test.sh ]; then
../run-test.sh
touch .stamp
exit 0
else
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
fi
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
......
architecture/synth_xilinx_srl/generate.py 0 → 100755
#!/usr/bin/python3
N = 131
# Test 1: pos_clk_no_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test1_%d.v' % i, 'w') as fp:
fp.write('''
module test1_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
'''.format(i))
# Test 2: pos_clk_with_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test2_%d.v' % i, 'w') as fp:
fp.write('''
module test2_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(e), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
'''.format(i))
# Test 3: pos_clk_with_enable_with_init_inferred
for i in range(1,N+1):
with open('test3_%d.v' % i, 'w') as fp:
fp.write('''
module test3_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(posedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(posedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
'''.format(i))
# Test 4: neg_clk_no_enable_no_init_not_inferred
for i in range(1,N+1):
with open('test4_%d.v' % i, 'w') as fp:
fp.write('''
module test4_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_NP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
'''.format(i))
# Test 5: neg_clk_no_enable_no_init_inferred
for i in range(1,N+1):
with open('test5_%d.v' % i, 'w') as fp:
fp.write('''
module test5_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
if (depth == 1) begin
always @(negedge clk) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
'''.format(i))
# Test 6: neg_clk_with_enable_with_init_inferred
for i in range(1,N+1):
with open('test6_%d.v' % i, 'w') as fp:
fp.write('''
module test6_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
'''.format(i))
# Test 10: pos_clk_no_enable_no_init_not_inferred_var_len
for i in range(1,N+1):
with open('test10_%d.v' % i, 'w') as fp:
fp.write('''
module test10_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
wire [depth-1:0] t;
assign t = int[w][depth:1];
assign q[w] = t[l];
end
endgenerate
endmodule
'''.format(i))
# Test 11: neg_clk_with_enable_with_init_inferred_var_len
for i in range(1,N+1):
with open('test11_%d.v' % i, 'w') as fp:
fp.write('''
module test11_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
endgenerate
endmodule
'''.format(i))
# Test 15: pos_clk_no_enable_no_init_not_inferred
for i in range(128+1,128+N+1):
with open('test15_%d.v' % i, 'w') as fp:
fp.write('''
module test15_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
'''.format(i))
# Test 16: neg_clk_with_enable_with_init_inferred_var_len
for i in range(128+1,128+N+1):
with open('test16_%d.v' % i, 'w') as fp:
fp.write('''
module test16_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
endgenerate
endmodule
'''.format(i))
# Test 18: neg_clk_with_enable_with_init_inferred2
for i in range(1,N+1):
with open('test18_%d.v' % i, 'w') as fp:
fp.write('''
module test18_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(negedge clk) if (e) int[d][w] <= i[w];
end
else begin
always @(negedge clk) if (e) int[d][w] <= int[d-1][w];
end
end
end
assign q = int[depth-1];
endgenerate
endmodule'''.format(i))
# Test 19: pos_clk_with_enable_no_init_inferred2_var_len
for i in range(1,N+1):
with open('test19_%d.v' % i, 'w') as fp:
fp.write('''
module test19_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(posedge clk) if (e) int[d][w] <= i[w];
end
else begin
always @(posedge clk) if (e) int[d][w] <= int[d-1][w];
end
end
end
assign q = int[l];
endgenerate
endmodule'''.format(i))
architecture/synth_xilinx_srl/lfsr.ys 0 → 100644
design -reset; read_verilog lfsr_3.out/lfsr_3_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-count 0; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_4.out/lfsr_4_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_5.out/lfsr_5_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_6.out/lfsr_6_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_7.out/lfsr_7_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_8.out/lfsr_8_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_9.out/lfsr_9_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_10.out/lfsr_10_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_11.out/lfsr_11_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_12.out/lfsr_12_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_13.out/lfsr_13_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_14.out/lfsr_14_syn0.v; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_15.out/lfsr_15_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_16.out/lfsr_16_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_17.out/lfsr_17_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_18.out/lfsr_18_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_19.out/lfsr_19_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_20.out/lfsr_20_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_21.out/lfsr_21_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_22.out/lfsr_22_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_23.out/lfsr_23_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_24.out/lfsr_24_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_25.out/lfsr_25_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_26.out/lfsr_26_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_27.out/lfsr_27_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_28.out/lfsr_28_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_29.out/lfsr_29_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_30.out/lfsr_30_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_31.out/lfsr_31_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_32.out/lfsr_32_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_33.out/lfsr_33_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_34.out/lfsr_34_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_35.out/lfsr_35_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_36.out/lfsr_36_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_37.out/lfsr_37_syn0.v; select t:FD* -assert-count 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_38.out/lfsr_38_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_39.out/lfsr_39_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_40.out/lfsr_40_syn0.v; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_41.out/lfsr_41_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_42.out/lfsr_42_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_43.out/lfsr_43_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_44.out/lfsr_44_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_45.out/lfsr_45_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_46.out/lfsr_46_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_47.out/lfsr_47_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_48.out/lfsr_48_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_49.out/lfsr_49_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_50.out/lfsr_50_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_51.out/lfsr_51_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_52.out/lfsr_52_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_53.out/lfsr_53_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_54.out/lfsr_54_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_55.out/lfsr_55_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_56.out/lfsr_56_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_57.out/lfsr_57_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_58.out/lfsr_58_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_59.out/lfsr_59_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_60.out/lfsr_60_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_61.out/lfsr_61_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_62.out/lfsr_62_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_63.out/lfsr_63_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_64.out/lfsr_64_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_65.out/lfsr_65_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_66.out/lfsr_66_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_67.out/lfsr_67_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_68.out/lfsr_68_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_69.out/lfsr_69_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_70.out/lfsr_70_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_71.out/lfsr_71_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_72.out/lfsr_72_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_73.out/lfsr_73_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_74.out/lfsr_74_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_75.out/lfsr_75_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_76.out/lfsr_76_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_77.out/lfsr_77_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_78.out/lfsr_78_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_79.out/lfsr_79_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_80.out/lfsr_80_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_81.out/lfsr_81_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_82.out/lfsr_82_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_83.out/lfsr_83_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_84.out/lfsr_84_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_85.out/lfsr_85_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_86.out/lfsr_86_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_87.out/lfsr_87_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_88.out/lfsr_88_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_89.out/lfsr_89_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_90.out/lfsr_90_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_91.out/lfsr_91_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_92.out/lfsr_92_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_93.out/lfsr_93_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_94.out/lfsr_94_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_95.out/lfsr_95_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_96.out/lfsr_96_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_97.out/lfsr_97_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_98.out/lfsr_98_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_99.out/lfsr_99_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_100.out/lfsr_100_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_101.out/lfsr_101_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_102.out/lfsr_102_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_103.out/lfsr_103_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_104.out/lfsr_104_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_105.out/lfsr_105_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_106.out/lfsr_106_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_107.out/lfsr_107_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_108.out/lfsr_108_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_109.out/lfsr_109_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_110.out/lfsr_110_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_111.out/lfsr_111_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_112.out/lfsr_112_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_113.out/lfsr_113_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_114.out/lfsr_114_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_115.out/lfsr_115_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_116.out/lfsr_116_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_117.out/lfsr_117_syn0.v; select t:FD* -assert-max 5; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_118.out/lfsr_118_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_119.out/lfsr_119_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_120.out/lfsr_120_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_121.out/lfsr_121_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_122.out/lfsr_122_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_123.out/lfsr_123_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_124.out/lfsr_124_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_125.out/lfsr_125_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_126.out/lfsr_126_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_127.out/lfsr_127_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_128.out/lfsr_128_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_129.out/lfsr_129_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_130.out/lfsr_130_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_131.out/lfsr_131_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_132.out/lfsr_132_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_133.out/lfsr_133_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_134.out/lfsr_134_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_135.out/lfsr_135_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_136.out/lfsr_136_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_137.out/lfsr_137_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_138.out/lfsr_138_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_139.out/lfsr_139_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_140.out/lfsr_140_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_141.out/lfsr_141_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_142.out/lfsr_142_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_143.out/lfsr_143_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_144.out/lfsr_144_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_145.out/lfsr_145_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_146.out/lfsr_146_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_147.out/lfsr_147_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_148.out/lfsr_148_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_149.out/lfsr_149_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_150.out/lfsr_150_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_151.out/lfsr_151_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_152.out/lfsr_152_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_153.out/lfsr_153_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_154.out/lfsr_154_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_155.out/lfsr_155_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_156.out/lfsr_156_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_157.out/lfsr_157_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_158.out/lfsr_158_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_159.out/lfsr_159_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_160.out/lfsr_160_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_161.out/lfsr_161_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_162.out/lfsr_162_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_163.out/lfsr_163_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_164.out/lfsr_164_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_165.out/lfsr_165_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_166.out/lfsr_166_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_167.out/lfsr_167_syn0.v; select t:FD* -assert-max 3; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog lfsr_168.out/lfsr_168_syn0.v; select t:FD* -assert-max 4; select t:SRL* -assert-min 1; select t:LUT* -assert-max 1; select t:FD* t:SRL* t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/run-test.sh 0 → 100755
#!/bin/bash
shopt -s extglob
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
python3 generate_lfsr.py
python3 ../generate.py
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx' -l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="-f 'verilog -noblackbox -icells' -p 'synth_xilinx -retime' -l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../*.ys .
for ys in *.ys; do
yosys -q $ys
done
architecture/synth_xilinx_srl/test1.ys 0 → 100644
design -reset; read_verilog test1_1.out/test1_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_2.out/test1_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_3.out/test1_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_4.out/test1_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_5.out/test1_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_6.out/test1_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_7.out/test1_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_8.out/test1_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_9.out/test1_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_10.out/test1_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_11.out/test1_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_12.out/test1_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_13.out/test1_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_14.out/test1_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_15.out/test1_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_16.out/test1_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_17.out/test1_17_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_18.out/test1_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_19.out/test1_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_20.out/test1_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_21.out/test1_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_22.out/test1_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_23.out/test1_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_24.out/test1_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_25.out/test1_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_26.out/test1_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_27.out/test1_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_28.out/test1_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_29.out/test1_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_30.out/test1_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_31.out/test1_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_32.out/test1_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_33.out/test1_33_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_34.out/test1_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_35.out/test1_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_36.out/test1_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_37.out/test1_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_38.out/test1_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_39.out/test1_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_40.out/test1_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_41.out/test1_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_42.out/test1_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_43.out/test1_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_44.out/test1_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_45.out/test1_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_46.out/test1_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_47.out/test1_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_48.out/test1_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_49.out/test1_49_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_50.out/test1_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_51.out/test1_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_52.out/test1_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_53.out/test1_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_54.out/test1_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_55.out/test1_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_56.out/test1_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_57.out/test1_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_58.out/test1_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_59.out/test1_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_60.out/test1_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_61.out/test1_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_62.out/test1_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_63.out/test1_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_64.out/test1_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_65.out/test1_65_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_66.out/test1_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_67.out/test1_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_68.out/test1_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_69.out/test1_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_70.out/test1_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_71.out/test1_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_72.out/test1_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_73.out/test1_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_74.out/test1_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_75.out/test1_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_76.out/test1_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_77.out/test1_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_78.out/test1_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_79.out/test1_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_80.out/test1_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_81.out/test1_81_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_82.out/test1_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_83.out/test1_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_84.out/test1_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_85.out/test1_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_86.out/test1_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_87.out/test1_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_88.out/test1_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_89.out/test1_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_90.out/test1_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_91.out/test1_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_92.out/test1_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_93.out/test1_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_94.out/test1_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_95.out/test1_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_96.out/test1_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_97.out/test1_97_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_98.out/test1_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_99.out/test1_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_100.out/test1_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_101.out/test1_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_102.out/test1_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_103.out/test1_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_104.out/test1_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_105.out/test1_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_106.out/test1_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_107.out/test1_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_108.out/test1_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_109.out/test1_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_110.out/test1_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_111.out/test1_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_112.out/test1_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_113.out/test1_113_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_114.out/test1_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_115.out/test1_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_116.out/test1_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_117.out/test1_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_118.out/test1_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_119.out/test1_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_120.out/test1_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_121.out/test1_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_122.out/test1_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_123.out/test1_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_124.out/test1_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_125.out/test1_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_126.out/test1_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_127.out/test1_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_128.out/test1_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_129.out/test1_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_130.out/test1_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test1_131.out/test1_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test10.ys 0 → 100644
design -reset; read_verilog test10_1.out/test10_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_2.out/test10_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_3.out/test10_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_4.out/test10_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_5.out/test10_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_6.out/test10_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_7.out/test10_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_8.out/test10_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_9.out/test10_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_10.out/test10_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_11.out/test10_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_12.out/test10_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_13.out/test10_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_14.out/test10_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_15.out/test10_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_16.out/test10_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_17.out/test10_17_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_18.out/test10_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_19.out/test10_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_20.out/test10_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_21.out/test10_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_22.out/test10_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_23.out/test10_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_24.out/test10_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_25.out/test10_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_26.out/test10_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_27.out/test10_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_28.out/test10_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_29.out/test10_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_30.out/test10_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_31.out/test10_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_32.out/test10_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_33.out/test10_33_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_34.out/test10_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_35.out/test10_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_36.out/test10_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_37.out/test10_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_38.out/test10_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_39.out/test10_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_40.out/test10_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_41.out/test10_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_42.out/test10_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_43.out/test10_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_44.out/test10_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_45.out/test10_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_46.out/test10_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_47.out/test10_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_48.out/test10_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_49.out/test10_49_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_50.out/test10_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_51.out/test10_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_52.out/test10_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_53.out/test10_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_54.out/test10_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_55.out/test10_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_56.out/test10_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_57.out/test10_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_58.out/test10_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_59.out/test10_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_60.out/test10_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_61.out/test10_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_62.out/test10_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_63.out/test10_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_64.out/test10_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_65.out/test10_65_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_66.out/test10_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_67.out/test10_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_68.out/test10_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_69.out/test10_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_70.out/test10_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_71.out/test10_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_72.out/test10_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_73.out/test10_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_74.out/test10_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_75.out/test10_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_76.out/test10_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_77.out/test10_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_78.out/test10_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_79.out/test10_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_80.out/test10_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_81.out/test10_81_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_82.out/test10_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_83.out/test10_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_84.out/test10_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_85.out/test10_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_86.out/test10_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_87.out/test10_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_88.out/test10_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_89.out/test10_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_90.out/test10_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_91.out/test10_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_92.out/test10_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_93.out/test10_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_94.out/test10_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_95.out/test10_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_96.out/test10_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_97.out/test10_97_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_98.out/test10_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_99.out/test10_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_100.out/test10_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_101.out/test10_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_102.out/test10_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_103.out/test10_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_104.out/test10_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_105.out/test10_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_106.out/test10_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_107.out/test10_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_108.out/test10_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_109.out/test10_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_110.out/test10_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_111.out/test10_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_112.out/test10_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_113.out/test10_113_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_114.out/test10_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_115.out/test10_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_116.out/test10_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_117.out/test10_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_118.out/test10_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_119.out/test10_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_120.out/test10_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_121.out/test10_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_122.out/test10_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_123.out/test10_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_124.out/test10_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_125.out/test10_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_126.out/test10_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_127.out/test10_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_128.out/test10_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test10_129.out/test10_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_130.out/test10_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test10_131.out/test10_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test11.ys 0 → 100644
design -reset; read_verilog test11_1.out/test11_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_2.out/test11_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_3.out/test11_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_4.out/test11_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_5.out/test11_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_6.out/test11_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_7.out/test11_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_8.out/test11_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_9.out/test11_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_10.out/test11_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_11.out/test11_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_12.out/test11_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_13.out/test11_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_14.out/test11_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_15.out/test11_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_16.out/test11_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_17.out/test11_17_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_18.out/test11_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_19.out/test11_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_20.out/test11_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_21.out/test11_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_22.out/test11_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_23.out/test11_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_24.out/test11_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_25.out/test11_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_26.out/test11_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_27.out/test11_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_28.out/test11_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_29.out/test11_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_30.out/test11_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_31.out/test11_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_32.out/test11_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_33.out/test11_33_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_34.out/test11_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_35.out/test11_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_36.out/test11_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_37.out/test11_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_38.out/test11_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_39.out/test11_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_40.out/test11_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_41.out/test11_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_42.out/test11_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_43.out/test11_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_44.out/test11_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_45.out/test11_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_46.out/test11_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_47.out/test11_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_48.out/test11_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_49.out/test11_49_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_50.out/test11_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_51.out/test11_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_52.out/test11_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_53.out/test11_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_54.out/test11_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_55.out/test11_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_56.out/test11_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_57.out/test11_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_58.out/test11_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_59.out/test11_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_60.out/test11_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_61.out/test11_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_62.out/test11_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_63.out/test11_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_64.out/test11_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_65.out/test11_65_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_66.out/test11_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_67.out/test11_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_68.out/test11_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_69.out/test11_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_70.out/test11_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_71.out/test11_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_72.out/test11_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_73.out/test11_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_74.out/test11_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_75.out/test11_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_76.out/test11_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_77.out/test11_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_78.out/test11_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_79.out/test11_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_80.out/test11_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_81.out/test11_81_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_82.out/test11_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_83.out/test11_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_84.out/test11_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_85.out/test11_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_86.out/test11_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_87.out/test11_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_88.out/test11_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_89.out/test11_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_90.out/test11_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_91.out/test11_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_92.out/test11_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_93.out/test11_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_94.out/test11_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_95.out/test11_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_96.out/test11_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_97.out/test11_97_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_98.out/test11_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_99.out/test11_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_100.out/test11_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_101.out/test11_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_102.out/test11_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_103.out/test11_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_104.out/test11_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_105.out/test11_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_106.out/test11_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_107.out/test11_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_108.out/test11_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_109.out/test11_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_110.out/test11_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_111.out/test11_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_112.out/test11_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_113.out/test11_113_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_114.out/test11_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_115.out/test11_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_116.out/test11_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_117.out/test11_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_118.out/test11_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_119.out/test11_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_120.out/test11_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_121.out/test11_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_122.out/test11_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_123.out/test11_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_124.out/test11_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_125.out/test11_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_126.out/test11_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_127.out/test11_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_128.out/test11_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 %% %n t:* %i -assert-none
design -reset; read_verilog test11_129.out/test11_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_130.out/test11_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test11_131.out/test11_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test13.ys 0 → 100644
# Check that non chain users block SRLs
design -reset; read_verilog test13a.out/test13a_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13b.out/test13b_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13c.out/test13c_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test13d.out/test13d_syn0.v; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test13a.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_port
module test13a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
assign state = int[0][depth:1];
endgenerate
endmodule
architecture/synth_xilinx_srl/test13b.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_port
module test13b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
assign state = int[0];
endgenerate
endmodule
architecture/synth_xilinx_srl/test13c.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_xor
module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
assign state = int[0][depth:1];
endgenerate
endmodule
architecture/synth_xilinx_srl/test13d.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_xor
module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
assign state = {depth{^int[0]}};
endgenerate
endmodule
architecture/synth_xilinx_srl/test15.ys 0 → 100644
design -reset; read_verilog test15_129.out/test15_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_130.out/test15_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_131.out/test15_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_132.out/test15_132_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_133.out/test15_133_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_134.out/test15_134_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_135.out/test15_135_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_136.out/test15_136_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_137.out/test15_137_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_138.out/test15_138_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_139.out/test15_139_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_140.out/test15_140_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_141.out/test15_141_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_142.out/test15_142_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_143.out/test15_143_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_144.out/test15_144_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_145.out/test15_145_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_146.out/test15_146_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_147.out/test15_147_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_148.out/test15_148_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_149.out/test15_149_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_150.out/test15_150_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_151.out/test15_151_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_152.out/test15_152_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_153.out/test15_153_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_154.out/test15_154_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_155.out/test15_155_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_156.out/test15_156_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_157.out/test15_157_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_158.out/test15_158_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_159.out/test15_159_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_160.out/test15_160_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_161.out/test15_161_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_162.out/test15_162_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_163.out/test15_163_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_164.out/test15_164_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_165.out/test15_165_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_166.out/test15_166_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_167.out/test15_167_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_168.out/test15_168_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_169.out/test15_169_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_170.out/test15_170_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_171.out/test15_171_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_172.out/test15_172_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_173.out/test15_173_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_174.out/test15_174_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_175.out/test15_175_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_176.out/test15_176_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_177.out/test15_177_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_178.out/test15_178_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_179.out/test15_179_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_180.out/test15_180_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_181.out/test15_181_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_182.out/test15_182_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_183.out/test15_183_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_184.out/test15_184_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_185.out/test15_185_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_186.out/test15_186_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_187.out/test15_187_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_188.out/test15_188_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_189.out/test15_189_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_190.out/test15_190_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_191.out/test15_191_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_192.out/test15_192_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_193.out/test15_193_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_194.out/test15_194_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_195.out/test15_195_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_196.out/test15_196_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_197.out/test15_197_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_198.out/test15_198_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_199.out/test15_199_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_200.out/test15_200_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_201.out/test15_201_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_202.out/test15_202_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_203.out/test15_203_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_204.out/test15_204_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_205.out/test15_205_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_206.out/test15_206_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_207.out/test15_207_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_208.out/test15_208_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_209.out/test15_209_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_210.out/test15_210_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_211.out/test15_211_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_212.out/test15_212_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_213.out/test15_213_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_214.out/test15_214_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_215.out/test15_215_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_216.out/test15_216_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_217.out/test15_217_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_218.out/test15_218_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_219.out/test15_219_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_220.out/test15_220_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_221.out/test15_221_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_222.out/test15_222_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_223.out/test15_223_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_224.out/test15_224_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_225.out/test15_225_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_226.out/test15_226_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_227.out/test15_227_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_228.out/test15_228_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_229.out/test15_229_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_230.out/test15_230_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_231.out/test15_231_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_232.out/test15_232_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_233.out/test15_233_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_234.out/test15_234_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_235.out/test15_235_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_236.out/test15_236_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_237.out/test15_237_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_238.out/test15_238_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_239.out/test15_239_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_240.out/test15_240_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_241.out/test15_241_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_242.out/test15_242_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_243.out/test15_243_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_244.out/test15_244_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_245.out/test15_245_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_246.out/test15_246_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_247.out/test15_247_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_248.out/test15_248_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_249.out/test15_249_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_250.out/test15_250_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_251.out/test15_251_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_252.out/test15_252_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_253.out/test15_253_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_254.out/test15_254_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_255.out/test15_255_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_256.out/test15_256_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_257.out/test15_257_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_258.out/test15_258_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test15_259.out/test15_259_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test16.ys 0 → 100644
design -reset; read_verilog test16_129.out/test16_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_130.out/test16_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_131.out/test16_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_132.out/test16_132_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_133.out/test16_133_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_134.out/test16_134_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_135.out/test16_135_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_136.out/test16_136_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_137.out/test16_137_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_138.out/test16_138_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_139.out/test16_139_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_140.out/test16_140_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_141.out/test16_141_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_142.out/test16_142_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_143.out/test16_143_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_144.out/test16_144_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_145.out/test16_145_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_146.out/test16_146_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_147.out/test16_147_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_148.out/test16_148_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_149.out/test16_149_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_150.out/test16_150_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_151.out/test16_151_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_152.out/test16_152_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_153.out/test16_153_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_154.out/test16_154_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_155.out/test16_155_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_156.out/test16_156_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_157.out/test16_157_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_158.out/test16_158_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_159.out/test16_159_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_160.out/test16_160_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_161.out/test16_161_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_162.out/test16_162_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_163.out/test16_163_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_164.out/test16_164_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_165.out/test16_165_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_166.out/test16_166_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_167.out/test16_167_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_168.out/test16_168_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_169.out/test16_169_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_170.out/test16_170_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_171.out/test16_171_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_172.out/test16_172_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_173.out/test16_173_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_174.out/test16_174_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_175.out/test16_175_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_176.out/test16_176_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 5; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_177.out/test16_177_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_178.out/test16_178_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_179.out/test16_179_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_180.out/test16_180_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_181.out/test16_181_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_182.out/test16_182_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_183.out/test16_183_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_184.out/test16_184_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_185.out/test16_185_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_186.out/test16_186_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_187.out/test16_187_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_188.out/test16_188_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_189.out/test16_189_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_190.out/test16_190_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_191.out/test16_191_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_192.out/test16_192_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 3; select t:MUXF8 -assert-count 1; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_193.out/test16_193_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_194.out/test16_194_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_195.out/test16_195_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_196.out/test16_196_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_197.out/test16_197_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_198.out/test16_198_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_199.out/test16_199_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_200.out/test16_200_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_201.out/test16_201_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_202.out/test16_202_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_203.out/test16_203_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_204.out/test16_204_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_205.out/test16_205_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_206.out/test16_206_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_207.out/test16_207_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_208.out/test16_208_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 6; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_209.out/test16_209_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_210.out/test16_210_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_211.out/test16_211_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_212.out/test16_212_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_213.out/test16_213_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_214.out/test16_214_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_215.out/test16_215_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_216.out/test16_216_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_217.out/test16_217_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_218.out/test16_218_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_219.out/test16_219_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_220.out/test16_220_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_221.out/test16_221_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_222.out/test16_222_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_223.out/test16_223_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_224.out/test16_224_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_225.out/test16_225_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_226.out/test16_226_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_227.out/test16_227_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_228.out/test16_228_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_229.out/test16_229_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_230.out/test16_230_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_231.out/test16_231_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_232.out/test16_232_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_233.out/test16_233_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_234.out/test16_234_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_235.out/test16_235_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_236.out/test16_236_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_237.out/test16_237_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_238.out/test16_238_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_239.out/test16_239_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_240.out/test16_240_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 7; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_241.out/test16_241_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_242.out/test16_242_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_243.out/test16_243_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_244.out/test16_244_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_245.out/test16_245_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_246.out/test16_246_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_247.out/test16_247_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_248.out/test16_248_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_249.out/test16_249_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_250.out/test16_250_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_251.out/test16_251_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_252.out/test16_252_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_253.out/test16_253_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_254.out/test16_254_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_255.out/test16_255_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_256.out/test16_256_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT3 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_257.out/test16_257_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT5 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_258.out/test16_258_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT5 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
design -reset; read_verilog test16_259.out/test16_259_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 8; select t:MUXF7 -assert-count 4; select t:MUXF8 -assert-count 2; select t:LUT5 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:LUT* t:MUXF* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test17.ys 0 → 100644
design -reset; read_verilog test17a.out/test17a_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17b.out/test17b_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17c.out/test17c_syn0.v; select t:SRL16E -assert-count 2; select t:* t:SRL16E %d -assert-count 0;
design -reset; read_verilog test17d.out/test17d_syn0.v; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:* t:SRL16E %d t:FD* %d -assert-count 0;
design -reset; read_verilog test17e.out/test17e_syn0.v; select t:SRL16E -assert-count 1; select t:* t:SRL16E %d -assert-count 0;
architecture/synth_xilinx_srl/test17a.v 0 → 100644
// Check inference even when not in vector
module test17a (input clk, input i, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) a1 <= i;
always @(posedge clk) a2 <= a1;
always @(posedge clk) a3 <= a2;
always @(posedge clk) a4 <= a3;
always @(posedge clk) a5 <= a4;
always @(posedge clk) a6 <= a5;
always @(posedge clk) a7 <= a6;
always @(posedge clk) a8 <= a7;
assign q = a8;
endgenerate
endmodule
architecture/synth_xilinx_srl/test17b.v 0 → 100644
// Check inference even when not in vector
module test17a (input clk, input i, input e, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
architecture/synth_xilinx_srl/test17c.v 0 → 100644
// Check inference even when keep attribute specified
module test17c (input clk, input i, input e, output q);
generate
reg a1, a2, a3;
(* keep *) reg a4;
reg a5, a6, a7, a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
architecture/synth_xilinx_srl/test17d.v 0 → 100644
// Check inference even when keep attribute specified
module test17d (input clk, input i, input e, output q);
generate
reg a1, a2;
(* keep *) reg a3;
(* keep *) reg a4;
reg a5, a6, a7, a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
architecture/synth_xilinx_srl/test17e.v 0 → 100644
// Check inference even when keep attribute specified
module test17d (input clk, input i, input e, output q);
generate
reg a1, a2;
(* blah *) reg a3;
reg a4, a5, a6;
(* boo *) reg a7;
reg a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
architecture/synth_xilinx_srl/test18.ys 0 → 100644
design -reset; read_verilog test18_1.out/test18_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_2.out/test18_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_3.out/test18_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_4.out/test18_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_5.out/test18_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_6.out/test18_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_7.out/test18_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_8.out/test18_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_9.out/test18_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_10.out/test18_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_11.out/test18_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_12.out/test18_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_13.out/test18_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_14.out/test18_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_15.out/test18_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_16.out/test18_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_17.out/test18_17_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_18.out/test18_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_19.out/test18_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_20.out/test18_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_21.out/test18_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_22.out/test18_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_23.out/test18_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_24.out/test18_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_25.out/test18_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_26.out/test18_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_27.out/test18_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_28.out/test18_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_29.out/test18_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_30.out/test18_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_31.out/test18_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_32.out/test18_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_33.out/test18_33_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_34.out/test18_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_35.out/test18_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_36.out/test18_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_37.out/test18_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_38.out/test18_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_39.out/test18_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_40.out/test18_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_41.out/test18_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_42.out/test18_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_43.out/test18_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_44.out/test18_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_45.out/test18_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_46.out/test18_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_47.out/test18_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_48.out/test18_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_49.out/test18_49_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_50.out/test18_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_51.out/test18_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_52.out/test18_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_53.out/test18_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_54.out/test18_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_55.out/test18_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_56.out/test18_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_57.out/test18_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_58.out/test18_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_59.out/test18_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_60.out/test18_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_61.out/test18_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_62.out/test18_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_63.out/test18_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_64.out/test18_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_65.out/test18_65_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_66.out/test18_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_67.out/test18_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_68.out/test18_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_69.out/test18_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_70.out/test18_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_71.out/test18_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_72.out/test18_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_73.out/test18_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_74.out/test18_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_75.out/test18_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_76.out/test18_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_77.out/test18_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_78.out/test18_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_79.out/test18_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_80.out/test18_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_81.out/test18_81_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_82.out/test18_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_83.out/test18_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_84.out/test18_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_85.out/test18_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_86.out/test18_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_87.out/test18_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_88.out/test18_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_89.out/test18_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_90.out/test18_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_91.out/test18_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_92.out/test18_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_93.out/test18_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_94.out/test18_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_95.out/test18_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_96.out/test18_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_97.out/test18_97_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_98.out/test18_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_99.out/test18_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_100.out/test18_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_101.out/test18_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_102.out/test18_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_103.out/test18_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_104.out/test18_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_105.out/test18_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_106.out/test18_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_107.out/test18_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_108.out/test18_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_109.out/test18_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_110.out/test18_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_111.out/test18_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_112.out/test18_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_113.out/test18_113_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_114.out/test18_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_115.out/test18_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_116.out/test18_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_117.out/test18_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_118.out/test18_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_119.out/test18_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_120.out/test18_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_121.out/test18_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_122.out/test18_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_123.out/test18_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_124.out/test18_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_125.out/test18_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_126.out/test18_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_127.out/test18_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_128.out/test18_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_129.out/test18_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_130.out/test18_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test18_131.out/test18_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test19.ys 0 → 100644
design -reset; read_verilog test19_1.out/test19_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_2.out/test19_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_3.out/test19_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_4.out/test19_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_5.out/test19_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_6.out/test19_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_7.out/test19_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_8.out/test19_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_9.out/test19_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_10.out/test19_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_11.out/test19_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_12.out/test19_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_13.out/test19_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_14.out/test19_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_15.out/test19_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_16.out/test19_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_17.out/test19_17_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_18.out/test19_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_19.out/test19_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_20.out/test19_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_21.out/test19_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_22.out/test19_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_23.out/test19_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_24.out/test19_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_25.out/test19_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_26.out/test19_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_27.out/test19_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_28.out/test19_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_29.out/test19_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_30.out/test19_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_31.out/test19_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_32.out/test19_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_33.out/test19_33_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_34.out/test19_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_35.out/test19_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_36.out/test19_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_37.out/test19_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_38.out/test19_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_39.out/test19_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_40.out/test19_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_41.out/test19_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_42.out/test19_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_43.out/test19_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_44.out/test19_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_45.out/test19_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_46.out/test19_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_47.out/test19_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_48.out/test19_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_49.out/test19_49_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_50.out/test19_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_51.out/test19_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_52.out/test19_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_53.out/test19_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_54.out/test19_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_55.out/test19_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_56.out/test19_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_57.out/test19_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_58.out/test19_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_59.out/test19_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_60.out/test19_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_61.out/test19_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_62.out/test19_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_63.out/test19_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_64.out/test19_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_65.out/test19_65_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_66.out/test19_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_67.out/test19_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_68.out/test19_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_69.out/test19_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_70.out/test19_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_71.out/test19_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_72.out/test19_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_73.out/test19_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_74.out/test19_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_75.out/test19_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_76.out/test19_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_77.out/test19_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_78.out/test19_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_79.out/test19_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_80.out/test19_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_81.out/test19_81_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_82.out/test19_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_83.out/test19_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_84.out/test19_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_85.out/test19_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_86.out/test19_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_87.out/test19_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_88.out/test19_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_89.out/test19_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_90.out/test19_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_91.out/test19_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_92.out/test19_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_93.out/test19_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_94.out/test19_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_95.out/test19_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_96.out/test19_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_97.out/test19_97_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_98.out/test19_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_99.out/test19_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_100.out/test19_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_101.out/test19_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_102.out/test19_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_103.out/test19_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_104.out/test19_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_105.out/test19_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_106.out/test19_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_107.out/test19_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_108.out/test19_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_109.out/test19_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_110.out/test19_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_111.out/test19_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_112.out/test19_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_113.out/test19_113_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_114.out/test19_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_115.out/test19_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_116.out/test19_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_117.out/test19_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_118.out/test19_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_119.out/test19_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_120.out/test19_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_121.out/test19_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_122.out/test19_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_123.out/test19_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_124.out/test19_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_125.out/test19_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_126.out/test19_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_127.out/test19_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_128.out/test19_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_129.out/test19_129_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_130.out/test19_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
design -reset; read_verilog test19_131.out/test19_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test20.v 0 → 100644
module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(negedge clk) if (e) int[d][w] <= i[w];
end
else begin
always @(negedge clk) if (e) int[d][w] <= int[d-1][w];
end
end
end
assign z = int[depth-1];
endgenerate
endmodule
architecture/synth_xilinx_srl/test20.ys 0 → 100644
design -reset; read_verilog test20.out/test20_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test21.ys 0 → 100644
# Check that retiming does not infer shift registers
design -reset; read_verilog test21a.out/test21a_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
design -reset; read_verilog test21b.out/test21b_syn0.v; select t:SRL* -assert-count 0; select t:FD* -assert-min 20
architecture/synth_xilinx_srl/test21a.v 0 → 100644
module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
genvar d;
wire [depth:0] int;
assign int[0] = ^i[width-1:0];
generate
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1]));
end
endgenerate
assign q = int[depth];
endmodule
architecture/synth_xilinx_srl/test21b.v 0 → 100644
module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
reg [depth-1:0] int;
genvar d;
for (d = 0; d < depth; d=d+1)
initial int[d] <= ~(d % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int <= ~^i[width-1:0];
assign q = int;
end
else begin
always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] };
assign q = int[depth-1];
end
endmodule
architecture/synth_xilinx_srl/test6.ys 0 → 100644
design -reset; read_verilog test6_1.out/test6_1_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_2.out/test6_2_syn0.v; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_3.out/test6_3_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_4.out/test6_4_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_5.out/test6_5_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_6.out/test6_6_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_7.out/test6_7_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_8.out/test6_8_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_9.out/test6_9_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_10.out/test6_10_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_11.out/test6_11_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_12.out/test6_12_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_13.out/test6_13_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_14.out/test6_14_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_15.out/test6_15_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_16.out/test6_16_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_17.out/test6_17_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_18.out/test6_18_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_19.out/test6_19_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_20.out/test6_20_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_21.out/test6_21_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_22.out/test6_22_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_23.out/test6_23_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_24.out/test6_24_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_25.out/test6_25_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_26.out/test6_26_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_27.out/test6_27_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_28.out/test6_28_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_29.out/test6_29_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_30.out/test6_30_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_31.out/test6_31_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_32.out/test6_32_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_33.out/test6_33_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_34.out/test6_34_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_35.out/test6_35_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_36.out/test6_36_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_37.out/test6_37_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_38.out/test6_38_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_39.out/test6_39_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_40.out/test6_40_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_41.out/test6_41_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_42.out/test6_42_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_43.out/test6_43_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_44.out/test6_44_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_45.out/test6_45_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_46.out/test6_46_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_47.out/test6_47_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_48.out/test6_48_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_49.out/test6_49_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_50.out/test6_50_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_51.out/test6_51_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_52.out/test6_52_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_53.out/test6_53_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_54.out/test6_54_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_55.out/test6_55_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_56.out/test6_56_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_57.out/test6_57_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_58.out/test6_58_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_59.out/test6_59_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_60.out/test6_60_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_61.out/test6_61_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_62.out/test6_62_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_63.out/test6_63_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_64.out/test6_64_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_65.out/test6_65_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_66.out/test6_66_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_67.out/test6_67_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_68.out/test6_68_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_69.out/test6_69_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_70.out/test6_70_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_71.out/test6_71_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_72.out/test6_72_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_73.out/test6_73_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_74.out/test6_74_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_75.out/test6_75_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_76.out/test6_76_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_77.out/test6_77_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_78.out/test6_78_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_79.out/test6_79_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_80.out/test6_80_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_81.out/test6_81_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_82.out/test6_82_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_83.out/test6_83_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_84.out/test6_84_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_85.out/test6_85_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_86.out/test6_86_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_87.out/test6_87_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_88.out/test6_88_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_89.out/test6_89_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_90.out/test6_90_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_91.out/test6_91_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_92.out/test6_92_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_93.out/test6_93_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_94.out/test6_94_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_95.out/test6_95_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_96.out/test6_96_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_97.out/test6_97_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_98.out/test6_98_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_99.out/test6_99_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_100.out/test6_100_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_101.out/test6_101_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_102.out/test6_102_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_103.out/test6_103_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_104.out/test6_104_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_105.out/test6_105_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_106.out/test6_106_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_107.out/test6_107_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_108.out/test6_108_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_109.out/test6_109_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_110.out/test6_110_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_111.out/test6_111_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_112.out/test6_112_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_113.out/test6_113_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_114.out/test6_114_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_115.out/test6_115_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_116.out/test6_116_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_117.out/test6_117_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_118.out/test6_118_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_119.out/test6_119_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_120.out/test6_120_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_121.out/test6_121_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_122.out/test6_122_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_123.out/test6_123_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_124.out/test6_124_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_125.out/test6_125_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_126.out/test6_126_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_127.out/test6_127_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_128.out/test6_128_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_129.out/test6_129_syn0.v; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_130.out/test6_130_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
design -reset; read_verilog test6_131.out/test6_131_syn0.v; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test7.ys 0 → 100644
# Check that shift registers with resets are not inferred into SRLs
design -reset; read_verilog test7a.out/test7a_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7b.out/test7b_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7c.out/test7c_syn0.v; select t:SRL* -assert-count 0
design -reset; read_verilog test7d.out/test7d_syn0.v; select t:SRL* -assert-count 0
architecture/synth_xilinx_srl/test7a.v 0 → 100644
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset
module test7a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
architecture/synth_xilinx_srl/test7b.v 0 → 100644
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset
module test7b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] };
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
architecture/synth_xilinx_srl/test7c.v 0 → 100644
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
module test7c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1]));
end
wire [depth-1:0] t;
assign t = int[w][depth:1];
assign q[w] = t[l];
end
endgenerate
endmodule
architecture/synth_xilinx_srl/test7d.v 0 → 100644
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
module test7d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
endgenerate
endmodule
architecture/synth_xilinx_srl/test8.v 0 → 100644
// Check multi-bit works
// pos_clk_no_enable_no_init_not_inferred_N_width
module test8 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
architecture/synth_xilinx_srl/test8.ys 0 → 100644
# Check that wide shift registers are not a problem
read_verilog test8.out/test8_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/test9.v 0 → 100644
// Check multi-bit works
// neg_clk_no_enable_with_init_with_inferred_N_width
module test9 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) int[w] <= { int[w][depth-2:0], i[w] };
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
architecture/synth_xilinx_srl/test9.ys 0 → 100644
read_verilog test9.out/test9_syn0.v; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/ug901.ys 0 → 100644
design -reset; read_verilog ug901a.out/ug901a_syn0.v; select t:SRLC32E -assert-count 1
design -reset; read_verilog ug901b.out/ug901b_syn0.v; select t:SRLC32E -assert-count 1
design -reset; read_verilog ug901c.out/ug901c_syn0.v; select t:SRLC32E -assert-count 1
architecture/synth_xilinx_srl/ug901a.v 0 → 100644
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 8-bit Shift Register
// Rising edge clock
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk)
begin
if (clken)
shreg <= {shreg[WIDTH-2:0], SI};
end
assign SO = shreg[WIDTH-1];
endmodule
architecture/synth_xilinx_srl/ug901b.v 0 → 100644
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 32-bit Shift Register
// Rising edge clock
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
integer i;
always @(posedge clk)
begin
if (clken)
begin
for (i = 0; i < WIDTH-1; i = i+1)
shreg[i+1] <= shreg[i];
shreg[0] <= SI;
end
end
assign SO = shreg[WIDTH-1];
endmodule
architecture/synth_xilinx_srl/ug901c.v 0 → 100644
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
input [SELWIDTH-1:0] SEL;
output DO;
localparam DATAWIDTH = 2**SELWIDTH;
reg [DATAWIDTH-1:0] data;
assign DO = data[SEL];
always @(posedge CLK)
begin
if (CE == 1'b1)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
regression/Makefile
......@@ -30,8 +30,9 @@ $(eval $(call template,issue_00041,issue_00041))
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
# Takes too long
#$(eval $(call template,issue_00065,issue_00065))
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,issue_00065,issue_00065))
endif
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
......@@ -299,8 +300,9 @@ $(eval $(call template,issue_00763,issue_00763))
$(eval $(call template,issue_00767,issue_00767))
#issue_00774
# Takes too long
#$(eval $(call template,issue_00774,issue_00774))
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,issue_00774,issue_00774))
endif
#issue_00781
$(eval $(call template,issue_00781,issue_00781))
......
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