Add tests for new commands in passes/pmgen

-ice40_wrapcarry
-test_pmgen
-xilinx_srl

architecture/Makefile

@@ -54,6 +54,8 @@ $(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_b
 $(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
 $(eval $(call template,synth_ice40_fulladder,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
 $(eval $(call template,synth_ice40_error,synth_ice40_fully_selected synth_ice40_abc9_retime synth_ice40_device_unknown))
+$(eval $(call template,ice40_wrapcarry,ice40_wrapcarry ice40_wrapcarry_top))
+$(eval $(call template,ice40_wrapcarry_adders,ice40_wrapcarry ice40_wrapcarry_top))
 
 #intel
 $(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_iopads synth_intel_nobram synth_intel_max10 ))
@@ -69,8 +71,9 @@ $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf
 $(eval $(call template,synth_sf2_error,synth_sf2_fully_selected ))
 
 #xilinx
-$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_widemux_9 synth_xilinx_widemux_2 synth_xilinx_widemux_3 synth_xilinx_nowidelut_abc9))
+$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_widemux_9 synth_xilinx_widemux_2 synth_xilinx_widemux_3 synth_xilinx_nowidelut_abc9 xilinx_srl_minlen_variable xilinx_srl_minlen))
 $(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch synth_xilinx_abc9_retime synth_xilinx_widemux_1))
+$(eval $(call template,xilinx_srl,xilinx_srl_minlen xilinx_srl_fixed xilinx_srl_variable xilinx_srl_minlen_variable))
 ifeq ($(ENABLE_HEAVY_TESTS),1)
 $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
 $(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))

architecture/ice40_wrapcarry/testbench.v

+module testbench;
+    reg [7:0] in;
+
+	wire [3:0] outA,outB;
+	wire [3:0] poutA,poutB;
+
+    initial begin
+       //  $dumpfile("testbench.vcd");
+       //  $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[3:0]),
+	.y(in[7:4]),
+	.A(outA),
+	.B(outB)
+	);
+
+
+	//assign poutA =  in[3:0] % in[7:4];
+	assign poutB =  in[3:0] / in[7:4];
+
+	//check_comb mod_test(outA, poutA);
+	check_comb div_test(outB, poutB);
+	assert_comb div2_test(outB[2], poutB[2]);
+
+endmodule
+
+module check_comb(input [3:0] test, input [3:0] pat);
+    always @*
+    begin
+        #1;
+        if (test !== pat)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
+            $stop;
+        end
+    end
+endmodule
+

architecture/ice40_wrapcarry/top.v

+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+//assign A =  x % y;
+assign B =  x / y;
+
+endmodule

architecture/ice40_wrapcarry_adders/testbench.v

+module testbench;
+    reg [31:0] in;
+
+	wire [15:0] outA,outB;
+	wire [15:0] poutA,poutB;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[15:0]),
+	.y(in[31:16]),
+	.A(outA),
+	.B(outB)
+	);
+
+
+	assign poutA =  in[15:0] + in[31:16];
+	assign poutB =  in[15:0] - in[31:16];
+
+	check_comb add_test(outA, poutA);
+	check_comb sub_test(outB, poutB);
+	assert_comb sub0_test(outB[2], poutB[2]);
+
+endmodule
+
+module check_comb(input [15:0] test, input [15:0] pat);
+    always @*
+    begin
+        #1;
+        if (test != pat)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
+            $stop;
+        end
+    end
+endmodule
+

architecture/ice40_wrapcarry_adders/top.v

+module top
+(
+ input [15:0] x,
+ input [15:0] y,
+
+ output [15:0] A,
+ output [15:0] B
+ );
+
+assign A =  x + y;
+assign B =  x - y;
+
+endmodule

architecture/run.sh

@@ -99,6 +99,10 @@ else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 	elif [ "$1" = "synth_ice40_fulladder" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
+	elif [ "$1" = "ice40_wrapcarry" ]; then
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
+	elif [ "$1" = "ice40_wrapcarry_adders" ]; then
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 	elif [ "$1" = "synth_intel" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
 	elif [ "$1" = "synth_intel_a10gx" ]; then
@@ -115,6 +119,8 @@ else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
 	elif [ "$1" = "synth_xilinx" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
+	elif [ "$1" = "xilinx_srl" ]; then
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
 	elif [ "$1" = "synth_greenpak4" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
 	elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then

architecture/scripts/ice40_wrapcarry.ys

+read_verilog ../top.v
+synth_ice40
+ice40_wrapcarry
+write_verilog synth.v

architecture/scripts/ice40_wrapcarry_top.ys

+read_verilog ../top.v
+synth_ice40
+ice40_wrapcarry top
+write_verilog synth.v

architecture/scripts/xilinx_srl_fixed.ys

+read_verilog ../top.v
+synth_xilinx
+xilinx_srl -fixed
+write_verilog synth.v

architecture/scripts/xilinx_srl_minlen.ys

+read_verilog ../top.v
+synth_xilinx
+xilinx_srl -fixed -minlen 1
+design -reset
+read_verilog ../top.v
+synth_xilinx
+write_verilog synth.v

architecture/scripts/xilinx_srl_minlen_variable.ys

+read_verilog ../top.v
+synth_xilinx
+xilinx_srl -variable -minlen 1
+design -reset
+read_verilog ../top.v
+synth_xilinx
+write_verilog synth.v

architecture/scripts/xilinx_srl_variable.ys

+read_verilog ../top.v
+synth_xilinx
+xilinx_srl -variable
+write_verilog synth.v

architecture/xilinx_srl/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg in = 0;
+    wire [7:0] f;
+
+
+    top uut ( .clk(clk),
+              .in(in),
+              .out(f));
+
+    always @(posedge clk) begin
+    #3
+    in <= ~in;
+    end
+
+
+
+	assert_expr f_test(.clk(clk), .A(f[0]));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A === 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

architecture/xilinx_srl/top.v

+module top    (
+out,
+out1,
+clk,
+in
+);
+    output [7:0] out;
+    output [7:0] out1;
+    input signed clk, in;
+    reg signed [7:0] out;
+    reg signed [7:0] out1;
+
+    always @(posedge clk)
+	begin
+`ifndef BUG
+		out    <= out >> 1;
+		out[7] <= in;
+`else
+	out <= 8'bZZZZZZZZ;
+`endif
+	end
+
+	always @(posedge clk)
+	begin
+		out1    <= out1 >> 1;
+		out1[7] <= in;
+	end
+
+endmodule

simple/Makefile

@@ -235,4 +235,7 @@ $(eval $(call template, simplemap_mem_slice_concat, simplemap simplemap_top simp
 #techmap
 $(eval $(call template, techmap, techmap techmap_wb techmap_autoproc techmap_recursive techmap_extern techmap_assert techmap_i techmap_d techmap_max_iter techmap_map))
 
+#test_pmgen
+$(eval $(call template, test_pmgen, test_pmgen_eqpmux test_pmgen_generate_eqpmux test_pmgen_generate_ice40_dsp test_pmgen_generate_peepopt_muldiv test_pmgen_generate_peepopt_shiftmul test_pmgen_generate_reduce test_pmgen_generate_xilinx_srl_fixed test_pmgen_generate_xilinx_srl_variable test_pmgen_reduce_chain test_pmgen_reduce_tree))
+
 .PHONY: all clean

simple/scripts/test_pmgen_eqpmux.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -eqpmux
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_generate_eqpmux.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -generate eqpmux
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_generate_ice40_dsp.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -generate ice40_dsp
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_generate_peepopt_muldiv.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -generate peepopt-muldiv
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_generate_peepopt_shiftmul.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -generate peepopt-shiftmul
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_generate_reduce.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -generate reduce
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_generate_xilinx_srl_fixed.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -generate xilinx_srl.fixed
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_generate_xilinx_srl_variable.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -generate xilinx_srl.variable
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_reduce_chain.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -reduce_chain
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/scripts/test_pmgen_reduce_tree.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_pmgen -reduce_tree
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

simple/test_pmgen/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

simple/test_pmgen/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+
+    assign 	io[1] = (i)? ~en : 1'bZ;
+
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule