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lvzhengyang
yosys-tests
Commits
7c883418
Commit
7c883418
authored
Sep 05, 2019
by
Eddie Hung
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Extend assert_area.py support for macc
parent
559c633e
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7 additions
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architecture/synth_xilinx_dsp/assert_area.py
+7
-7
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architecture/synth_xilinx_dsp/assert_area.py
View file @
7c883418
...
...
@@ -4,18 +4,18 @@ import glob
import
re
import
os
re_mux
=
re
.
compile
(
r'
mul
_(\d+)(s?)_(\d+)(s?)_(A?B?M?P?)_A?B?M?P?\.v'
)
re_mux
=
re
.
compile
(
r'
(mul|macc)
_(\d+)(s?)_(\d+)(s?)_(A?B?M?P?)_A?B?M?P?\.v'
)
for
fn
in
glob
.
glob
(
'*.v'
):
m
=
re_mux
.
match
(
fn
)
if
not
m
:
continue
A
,
B
=
map
(
int
,
m
.
group
(
1
,
3
))
Asigned
,
Bsigned
=
m
.
group
(
2
,
4
)
Areg
=
'A'
in
m
.
group
(
5
)
Breg
=
'B'
in
m
.
group
(
5
)
Mreg
=
'M'
in
m
.
group
(
5
)
Preg
=
'P'
in
m
.
group
(
5
)
A
,
B
=
map
(
int
,
m
.
group
(
2
,
4
))
Asigned
,
Bsigned
=
m
.
group
(
3
,
5
)
Areg
=
'A'
in
m
.
group
(
6
)
Breg
=
'B'
in
m
.
group
(
6
)
Mreg
=
'M'
in
m
.
group
(
6
)
Preg
=
'P'
in
m
.
group
(
6
)
if
A
<
B
:
A
,
B
=
B
,
A
Asigned
,
Bsigned
=
Bsigned
,
Asigned
...
...
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