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yosys-tests
Commit 7c5101bf by SergeyDegtyar
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Review and update tests for issues 655-823

parent 10d55221
Showing with 65 additions and 635 deletions
regression/Makefile
......@@ -17,65 +17,6 @@ clean::
))
endef
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00655
$(eval $(call template,issue_00655,issue_00655))
#issue_00675
$(eval $(call template,issue_00675,issue_00675))
#issue_00685
$(eval $(call template,issue_00685,issue_00685))
#issue_00689
$(eval $(call template,issue_00689,issue_00689))
#issue_00699
$(eval $(call template,issue_00699,issue_00699))
#issue_00705
$(eval $(call template,issue_00705,issue_00705))
#issue_00708
$(eval $(call template,issue_00708,issue_00708))
#issue_00737
$(eval $(call template,issue_00737,issue_00737))
#issue_00763
$(eval $(call template,issue_00763,issue_00763))
#issue_00767
$(eval $(call template,issue_00767,issue_00767))
#issue_00774
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,issue_00774,issue_00774))
endif
#issue_00781
$(eval $(call template,issue_00781,issue_00781))
#issue_00785
$(eval $(call template,issue_00785,issue_00785))
#issue_00807
$(eval $(call template,issue_00807,issue_00807))
#issue_00809
$(eval $(call template,issue_00809,issue_00809))
#issue_00810
$(eval $(call template,issue_00810,issue_00810))
#issue_00814
$(eval $(call template,issue_00814,issue_00814))
#issue_00823
$(eval $(call template,issue_00823,issue_00823))
#issue_00826
$(eval $(call template,issue_00826,issue_00826))
......@@ -254,9 +195,6 @@ $(eval $(call template,issue_01372,issue_01372))
#Still open bugs (should be failed):
#issue_00656
$(eval $(call template,issue_00656,issue_00656))
#issue_01014
$(eval $(call template,issue_01014,issue_01014))
......
regression/issue_00655/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
wire serial_tx;
reg serial_rx;
reg clk100;
reg cpu_reset;
wire eth_ref_clk;
wire user_led0;
wire user_led1;
wire user_led2;
wire user_led3;
reg user_sw0;
reg user_sw1;
reg user_sw2;
reg user_sw3;
reg user_btn0;
reg user_btn1;
reg user_btn2;
reg user_btn3;
wire spiflash_1x_cs_n;
wire spiflash_1x_mosi;
reg spiflash_1x_miso;
wire spiflash_1x_wp;
wire spiflash_1x_hold;
wire [13:0] ddram_a;
wire [2:0] ddram_ba;
wire ddram_ras_n;
wire ddram_cas_n;
wire ddram_we_n;
wire ddram_cs_n;
wire [1:0] ddram_dm;
wire [15:0] ddram_dq;
wire [1:0] ddram_dqs_p;
wire [1:0] ddram_dqs_n;
wire ddram_clk_p;
wire ddram_clk_n;
wire ddram_cke;
wire ddram_odt;
wire ddram_reset_n;
top uut (
serial_tx,
serial_rx,
clk,
cpu_reset,
eth_ref_clk,
user_led0,
user_led1,
user_led2,
user_led3,
user_sw0,
user_sw1,
user_sw2,
user_sw3,
user_btn0,
user_btn1,
user_btn2,
user_btn3,
spiflash_1x_cs_n,
spiflash_1x_mosi,
spiflash_1x_miso,
spiflash_1x_wp,
spiflash_1x_hold,
ddram_a,
ddram_ba,
ddram_ras_n,
ddram_cas_n,
ddram_we_n,
ddram_cs_n,
ddram_dm,
ddram_dq,
ddram_dqs_p,
ddram_dqs_n,
ddram_clk_p,
ddram_clk_n,
ddram_cke,
ddram_odt,
ddram_reset_n
);
endmodule
regression/issue_00655/top.edif deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00655/top_wo_attrprop.edif deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00675/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00689/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00699/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00705/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [7:0] dbr; // Data bus READ
reg [7:0] addr = 0; // Address bus - eight bits
always @(posedge clk)
begin
addr = addr + 1;
end
top uut (
dbr, // Data bus READ
addr, // Address bus - eight bits
clk // Clock
);
assert_Z b1_test(clk,dbr[7]);
endmodule
regression/issue_00763/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
reg b,u = 0;
always @(posedge clk)
begin
b = b + 1;
u = ~u;
end
top uut (clk,b,u);
endmodule
regression/issue_00767/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
reg b,u = 0;
always @(posedge clk)
begin
b = b + 1;
u = ~u;
end
top uut (clk,b,u,out);
endmodule
regression/issue_00781/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
reg b,u = 0;
always @(posedge clk)
begin
b = b + 1;
u = ~u;
end
top uut (clk,b,u);
endmodule
regression/issue_00790/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [3:0] D;
reg [1:0] S = 0;
reg [3:0] control = 0;
always @(posedge clk)
case(S)
2'b00: begin end
2'b01: control <= 4'h2;
2'b10: control <= 4'h4;
2'b11: control <= 4'h8;
default: control <= 4'h0;
endcase
top uut (
.clk (clk ),
.I (S ),
.O (D )
);
always @(posedge clk) begin
//#3;
S <= S + 1;
end
check_output out_test( .A(control), .B(D));
endmodule
module check_output(input [3:0] A, input [3:0] B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
regression/issue_00790/top.v deleted 100644 → 0
module mcve(i_clk, i_value, o_value);
input wire i_clk;
input wire [1:0] i_value;
output reg [3:0] o_value;
initial o_value = 0;
always @(posedge i_clk)
case(i_value)
2'b00: begin end
`ifndef BUG
2'b01: o_value <= 4'h2;
`else
2'b01: o_value <= 4'h3;
`endif
2'b10: o_value <= 4'h4;
2'b11: o_value <= 4'h8;
default: o_value <= 4'h1;
endcase
endmodule
module top (
input clk,
input [1:0] I,
output [3:0] O
);
mcve u_mcve (
.i_clk(clk),
.i_value(I),
.o_value(O)
);
endmodule
regression/issue_00807/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] x = 0;
wire y;
always @(posedge clk)
begin
x = x + 1;
end
top uut (x,y);
assert_X out_test (clk,y);
endmodule
regression/issue_00809/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] x = 0;
wire y;
always @(posedge clk)
begin
x = x + 1;
end
reg [3:0] A;
reg [3:0] B;
wire [3:0] O;
wire [3:0] O_p;
wire C;
wire C_p;
assign {C_p, O_p} = A + B;
top uut (C,O,A,B);
assert_comb c_test (C,C_p);
assert_comb o0_test (O[0],O_p[0]);
assert_comb o1_test (O[1],O_p[1]);
assert_comb o2_test (O[2],O_p[2]);
assert_comb o3_test (O[3],O_p[3]);
endmodule
regression/issue_00814/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] c = 0;
reg in, jmp = 0;
wire [8-1:0] out,out_o;
always @(posedge clk)
begin
c = c + 1;
end
assign in = c[0];
assign jmp = c[1];
initial out = 0;
always @(posedge clk)
if (jmp)
out <= { out[UNDEFINED-1:0], in };
else
out <= { 1'b0, out[UNDEFINED-1:1] };
top uut (clk, jmp, in, out_o);
assert_comb o0_test (out[0],out_o[0]);
assert_comb o1_test (out[1],out_o[1]);
assert_comb o2_test (out[2],out_o[2]);
assert_comb o3_test (out[3],out_o[3]);
assert_comb o4_test (out[4],out_o[4]);
assert_comb o5_test (out[5],out_o[5]);
assert_comb o6_test (out[6],out_o[6]);
assert_comb o7_test (out[7],out_o[7]);
endmodule
regression/scripts/issue_00656.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_00689.ys deleted 100644 → 0
tee -o result.log read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00699.ys deleted 100644 → 0
tee -o result.log read_verilog -sv ../top.v
regression/scripts/issue_00705.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00708.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_00737.ys deleted 100644 → 0
tee -o result.log read_verilog -dump_ast1 ../top.v
regression/scripts/issue_00763.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00790.ys deleted 100644 → 0
read -formal ../top_assert.v
prep -top mcve
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00814.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression_revised/Makefile
......@@ -264,6 +264,64 @@ $(eval $(call template,issue_00642,issue_00642))
#issue_00644
$(eval $(call template,issue_00644,issue_00644))
#issue_00655
$(eval $(call template,issue_00655,issue_00655))
#issue_00675
$(eval $(call template,issue_00675,issue_00675))
#issue_00685
$(eval $(call template,issue_00685,issue_00685))
#issue_00689
$(eval $(call template,issue_00689,issue_00689))
#issue_00699
$(eval $(call template,issue_00699,issue_00699))
#issue_00705
$(eval $(call template,issue_00705,issue_00705))
#issue_00708
$(eval $(call template,issue_00708,issue_00708))
#issue_00737
$(eval $(call template,issue_00737,issue_00737))
#issue_00763
$(eval $(call template,issue_00763,issue_00763_fail))
#issue_00767
$(eval $(call template,issue_00767,issue_00767))
#issue_00774
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,issue_00774,issue_00774))
endif
#issue_00781
$(eval $(call template,issue_00781,issue_00781))
#issue_00785
$(eval $(call template,issue_00785,issue_00785))
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00807
$(eval $(call template,issue_00807,issue_00807))
#issue_00809
$(eval $(call template,issue_00809,issue_00809))
#issue_00810
$(eval $(call template,issue_00810,issue_00810))
#issue_00814
$(eval $(call template,issue_00814,issue_00814_fail))
#issue_00823
$(eval $(call template,issue_00823,issue_00823))
#Still open bugs (should be failed):
#issue_00329
......@@ -272,4 +330,7 @@ $(eval $(call template,issue_00329,issue_00329))
#issue_00623
$(eval $(call template,issue_00623,issue_00623))
#issue_00656
$(eval $(call template,issue_00656,issue_00656))
.PHONY: all clean
regression/scripts/issue_00655.ys → regression_revised/issue_00655/issue_00655.ys
......@@ -17,9 +17,9 @@ read_verilog -I../verilog/config ../verilog/submodule/rtl/lm32_debug.v
read_verilog -I../verilog/config ../verilog/submodule/rtl/lm32_itlb.v
read_verilog -I../verilog/config ../verilog/submodule/rtl/lm32_dtlb.v
read_verilog -I../verilog/config ../top.v
# hierarchy -top top
hierarchy -top top
# proc; memory; opt; fsm; opt
attrmap -tocase keep -imap keep="true" keep=1 \
-imap keep="false" keep=0 -remove keep=0
tee -o result.log synth_xilinx -top top -edif top.edif
write_verilog synth.v
synth_xilinx -top top
write_edif -attrprop result.out
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