Rename test group back to 'architecture'

743baf58 · SergeyDegtyar · 0d34ab09 · 743baf58 · 743baf58 · 743baf58
Commit 743baf58 authored Oct 30, 2019 by SergeyDegtyar
596 changed files
--- a/Makefile
+++ b/Makefile

-SUBDIRS := architecture_reviewed backends bigsim equiv frontends misc regression simple yosys
+SUBDIRS := architecture backends bigsim equiv frontends misc regression simple yosys

 ifeq ($(VERIFIC),1)
 export VERIFIC=1

--- a/architecture_reviewed/.gitignore
+++ b/architecture_reviewed/.gitignore
--- a/architecture/.start
+++ b/architecture/.start
--- a/architecture_reviewed/Makefile
+++ b/architecture_reviewed/Makefile
--- a/architecture_reviewed/common.v
+++ b/architecture_reviewed/common.v
--- a/architecture_reviewed/run.sh
+++ b/architecture_reviewed/run.sh
--- a/architecture_reviewed/synth_achronix/synth_achronix.ys
+++ b/architecture_reviewed/synth_achronix/synth_achronix.ys
--- a/architecture_reviewed/synth_achronix/synth_achronix_fail.pat
+++ b/architecture_reviewed/synth_achronix/synth_achronix_fail.pat
--- a/architecture_reviewed/synth_achronix/synth_achronix_fail.ys
+++ b/architecture_reviewed/synth_achronix/synth_achronix_fail.ys
--- a/architecture_reviewed/synth_achronix/synth_achronix_noflatten.ys
+++ b/architecture_reviewed/synth_achronix/synth_achronix_noflatten.ys
--- a/architecture_reviewed/synth_achronix/synth_achronix_retime.ys
+++ b/architecture_reviewed/synth_achronix/synth_achronix_retime.ys
--- a/architecture_reviewed/synth_achronix/synth_achronix_run.ys
+++ b/architecture_reviewed/synth_achronix/synth_achronix_run.ys
--- a/architecture_reviewed/synth_achronix/synth_achronix_top.ys
+++ b/architecture_reviewed/synth_achronix/synth_achronix_top.ys
--- a/architecture_reviewed/synth_achronix/synth_achronix_vout.ys
+++ b/architecture_reviewed/synth_achronix/synth_achronix_vout.ys
--- a/architecture_reviewed/synth_achronix/top.v
+++ b/architecture_reviewed/synth_achronix/top.v
--- a/architecture_reviewed/synth_anlogic/anlogic_determine_init_eqn.ys
+++ b/architecture_reviewed/synth_anlogic/anlogic_determine_init_eqn.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_edif.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_edif.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_fail.pat
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_fail.pat
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_fail.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_fail.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_fulladder.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_fulladder.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_json.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_json.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_noflatten.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_noflatten.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_retime.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_retime.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_run.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_run.ys
--- a/architecture_reviewed/synth_anlogic/synth_anlogic_top.ys
+++ b/architecture_reviewed/synth_anlogic/synth_anlogic_top.ys
--- a/architecture_reviewed/synth_anlogic/top.v
+++ b/architecture_reviewed/synth_anlogic/top.v
--- a/architecture_reviewed/synth_anlogic/top_fulladder.v
+++ b/architecture_reviewed/synth_anlogic/top_fulladder.v
--- a/architecture_reviewed/synth_anlogic/top_mem.v
+++ b/architecture_reviewed/synth_anlogic/top_mem.v
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_fail.pat
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_fail.pat
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_fail.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_fail.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_for_lcov.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_for_lcov.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_fulladder.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_fulladder.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_noflatten.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_noflatten.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_retime.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_retime.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_run.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_run.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_top.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_top.ys
--- a/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_vout.ys
+++ b/architecture_reviewed/synth_coolrunner2/synth_coolrunner2_vout.ys
--- a/architecture_reviewed/synth_coolrunner2/top.v
+++ b/architecture_reviewed/synth_coolrunner2/top.v
--- a/architecture_reviewed/synth_coolrunner2/top_fulladder.v
+++ b/architecture_reviewed/synth_coolrunner2/top_fulladder.v
--- a/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2.ys
+++ b/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2.ys
--- a/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_noflatten.ys
+++ b/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_noflatten.ys
--- a/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_retime.ys
+++ b/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_retime.ys
--- a/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_run.ys
+++ b/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_run.ys
--- a/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_top.ys
+++ b/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_top.ys
--- a/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_vout.ys
+++ b/architecture_reviewed/synth_coolrunner2_lcov/synth_coolrunner2_vout.ys
--- a/architecture_reviewed/synth_coolrunner2_lcov/top.v
+++ b/architecture_reviewed/synth_coolrunner2_lcov/top.v
--- a/architecture_reviewed/synth_easic/synth_easic.ys
+++ b/architecture_reviewed/synth_easic/synth_easic.ys
--- a/architecture_reviewed/synth_easic/synth_easic_etools.ys
+++ b/architecture_reviewed/synth_easic/synth_easic_etools.ys
--- a/architecture_reviewed/synth_easic/synth_easic_fail.pat
+++ b/architecture_reviewed/synth_easic/synth_easic_fail.pat
--- a/architecture_reviewed/synth_easic/synth_easic_fail.ys
+++ b/architecture_reviewed/synth_easic/synth_easic_fail.ys
--- a/architecture_reviewed/synth_easic/synth_easic_noflatten.ys
+++ b/architecture_reviewed/synth_easic/synth_easic_noflatten.ys
--- a/architecture_reviewed/synth_easic/synth_easic_retime.ys
+++ b/architecture_reviewed/synth_easic/synth_easic_retime.ys
--- a/architecture_reviewed/synth_easic/synth_easic_run.ys
+++ b/architecture_reviewed/synth_easic/synth_easic_run.ys
--- a/architecture_reviewed/synth_easic/synth_easic_top.ys
+++ b/architecture_reviewed/synth_easic/synth_easic_top.ys
--- a/architecture_reviewed/synth_easic/testbench.v
+++ b/architecture_reviewed/synth_easic/testbench.v
--- a/architecture_reviewed/synth_easic/top.v
+++ b/architecture_reviewed/synth_easic/top.v
--- a/architecture_reviewed/synth_ecp5/ecp5_ffinit.ys
+++ b/architecture_reviewed/synth_ecp5/ecp5_ffinit.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_abc2.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_abc2.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_abc9.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_abc9.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_abc9_nowidelut.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_abc9_nowidelut.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_blif.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_blif.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_edif.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_edif.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_fail.pat
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_fail.pat
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_fail.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_fail.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_flatten.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_flatten.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_json.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_json.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_nobram.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_nobram.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_noccu2.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_noccu2.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_nodffe.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_nodffe.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_nodram.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_nodram.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_nodsp.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_nodsp.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_noflatten.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_noflatten.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_nomux.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_nomux.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_retime.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_retime.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_run.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_run.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_top.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_top.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_vpr.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_vpr.ys
--- a/architecture_reviewed/synth_ecp5/synth_ecp5_wide_ffs.ys
+++ b/architecture_reviewed/synth_ecp5/synth_ecp5_wide_ffs.ys
--- a/architecture_reviewed/synth_ecp5/top.v
+++ b/architecture_reviewed/synth_ecp5/top.v
--- a/architecture_reviewed/synth_ecp5/top_counter.v
+++ b/architecture_reviewed/synth_ecp5/top_counter.v
--- a/architecture_reviewed/synth_ecp5/top_dpram.v
+++ b/architecture_reviewed/synth_ecp5/top_dpram.v
--- a/architecture_reviewed/synth_ecp5/top_dsp.v
+++ b/architecture_reviewed/synth_ecp5/top_dsp.v
--- a/architecture_reviewed/synth_ecp5/top_mux.v
+++ b/architecture_reviewed/synth_ecp5/top_mux.v
--- a/architecture_reviewed/synth_ecp5/top_wide_ffs.v
+++ b/architecture_reviewed/synth_ecp5/top_wide_ffs.v
--- a/architecture_reviewed/synth_efinix/synth_efinix.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix.ys
--- a/architecture_reviewed/synth_efinix/synth_efinix_edif.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix_edif.ys
--- a/architecture_reviewed/synth_efinix/synth_efinix_fulladder.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix_fulladder.ys
--- a/architecture_reviewed/synth_efinix/synth_efinix_json.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix_json.ys
--- a/architecture_reviewed/synth_efinix/synth_efinix_noflatten.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix_noflatten.ys
--- a/architecture_reviewed/synth_efinix/synth_efinix_retime.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix_retime.ys
--- a/architecture_reviewed/synth_efinix/synth_efinix_run.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix_run.ys
--- a/architecture_reviewed/synth_efinix/synth_efinix_top.ys
+++ b/architecture_reviewed/synth_efinix/synth_efinix_top.ys
--- a/architecture_reviewed/synth_efinix/top.v
+++ b/architecture_reviewed/synth_efinix/top.v
--- a/architecture_reviewed/synth_efinix/top_fulladder.v
+++ b/architecture_reviewed/synth_efinix/top_fulladder.v
--- a/architecture_reviewed/synth_gowin/synth_gowin.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_fail.pat
+++ b/architecture_reviewed/synth_gowin/synth_gowin_fail.pat
--- a/architecture_reviewed/synth_gowin/synth_gowin_fail.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_fail.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_nobram.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_nobram.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_nodffe.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_nodffe.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_nodram.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_nodram.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_noflatten.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_noflatten.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_retime.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_retime.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_run.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_run.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_top.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_top.ys
--- a/architecture_reviewed/synth_gowin/synth_gowin_vout.ys
+++ b/architecture_reviewed/synth_gowin/synth_gowin_vout.ys
--- a/architecture_reviewed/synth_gowin/top.v
+++ b/architecture_reviewed/synth_gowin/top.v
--- a/architecture_reviewed/synth_gowin/top_dffe.v
+++ b/architecture_reviewed/synth_gowin/top_dffe.v
--- a/architecture_reviewed/synth_gowin/top_mem.v
+++ b/architecture_reviewed/synth_gowin/top_mem.v
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_adffs.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_adffs.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_adffsr.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_adffsr.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_fully_selected_fail.pat
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_fully_selected_fail.pat
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_fully_selected_fail.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_fully_selected_fail.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_gp_dffs.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_gp_dffs.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_inv_inputs.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_inv_inputs.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_invalid_part_fail.pat
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_invalid_part_fail.pat
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_invalid_part_fail.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_invalid_part_fail.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_json.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_json.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_noflatten.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_noflatten.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_part140.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_part140.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_part620.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_part620.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_part621.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_part621.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_retime.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_retime.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_run.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_run.ys
--- a/architecture_reviewed/synth_greenpak4/synth_greenpak4_top.ys
+++ b/architecture_reviewed/synth_greenpak4/synth_greenpak4_top.ys
--- a/architecture_reviewed/synth_greenpak4/top.v
+++ b/architecture_reviewed/synth_greenpak4/top.v
--- a/architecture_reviewed/synth_greenpak4/top_adffs.v
+++ b/architecture_reviewed/synth_greenpak4/top_adffs.v
--- a/architecture_reviewed/synth_greenpak4/top_dffsr.v
+++ b/architecture_reviewed/synth_greenpak4/top_dffsr.v
--- a/architecture_reviewed/synth_greenpak4/top_gp_dffs.v
+++ b/architecture_reviewed/synth_greenpak4/top_gp_dffs.v
--- a/architecture_reviewed/synth_greenpak4/top_inv_inputs.v
+++ b/architecture_reviewed/synth_greenpak4/top_inv_inputs.v
--- a/architecture_reviewed/synth_ice40/init.txt
+++ b/architecture_reviewed/synth_ice40/init.txt
--- a/architecture_reviewed/synth_ice40/init1.txt
+++ b/architecture_reviewed/synth_ice40/init1.txt
--- a/architecture_reviewed/synth_ice40/synth_ice40.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_abc2.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_abc2.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_abc9.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_abc9.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_abc9_retime_fail.pat
+++ b/architecture_reviewed/synth_ice40/synth_ice40_abc9_retime_fail.pat
--- a/architecture_reviewed/synth_ice40/synth_ice40_abc9_retime_fail.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_abc9_retime_fail.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_blif.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_blif.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_device_hx.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_device_hx.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_device_lp.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_device_lp.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_device_u.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_device_u.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_device_unknown_fail.pat
+++ b/architecture_reviewed/synth_ice40/synth_ice40_device_unknown_fail.pat
--- a/architecture_reviewed/synth_ice40/synth_ice40_device_unknown_fail.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_device_unknown_fail.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_dsp.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_dsp.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_edif.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_edif.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_flatten.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_flatten.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_fully_selected_fail.pat
+++ b/architecture_reviewed/synth_ice40/synth_ice40_fully_selected_fail.pat
--- a/architecture_reviewed/synth_ice40/synth_ice40_fully_selected_fail.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_fully_selected_fail.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_json.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_json.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_mem_init.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_mem_init.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_min_ce.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_min_ce.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_noabc.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_noabc.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_nobram.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_nobram.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_nocarry.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_nocarry.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_nodffe.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_nodffe.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_noflatten.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_noflatten.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_opt.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_opt.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_relut.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_relut.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_retime.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_retime.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_run.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_run.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_top.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_top.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_vpr.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_vpr.ys
--- a/architecture_reviewed/synth_ice40/synth_ice40_wide_ffs.ys
+++ b/architecture_reviewed/synth_ice40/synth_ice40_wide_ffs.ys
--- a/architecture_reviewed/synth_ice40/top.v
+++ b/architecture_reviewed/synth_ice40/top.v
--- a/architecture_reviewed/synth_ice40/top_dpram.v
+++ b/architecture_reviewed/synth_ice40/top_dpram.v
--- a/architecture_reviewed/synth_ice40/top_dsp.v
+++ b/architecture_reviewed/synth_ice40/top_dsp.v
--- a/architecture_reviewed/synth_ice40/top_dsp_nocarry.v
+++ b/architecture_reviewed/synth_ice40/top_dsp_nocarry.v
--- a/architecture_reviewed/synth_ice40/top_mem.v
+++ b/architecture_reviewed/synth_ice40/top_mem.v
--- a/architecture_reviewed/synth_ice40/top_wide_ffs.v
+++ b/architecture_reviewed/synth_ice40/top_wide_ffs.v
--- a/architecture_reviewed/synth_ice40_dsp/assert_area.py
+++ b/architecture_reviewed/synth_ice40_dsp/assert_area.py
--- a/architecture_reviewed/synth_ice40_dsp/generate_mul.py
+++ b/architecture_reviewed/synth_ice40_dsp/generate_mul.py
--- a/architecture_reviewed/synth_ice40_dsp/mul_16_16_keepABP_.v
+++ b/architecture_reviewed/synth_ice40_dsp/mul_16_16_keepABP_.v
--- a/architecture_reviewed/synth_ice40_dsp/mul_32_32_keepB_.v
+++ b/architecture_reviewed/synth_ice40_dsp/mul_32_32_keepB_.v
--- a/architecture_reviewed/synth_ice40_dsp/run-test.sh
+++ b/architecture_reviewed/synth_ice40_dsp/run-test.sh
--- a/architecture_reviewed/synth_intel/synth_intel.ys
+++ b/architecture_reviewed/synth_intel/synth_intel.ys
--- a/architecture_reviewed/synth_intel/synth_intel_a10gx.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_a10gx.ys
--- a/architecture_reviewed/synth_intel/synth_intel_cyclone10.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_cyclone10.ys
--- a/architecture_reviewed/synth_intel/synth_intel_cycloneiv.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_cycloneiv.ys
--- a/architecture_reviewed/synth_intel/synth_intel_cycloneive.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_cycloneive.ys
--- a/architecture_reviewed/synth_intel/synth_intel_cyclonev.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_cyclonev.ys
--- a/architecture_reviewed/synth_intel/synth_intel_fully_selected_fail.pat
+++ b/architecture_reviewed/synth_intel/synth_intel_fully_selected_fail.pat
--- a/architecture_reviewed/synth_intel/synth_intel_fully_selected_fail.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_fully_selected_fail.ys
--- a/architecture_reviewed/synth_intel/synth_intel_invalid_family_fail.pat
+++ b/architecture_reviewed/synth_intel/synth_intel_invalid_family_fail.pat
--- a/architecture_reviewed/synth_intel/synth_intel_invalid_family_fail.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_invalid_family_fail.ys
--- a/architecture_reviewed/synth_intel/synth_intel_iopads.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_iopads.ys
--- a/architecture_reviewed/synth_intel/synth_intel_max10.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_max10.ys
--- a/architecture_reviewed/synth_intel/synth_intel_nobram.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_nobram.ys
--- a/architecture_reviewed/synth_intel/synth_intel_noflatten.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_noflatten.ys
--- a/architecture_reviewed/synth_intel/synth_intel_retime.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_retime.ys
--- a/architecture_reviewed/synth_intel/synth_intel_run.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_run.ys
--- a/architecture_reviewed/synth_intel/synth_intel_top.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_top.ys
--- a/architecture_reviewed/synth_intel/synth_intel_vpr.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_vpr.ys
--- a/architecture_reviewed/synth_intel/synth_intel_vqm.ys
+++ b/architecture_reviewed/synth_intel/synth_intel_vqm.ys
--- a/architecture_reviewed/synth_intel/top.v
+++ b/architecture_reviewed/synth_intel/top.v
--- a/architecture_reviewed/synth_intel/top_dpram.v
+++ b/architecture_reviewed/synth_intel/top_dpram.v
--- a/architecture_reviewed/synth_intel/top_mem.v
+++ b/architecture_reviewed/synth_intel/top_mem.v
--- a/architecture_reviewed/synth_sf2/synth_sf2.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_clkbuf.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_clkbuf.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_edif.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_edif.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_fully_selected_fail.pat
+++ b/architecture_reviewed/synth_sf2/synth_sf2_fully_selected_fail.pat
--- a/architecture/synth_sf2/synth_sf2_fully_selected_fail.ys
+++ b/architecture/synth_sf2/synth_sf2_fully_selected_fail.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_json.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_json.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_noflatten.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_noflatten.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_noiobs.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_noiobs.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_retime.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_retime.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_run.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_run.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_top.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_top.ys
--- a/architecture/synth_sf2/synth_sf2_vlog.ys
+++ b/architecture/synth_sf2/synth_sf2_vlog.ys
--- a/architecture/synth_sf2/top.v
+++ b/architecture/synth_sf2/top.v
--- a/architecture/synth_sf2_lcov/synth_sf2.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_clkbuf.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_clkbuf.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_edif.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_edif.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_json.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_json.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_noflatten.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_noflatten.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_noiobs.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_noiobs.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_retime.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_retime.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_run.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_run.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_top.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_top.ys
--- a/architecture/synth_sf2_lcov/synth_sf2_vlog.ys
+++ b/architecture/synth_sf2_lcov/synth_sf2_vlog.ys
--- a/architecture_reviewed/synth_sf2_lcov/top.v
+++ b/architecture_reviewed/synth_sf2_lcov/top.v
--- a/architecture/synth_xilinx/synth_xilinx.ys
+++ b/architecture/synth_xilinx/synth_xilinx.ys
--- a/architecture/synth_xilinx/synth_xilinx_abc9.ys
+++ b/architecture/synth_xilinx/synth_xilinx_abc9.ys
--- a/architecture/synth_xilinx/synth_xilinx_abc9_retime_fail.pat
+++ b/architecture/synth_xilinx/synth_xilinx_abc9_retime_fail.pat
--- a/architecture/synth_xilinx/synth_xilinx_abc9_retime_fail.ys
+++ b/architecture/synth_xilinx/synth_xilinx_abc9_retime_fail.ys
--- a/architecture/synth_xilinx/synth_xilinx_arch_xc6s.ys
+++ b/architecture/synth_xilinx/synth_xilinx_arch_xc6s.ys
--- a/architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.pat
+++ b/architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.pat
--- a/architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.ys
+++ b/architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.ys
--- a/architecture/synth_xilinx/synth_xilinx_arch_xc6v.ys
+++ b/architecture/synth_xilinx/synth_xilinx_arch_xc6v.ys
--- a/architecture/synth_xilinx/synth_xilinx_arch_xc7.ys
+++ b/architecture/synth_xilinx/synth_xilinx_arch_xc7.ys
--- a/architecture/synth_xilinx/synth_xilinx_arch_xcu.ys
+++ b/architecture/synth_xilinx/synth_xilinx_arch_xcu.ys
--- a/architecture/synth_xilinx/synth_xilinx_arch_xcup.ys
+++ b/architecture/synth_xilinx/synth_xilinx_arch_xcup.ys
--- a/architecture/synth_xilinx/synth_xilinx_blif.ys
+++ b/architecture/synth_xilinx/synth_xilinx_blif.ys
--- a/architecture/synth_xilinx/synth_xilinx_dsp.ys
+++ b/architecture/synth_xilinx/synth_xilinx_dsp.ys
--- a/architecture/synth_xilinx/synth_xilinx_edif.ys
+++ b/architecture/synth_xilinx/synth_xilinx_edif.ys
--- a/architecture/synth_xilinx/synth_xilinx_flatten.ys
+++ b/architecture/synth_xilinx/synth_xilinx_flatten.ys
--- a/architecture/synth_xilinx/synth_xilinx_flatten_before_abc.ys
+++ b/architecture/synth_xilinx/synth_xilinx_flatten_before_abc.ys
--- a/architecture/synth_xilinx/synth_xilinx_fully_selected_fail.pat
+++ b/architecture/synth_xilinx/synth_xilinx_fully_selected_fail.pat
--- a/architecture/synth_xilinx/synth_xilinx_fully_selected_fail.ys
+++ b/architecture/synth_xilinx/synth_xilinx_fully_selected_fail.ys
--- a/architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.pat
+++ b/architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.pat
--- a/architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.ys
+++ b/architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.ys
--- a/architecture/synth_xilinx/synth_xilinx_iopad.ys
+++ b/architecture/synth_xilinx/synth_xilinx_iopad.ys
--- a/architecture/synth_xilinx/synth_xilinx_ise.ys
+++ b/architecture/synth_xilinx/synth_xilinx_ise.ys
--- a/architecture/synth_xilinx/synth_xilinx_nobram.ys
+++ b/architecture/synth_xilinx/synth_xilinx_nobram.ys
--- a/architecture/synth_xilinx/synth_xilinx_nocarry.ys
+++ b/architecture/synth_xilinx/synth_xilinx_nocarry.ys
--- a/architecture/synth_xilinx/synth_xilinx_noclkbuf.ys
+++ b/architecture/synth_xilinx/synth_xilinx_noclkbuf.ys
--- a/architecture/synth_xilinx/synth_xilinx_nodram.ys
+++ b/architecture/synth_xilinx/synth_xilinx_nodram.ys
--- a/architecture/synth_xilinx/synth_xilinx_nodsp.ys
+++ b/architecture/synth_xilinx/synth_xilinx_nodsp.ys
--- a/architecture/synth_xilinx/synth_xilinx_noiopad.ys
+++ b/architecture/synth_xilinx/synth_xilinx_noiopad.ys
--- a/architecture/synth_xilinx/synth_xilinx_nosrl.ys
+++ b/architecture/synth_xilinx/synth_xilinx_nosrl.ys
--- a/architecture/synth_xilinx/synth_xilinx_nowidelut.ys
+++ b/architecture/synth_xilinx/synth_xilinx_nowidelut.ys
--- a/architecture/synth_xilinx/synth_xilinx_nowidelut_abc9.ys
+++ b/architecture/synth_xilinx/synth_xilinx_nowidelut_abc9.ys
--- a/architecture/synth_xilinx/synth_xilinx_retime.ys
+++ b/architecture/synth_xilinx/synth_xilinx_retime.ys
--- a/architecture/synth_xilinx/synth_xilinx_run.ys
+++ b/architecture/synth_xilinx/synth_xilinx_run.ys
--- a/architecture/synth_xilinx/synth_xilinx_top.ys
+++ b/architecture/synth_xilinx/synth_xilinx_top.ys
--- a/architecture/synth_xilinx/synth_xilinx_vpr.ys
+++ b/architecture/synth_xilinx/synth_xilinx_vpr.ys
--- a/architecture/synth_xilinx/synth_xilinx_widemux.ys
+++ b/architecture/synth_xilinx/synth_xilinx_widemux.ys
--- a/architecture/synth_xilinx/synth_xilinx_widemux_1_fail.pat
+++ b/architecture/synth_xilinx/synth_xilinx_widemux_1_fail.pat
--- a/architecture/synth_xilinx/synth_xilinx_widemux_1_fail.ys
+++ b/architecture/synth_xilinx/synth_xilinx_widemux_1_fail.ys
--- a/architecture/synth_xilinx/top.v
+++ b/architecture/synth_xilinx/top.v
--- a/architecture/synth_xilinx/top_bram.v
+++ b/architecture/synth_xilinx/top_bram.v
--- a/architecture/synth_xilinx/top_dpram.v
+++ b/architecture/synth_xilinx/top_dpram.v
--- a/architecture/synth_xilinx/top_dsp.v
+++ b/architecture/synth_xilinx/top_dsp.v
--- a/architecture/synth_xilinx/top_dsp_simd.v
+++ b/architecture/synth_xilinx/top_dsp_simd.v
--- a/architecture/synth_xilinx/top_mux.v
+++ b/architecture/synth_xilinx/top_mux.v
--- a/architecture/synth_xilinx/top_nocarry.v
+++ b/architecture/synth_xilinx/top_nocarry.v
--- a/architecture/synth_xilinx/top_nosrl.v
+++ b/architecture/synth_xilinx/top_nosrl.v
--- a/architecture/synth_xilinx/top_srl.v
+++ b/architecture/synth_xilinx/top_srl.v
--- a/architecture/synth_xilinx/top_wide_ffs.v
+++ b/architecture/synth_xilinx/top_wide_ffs.v
--- a/architecture/synth_xilinx/xilinx_srl.ys
+++ b/architecture/synth_xilinx/xilinx_srl.ys
--- a/architecture/synth_xilinx_dsp/assert_area.py
+++ b/architecture/synth_xilinx_dsp/assert_area.py
--- a/architecture/synth_xilinx_dsp/generate_macc.py
+++ b/architecture/synth_xilinx_dsp/generate_macc.py
--- a/architecture/synth_xilinx_dsp/generate_mul.py
+++ b/architecture/synth_xilinx_dsp/generate_mul.py
--- a/architecture/synth_xilinx_dsp/generate_muladd.py
+++ b/architecture/synth_xilinx_dsp/generate_muladd.py
--- a/architecture/synth_xilinx_dsp/macc_25s_18s__49bitaccum.v
+++ b/architecture/synth_xilinx_dsp/macc_25s_18s__49bitaccum.v
--- a/architecture/synth_xilinx_dsp/mul_25s_18s_keepABP_.v
+++ b/architecture/synth_xilinx_dsp/mul_25s_18s_keepABP_.v
--- a/architecture/synth_xilinx_dsp/mul_32_32_keepB_.v
+++ b/architecture/synth_xilinx_dsp/mul_32_32_keepB_.v
--- a/architecture/synth_xilinx_dsp/run-test.sh
+++ b/architecture/synth_xilinx_dsp/run-test.sh
--- a/architecture/synth_xilinx_dsp/ug901a.v
+++ b/architecture/synth_xilinx_dsp/ug901a.v
--- a/architecture/synth_xilinx_dsp/ug901b.v
+++ b/architecture/synth_xilinx_dsp/ug901b.v
--- a/architecture/synth_xilinx_mux/assert_area.py
+++ b/architecture/synth_xilinx_mux/assert_area.py
--- a/architecture/synth_xilinx_mux/run-test.sh
+++ b/architecture/synth_xilinx_mux/run-test.sh
--- a/architecture_reviewed/synth_xilinx_srl/generate.py
+++ b/architecture_reviewed/synth_xilinx_srl/generate.py
--- a/architecture_reviewed/synth_xilinx_srl/lfsr_area.py
+++ b/architecture_reviewed/synth_xilinx_srl/lfsr_area.py
--- a/architecture/synth_xilinx_srl/multiclock.v
+++ b/architecture/synth_xilinx_srl/multiclock.v
--- a/architecture/synth_xilinx_srl/multiclock_var_len.v
+++ b/architecture/synth_xilinx_srl/multiclock_var_len.v
--- a/architecture/synth_xilinx_srl/multien.v
+++ b/architecture/synth_xilinx_srl/multien.v
--- a/architecture/synth_xilinx_srl/multien_var_len.v
+++ b/architecture/synth_xilinx_srl/multien_var_len.v
--- a/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v
+++ b/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v
--- a/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v
+++ b/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v
--- a/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v
+++ b/architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v
--- a/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v
+++ b/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v
--- a/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v
+++ b/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v
--- a/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v
+++ b/architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v
--- a/architecture/synth_xilinx_srl/rotate_3.v
+++ b/architecture/synth_xilinx_srl/rotate_3.v
--- a/architecture/synth_xilinx_srl/rotate_3_fdre.v
+++ b/architecture/synth_xilinx_srl/rotate_3_fdre.v
--- a/architecture/synth_xilinx_srl/rotate_3_var_len.v
+++ b/architecture/synth_xilinx_srl/rotate_3_var_len.v
--- a/architecture/synth_xilinx_srl/rotate_7_fdre_param.v
+++ b/architecture/synth_xilinx_srl/rotate_7_fdre_param.v
--- a/architecture/synth_xilinx_srl/rotate_7_fdre_reset.v
+++ b/architecture/synth_xilinx_srl/rotate_7_fdre_reset.v
--- a/architecture/synth_xilinx_srl/run-test.sh
+++ b/architecture/synth_xilinx_srl/run-test.sh
--- a/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v
+++ b/architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v
--- a/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v
+++ b/architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v
--- a/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v
+++ b/architecture/synth_xilinx_srl/sr_var_length_other_users_port.v
--- a/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v
+++ b/architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v
--- a/architecture/synth_xilinx_srl/test17a.v
+++ b/architecture/synth_xilinx_srl/test17a.v
--- a/architecture/synth_xilinx_srl/test17b.v
+++ b/architecture/synth_xilinx_srl/test17b.v
--- a/architecture/synth_xilinx_srl/test17c.v
+++ b/architecture/synth_xilinx_srl/test17c.v
--- a/architecture/synth_xilinx_srl/test17d.v
+++ b/architecture/synth_xilinx_srl/test17d.v
--- a/architecture/synth_xilinx_srl/test17e.v
+++ b/architecture/synth_xilinx_srl/test17e.v
--- a/architecture/synth_xilinx_srl/test20.v
+++ b/architecture/synth_xilinx_srl/test20.v
--- a/architecture/synth_xilinx_srl/test21a.v
+++ b/architecture/synth_xilinx_srl/test21a.v
--- a/architecture/synth_xilinx_srl/test21b.v
+++ b/architecture/synth_xilinx_srl/test21b.v
--- a/architecture/synth_xilinx_srl/ug901a.v
+++ b/architecture/synth_xilinx_srl/ug901a.v
--- a/architecture/synth_xilinx_srl/ug901b.v
+++ b/architecture/synth_xilinx_srl/ug901b.v
--- a/architecture/synth_xilinx_srl/ug901c.v
+++ b/architecture/synth_xilinx_srl/ug901c.v
--- a/architecture/xilinx_ug901_synthesis_examples/asym_ram_sdp_read_wider.v
+++ b/architecture/xilinx_ug901_synthesis_examples/asym_ram_sdp_read_wider.v
--- a/architecture/xilinx_ug901_synthesis_examples/asym_ram_sdp_write_wider.v
+++ b/architecture/xilinx_ug901_synthesis_examples/asym_ram_sdp_write_wider.v
--- a/architecture/xilinx_ug901_synthesis_examples/asym_ram_tdp_read_first.v
+++ b/architecture/xilinx_ug901_synthesis_examples/asym_ram_tdp_read_first.v
--- a/architecture/xilinx_ug901_synthesis_examples/asym_ram_tdp_write_first.v
+++ b/architecture/xilinx_ug901_synthesis_examples/asym_ram_tdp_write_first.v
--- a/architecture/xilinx_ug901_synthesis_examples/black_box_1.v
+++ b/architecture/xilinx_ug901_synthesis_examples/black_box_1.v
--- a/architecture/xilinx_ug901_synthesis_examples/bytewrite_ram_1b.v
+++ b/architecture/xilinx_ug901_synthesis_examples/bytewrite_ram_1b.v
--- a/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_nc.v
+++ b/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_nc.v
--- a/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_readfirst2.v
+++ b/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_readfirst2.v
--- a/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_rf.v
+++ b/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_rf.v
--- a/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_wf.v
+++ b/architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_wf.v
--- a/architecture/xilinx_ug901_synthesis_examples/cmacc.v
+++ b/architecture/xilinx_ug901_synthesis_examples/cmacc.v
--- a/architecture/xilinx_ug901_synthesis_examples/cmult.v
+++ b/architecture/xilinx_ug901_synthesis_examples/cmult.v
--- a/architecture/xilinx_ug901_synthesis_examples/dynamic_shift_registers_1.v
+++ b/architecture/xilinx_ug901_synthesis_examples/dynamic_shift_registers_1.v
--- a/architecture/xilinx_ug901_synthesis_examples/dynpreaddmultadd.v
+++ b/architecture/xilinx_ug901_synthesis_examples/dynpreaddmultadd.v
--- a/architecture/xilinx_ug901_synthesis_examples/fsm_1.v
+++ b/architecture/xilinx_ug901_synthesis_examples/fsm_1.v
--- a/architecture/xilinx_ug901_synthesis_examples/latches.v
+++ b/architecture/xilinx_ug901_synthesis_examples/latches.v
--- a/architecture/xilinx_ug901_synthesis_examples/macc.v
+++ b/architecture/xilinx_ug901_synthesis_examples/macc.v
--- a/architecture/xilinx_ug901_synthesis_examples/mult_unsigned.v
+++ b/architecture/xilinx_ug901_synthesis_examples/mult_unsigned.v
--- a/architecture/xilinx_ug901_synthesis_examples/presubmult.v
+++ b/architecture/xilinx_ug901_synthesis_examples/presubmult.v
--- a/architecture/xilinx_ug901_synthesis_examples/ram_simple_dual_one_clock.v
+++ b/architecture/xilinx_ug901_synthesis_examples/ram_simple_dual_one_clock.v
--- a/architecture/xilinx_ug901_synthesis_examples/ram_simple_dual_two_clocks.v
+++ b/architecture/xilinx_ug901_synthesis_examples/ram_simple_dual_two_clocks.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_dist.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_dist.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_init_file.data
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_init_file.data
--- a/architecture/xilinx_ug901_synthesis_examples/rams_init_file.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_init_file.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_pipeline.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_pipeline.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_sp_nc.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_sp_nc.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_sp_rf.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_sp_rf.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_sp_rf_rst.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_sp_rf_rst.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_sp_rom.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_sp_rom.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_sp_rom_1.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_sp_rom_1.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_sp_wf.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_sp_wf.v
--- a/architecture/xilinx_ug901_synthesis_examples/rams_tdp_rf_rf.v
+++ b/architecture/xilinx_ug901_synthesis_examples/rams_tdp_rf_rf.v
--- a/architecture/xilinx_ug901_synthesis_examples/registers_1.v
+++ b/architecture/xilinx_ug901_synthesis_examples/registers_1.v
--- a/architecture/xilinx_ug901_synthesis_examples/sfir_shifter.v
+++ b/architecture/xilinx_ug901_synthesis_examples/sfir_shifter.v
--- a/architecture/xilinx_ug901_synthesis_examples/shift_registers_0.v
+++ b/architecture/xilinx_ug901_synthesis_examples/shift_registers_0.v
--- a/architecture/xilinx_ug901_synthesis_examples/shift_registers_1.v
+++ b/architecture/xilinx_ug901_synthesis_examples/shift_registers_1.v
--- a/architecture/xilinx_ug901_synthesis_examples/squarediffmacc.v
+++ b/architecture/xilinx_ug901_synthesis_examples/squarediffmacc.v
--- a/architecture/xilinx_ug901_synthesis_examples/squarediffmult.v
+++ b/architecture/xilinx_ug901_synthesis_examples/squarediffmult.v
--- a/architecture/xilinx_ug901_synthesis_examples/top_mux.v
+++ b/architecture/xilinx_ug901_synthesis_examples/top_mux.v
--- a/architecture/xilinx_ug901_synthesis_examples/tristates_1.v
+++ b/architecture/xilinx_ug901_synthesis_examples/tristates_1.v
--- a/architecture/xilinx_ug901_synthesis_examples/tristates_2.v
+++ b/architecture/xilinx_ug901_synthesis_examples/tristates_2.v
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_read_first.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_read_first.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_black_box_1.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_black_box_1.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_ram_1b.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_ram_1b.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_nc.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_nc.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_rf.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_rf.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_wf.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_wf.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmacc.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmacc.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynamic_shift_registers_1.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynamic_shift_registers_1.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_fsm_1.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_fsm_1.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_latches.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_latches.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_macc.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_macc.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_mult_unsigned.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_mult_unsigned.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_presubmult.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_presubmult.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_one_clock.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_one_clock.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_two_clocks.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_two_clocks.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_dist.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_dist.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_nc.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_nc.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom_1.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom_1.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_tdp_rf_rf.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_tdp_rf_rf.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_sfir_shifter.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_sfir_shifter.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_0.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_0.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_1.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_1.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmacc.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmacc.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_top_mux.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_top_mux.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_no_change.v
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_no_change.v
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_read_first.v
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_read_first.v
--- a/architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_write_first.v
+++ b/architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_write_first.v
--- a/architecture_reviewed/synth_sf2/synth_sf2_fully_selected_fail.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_fully_selected_fail.ys
--- a/architecture_reviewed/synth_sf2/synth_sf2_vlog.ys
+++ b/architecture_reviewed/synth_sf2/synth_sf2_vlog.ys
--- a/architecture_reviewed/synth_sf2/top.v
+++ b/architecture_reviewed/synth_sf2/top.v
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_clkbuf.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_clkbuf.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_edif.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_edif.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_json.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_json.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_noflatten.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_noflatten.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_noiobs.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_noiobs.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_retime.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_retime.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_run.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_run.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_top.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_top.ys
--- a/architecture_reviewed/synth_sf2_lcov/synth_sf2_vlog.ys
+++ b/architecture_reviewed/synth_sf2_lcov/synth_sf2_vlog.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_abc9.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_abc9.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_abc9_retime_fail.pat
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_abc9_retime_fail.pat
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_abc9_retime_fail.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_abc9_retime_fail.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s_abc9.pat
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s_abc9.pat
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s_abc9.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s_abc9.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6v.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6v.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc7.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc7.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xcu.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xcu.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xcup.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_arch_xcup.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_blif.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_blif.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_dsp.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_dsp.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_edif.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_edif.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_flatten.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_flatten.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_flatten_before_abc.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_flatten_before_abc.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_fully_selected_fail.pat
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_fully_selected_fail.pat
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_fully_selected_fail.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_fully_selected_fail.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_invalid_arch_fail.pat
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_invalid_arch_fail.pat
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_invalid_arch_fail.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_invalid_arch_fail.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_iopad.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_iopad.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_ise.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_ise.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_nobram.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_nobram.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_nocarry.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_nocarry.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_noclkbuf.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_noclkbuf.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_nodram.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_nodram.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_nodsp.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_nodsp.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_noiopad.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_noiopad.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_nosrl.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_nosrl.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_nowidelut.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_nowidelut.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_nowidelut_abc9.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_nowidelut_abc9.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_retime.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_retime.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_run.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_run.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_top.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_top.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_vpr.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_vpr.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_widemux.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_widemux.ys
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_widemux_1_fail.pat
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_widemux_1_fail.pat
--- a/architecture_reviewed/synth_xilinx/synth_xilinx_widemux_1_fail.ys
+++ b/architecture_reviewed/synth_xilinx/synth_xilinx_widemux_1_fail.ys
--- a/architecture_reviewed/synth_xilinx/top.v
+++ b/architecture_reviewed/synth_xilinx/top.v
--- a/architecture_reviewed/synth_xilinx/top_bram.v
+++ b/architecture_reviewed/synth_xilinx/top_bram.v
--- a/architecture_reviewed/synth_xilinx/top_dpram.v
+++ b/architecture_reviewed/synth_xilinx/top_dpram.v
--- a/architecture_reviewed/synth_xilinx/top_dsp.v
+++ b/architecture_reviewed/synth_xilinx/top_dsp.v
--- a/architecture_reviewed/synth_xilinx/top_dsp_simd.v
+++ b/architecture_reviewed/synth_xilinx/top_dsp_simd.v
--- a/architecture_reviewed/synth_xilinx/top_mux.v
+++ b/architecture_reviewed/synth_xilinx/top_mux.v
--- a/architecture_reviewed/synth_xilinx/top_nocarry.v
+++ b/architecture_reviewed/synth_xilinx/top_nocarry.v
--- a/architecture_reviewed/synth_xilinx/top_nosrl.v
+++ b/architecture_reviewed/synth_xilinx/top_nosrl.v
--- a/architecture_reviewed/synth_xilinx/top_srl.v
+++ b/architecture_reviewed/synth_xilinx/top_srl.v
--- a/architecture_reviewed/synth_xilinx/top_wide_ffs.v
+++ b/architecture_reviewed/synth_xilinx/top_wide_ffs.v
--- a/architecture_reviewed/synth_xilinx/xilinx_srl.ys
+++ b/architecture_reviewed/synth_xilinx/xilinx_srl.ys
--- a/architecture_reviewed/synth_xilinx_dsp/assert_area.py
+++ b/architecture_reviewed/synth_xilinx_dsp/assert_area.py
--- a/architecture_reviewed/synth_xilinx_dsp/generate_macc.py
+++ b/architecture_reviewed/synth_xilinx_dsp/generate_macc.py
--- a/architecture_reviewed/synth_xilinx_dsp/generate_mul.py
+++ b/architecture_reviewed/synth_xilinx_dsp/generate_mul.py
--- a/architecture_reviewed/synth_xilinx_dsp/generate_muladd.py
+++ b/architecture_reviewed/synth_xilinx_dsp/generate_muladd.py
--- a/architecture_reviewed/synth_xilinx_dsp/macc_25s_18s__49bitaccum.v
+++ b/architecture_reviewed/synth_xilinx_dsp/macc_25s_18s__49bitaccum.v
--- a/architecture_reviewed/synth_xilinx_dsp/mul_25s_18s_keepABP_.v
+++ b/architecture_reviewed/synth_xilinx_dsp/mul_25s_18s_keepABP_.v
--- a/architecture_reviewed/synth_xilinx_dsp/mul_32_32_keepB_.v
+++ b/architecture_reviewed/synth_xilinx_dsp/mul_32_32_keepB_.v
--- a/architecture_reviewed/synth_xilinx_dsp/run-test.sh
+++ b/architecture_reviewed/synth_xilinx_dsp/run-test.sh
--- a/architecture_reviewed/synth_xilinx_dsp/ug901a.v
+++ b/architecture_reviewed/synth_xilinx_dsp/ug901a.v
--- a/architecture_reviewed/synth_xilinx_dsp/ug901b.v
+++ b/architecture_reviewed/synth_xilinx_dsp/ug901b.v
--- a/architecture_reviewed/synth_xilinx_mux/assert_area.py
+++ b/architecture_reviewed/synth_xilinx_mux/assert_area.py
--- a/architecture_reviewed/synth_xilinx_mux/run-test.sh
+++ b/architecture_reviewed/synth_xilinx_mux/run-test.sh
--- a/architecture_reviewed/synth_xilinx_srl/multiclock.v
+++ b/architecture_reviewed/synth_xilinx_srl/multiclock.v
--- a/architecture_reviewed/synth_xilinx_srl/multiclock_var_len.v
+++ b/architecture_reviewed/synth_xilinx_srl/multiclock_var_len.v
--- a/architecture_reviewed/synth_xilinx_srl/multien.v
+++ b/architecture_reviewed/synth_xilinx_srl/multien.v
--- a/architecture_reviewed/synth_xilinx_srl/multien_var_len.v
+++ b/architecture_reviewed/synth_xilinx_srl/multien_var_len.v
--- a/architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v
+++ b/architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v
--- a/architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v
+++ b/architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v
--- a/architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v
+++ b/architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v
--- a/architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v
+++ b/architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v
--- a/architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v
+++ b/architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v
--- a/architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v
+++ b/architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v
--- a/architecture_reviewed/synth_xilinx_srl/rotate_3.v
+++ b/architecture_reviewed/synth_xilinx_srl/rotate_3.v
--- a/architecture_reviewed/synth_xilinx_srl/rotate_3_fdre.v
+++ b/architecture_reviewed/synth_xilinx_srl/rotate_3_fdre.v
--- a/architecture_reviewed/synth_xilinx_srl/rotate_3_var_len.v
+++ b/architecture_reviewed/synth_xilinx_srl/rotate_3_var_len.v
--- a/architecture_reviewed/synth_xilinx_srl/rotate_7_fdre_param.v
+++ b/architecture_reviewed/synth_xilinx_srl/rotate_7_fdre_param.v
--- a/architecture_reviewed/synth_xilinx_srl/rotate_7_fdre_reset.v
+++ b/architecture_reviewed/synth_xilinx_srl/rotate_7_fdre_reset.v
--- a/architecture_reviewed/synth_xilinx_srl/run-test.sh
+++ b/architecture_reviewed/synth_xilinx_srl/run-test.sh
--- a/architecture_reviewed/synth_xilinx_srl/sr_fixed_length_other_users_port.v
+++ b/architecture_reviewed/synth_xilinx_srl/sr_fixed_length_other_users_port.v
--- a/architecture_reviewed/synth_xilinx_srl/sr_fixed_length_other_users_xor.v
+++ b/architecture_reviewed/synth_xilinx_srl/sr_fixed_length_other_users_xor.v
--- a/architecture_reviewed/synth_xilinx_srl/sr_var_length_other_users_port.v
+++ b/architecture_reviewed/synth_xilinx_srl/sr_var_length_other_users_port.v
--- a/architecture_reviewed/synth_xilinx_srl/sr_var_length_other_users_xor.v
+++ b/architecture_reviewed/synth_xilinx_srl/sr_var_length_other_users_xor.v
--- a/architecture_reviewed/synth_xilinx_srl/test17a.v
+++ b/architecture_reviewed/synth_xilinx_srl/test17a.v
--- a/architecture_reviewed/synth_xilinx_srl/test17b.v
+++ b/architecture_reviewed/synth_xilinx_srl/test17b.v
--- a/architecture_reviewed/synth_xilinx_srl/test17c.v
+++ b/architecture_reviewed/synth_xilinx_srl/test17c.v
--- a/architecture_reviewed/synth_xilinx_srl/test17d.v
+++ b/architecture_reviewed/synth_xilinx_srl/test17d.v
--- a/architecture_reviewed/synth_xilinx_srl/test17e.v
+++ b/architecture_reviewed/synth_xilinx_srl/test17e.v
--- a/architecture_reviewed/synth_xilinx_srl/test20.v
+++ b/architecture_reviewed/synth_xilinx_srl/test20.v
--- a/architecture_reviewed/synth_xilinx_srl/test21a.v
+++ b/architecture_reviewed/synth_xilinx_srl/test21a.v
--- a/architecture_reviewed/synth_xilinx_srl/test21b.v
+++ b/architecture_reviewed/synth_xilinx_srl/test21b.v
--- a/architecture_reviewed/synth_xilinx_srl/ug901a.v
+++ b/architecture_reviewed/synth_xilinx_srl/ug901a.v
--- a/architecture_reviewed/synth_xilinx_srl/ug901b.v
+++ b/architecture_reviewed/synth_xilinx_srl/ug901b.v
--- a/architecture_reviewed/synth_xilinx_srl/ug901c.v
+++ b/architecture_reviewed/synth_xilinx_srl/ug901c.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_sdp_read_wider.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_sdp_read_wider.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_sdp_write_wider.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_sdp_write_wider.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_tdp_read_first.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_tdp_read_first.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_tdp_write_first.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_tdp_write_first.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/black_box_1.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/black_box_1.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_ram_1b.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_ram_1b.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_nc.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_nc.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_readfirst2.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_readfirst2.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_rf.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_rf.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_wf.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_wf.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/cmacc.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/cmacc.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/cmult.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/cmult.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/dynamic_shift_registers_1.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/dynamic_shift_registers_1.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/dynpreaddmultadd.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/dynpreaddmultadd.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/fsm_1.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/fsm_1.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/latches.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/latches.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/macc.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/macc.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/mult_unsigned.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/mult_unsigned.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/presubmult.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/presubmult.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/ram_simple_dual_one_clock.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/ram_simple_dual_one_clock.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/ram_simple_dual_two_clocks.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/ram_simple_dual_two_clocks.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_dist.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_dist.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_init_file.data
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_init_file.data
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_init_file.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_init_file.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_pipeline.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_pipeline.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_nc.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_nc.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rf.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rf.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rf_rst.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rf_rst.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rom.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rom.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rom_1.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rom_1.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_wf.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_wf.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_tdp_rf_rf.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/rams_tdp_rf_rf.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/registers_1.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/registers_1.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/sfir_shifter.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/sfir_shifter.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/shift_registers_0.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/shift_registers_0.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/shift_registers_1.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/shift_registers_1.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/squarediffmacc.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/squarediffmacc.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/squarediffmult.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/squarediffmult.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/top_mux.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/top_mux.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/tristates_1.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/tristates_1.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/tristates_2.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/tristates_2.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_read_first.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_read_first.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_black_box_1.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_black_box_1.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_ram_1b.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_ram_1b.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_nc.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_nc.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_rf.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_rf.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_wf.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_wf.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_cmacc.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_cmacc.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_dynamic_shift_registers_1.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_dynamic_shift_registers_1.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_fsm_1.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_fsm_1.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_latches.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_latches.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_macc.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_macc.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_mult_unsigned.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_mult_unsigned.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_presubmult.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_presubmult.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_one_clock.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_one_clock.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_two_clocks.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_two_clocks.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_dist.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_dist.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_nc.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_nc.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom_1.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom_1.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_tdp_rf_rf.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_tdp_rf_rf.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_sfir_shifter.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_sfir_shifter.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_0.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_0.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_1.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_1.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmacc.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmacc.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_top_mux.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_top_mux.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_no_change.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_no_change.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_read_first.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_read_first.v
--- a/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_write_first.v
+++ b/architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_write_first.v