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yosys-tests
Commit 743baf58 by SergeyDegtyar
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Rename test group back to 'architecture'

parent 0d34ab09
Showing with 5224 additions and 5224 deletions
Makefile
SUBDIRS := architecture_reviewed backends bigsim equiv frontends misc regression simple yosys
SUBDIRS := architecture backends bigsim equiv frontends misc regression simple yosys
ifeq ($(VERIFIC),1)
export VERIFIC=1
......
architecture/synth_sf2/synth_sf2_fully_selected_fail.ys 0 → 100644
read_verilog ../top.v
select dffe
synth_sf2
write_verilog synth.v
architecture/synth_sf2/synth_sf2_vlog.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -vlog vlog.v # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -vlog vlog.v # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
architecture/synth_sf2_lcov/synth_sf2.ys 0 → 100644
read_verilog ../top.v
synth_sf2
architecture/synth_sf2_lcov/synth_sf2_clkbuf.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -clkbuf
architecture/synth_sf2_lcov/synth_sf2_edif.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -edif edif.edif
architecture/synth_sf2_lcov/synth_sf2_json.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -json json.json
architecture/synth_sf2_lcov/synth_sf2_noflatten.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -noflatten
architecture/synth_sf2_lcov/synth_sf2_noiobs.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -noiobs
architecture/synth_sf2_lcov/synth_sf2_retime.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -retime
architecture/synth_sf2_lcov/synth_sf2_run.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -run begin:json
architecture/synth_sf2_lcov/synth_sf2_top.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -top dff
architecture/synth_sf2_lcov/synth_sf2_vlog.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -vlog vlog.v
architecture/synth_xilinx/synth_xilinx.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top adff
proc
#-assert option was skipped because of unproven cellss
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
select -assert-none t:BUFG t:FDCE %% t:* %D
architecture/synth_xilinx/synth_xilinx_abc9.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_abc9_retime_fail.pat 0 → 100644
ERROR: -retime option not currently compatible with -abc9!
architecture/synth_xilinx/synth_xilinx_abc9_retime_fail.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -abc9 -retime
write_verilog synth.v
architecture/synth_xilinx/synth_xilinx_arch_xc6s.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.pat 0 → 100644
Warning: 'synth_xilinx -abc9' not currently supported for the 'xc6s' family, will use timing for 'xc7' instead.
architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
tee -o result.out equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xc6v.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xc7.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc7 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc7 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xcu.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcu # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcu # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xcup.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcup # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcup # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_blif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_dsp.ys 0 → 100644
read_verilog ../top_dsp_simd.v
design -save read
hierarchy -top simd
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd simd # Constrain all select calls below inside the top module
stat
select -assert-count 3 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
architecture/synth_xilinx/synth_xilinx_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_flatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_flatten_before_abc.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten_before_abc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten_before_abc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/synth_xilinx/synth_xilinx_fully_selected_fail.ys 0 → 100644
read_verilog ../top.v
select dffe
synth_xilinx
architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.pat 0 → 100644
ERROR: Invalid Xilinx -family setting: 'zinq7000'.
architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -arch zinq7000
architecture/synth_xilinx/synth_xilinx_iopad.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -iopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -iopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 2 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
architecture/synth_xilinx/synth_xilinx_ise.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 2 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
architecture/synth_xilinx/synth_xilinx_nobram.ys 0 → 100644
read_verilog ../top_bram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -nobram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:BUFG
select -assert-count 35 t:FDRE
select -assert-count 3 t:LUT2
select -assert-count 4 t:LUT4
select -assert-count 16 t:LUT6
select -assert-count 8 t:MUXF7
select -assert-count 32 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
architecture/synth_xilinx/synth_xilinx_nocarry.ys 0 → 100644
read_verilog ../top_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT4
select -assert-count 4 t:LUT6
select -assert-count 5 t:MUXCY
select -assert-count 6 t:XORCY
select -assert-none t:LUT2 t:LUT4 t:LUT6 t:MUXCY t:XORCY %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nocarry # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4
select -assert-count 4 t:LUT6
select -assert-none t:LUT2 t:LUT4 t:LUT6 %% t:* %D
architecture/synth_xilinx/synth_xilinx_noclkbuf.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noclkbuf # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:FDRE
select -assert-none t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_nodram.ys 0 → 100644
read_verilog ../top_dpram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 2 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 6 t:RAM64X1D
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -nodram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 2 t:BUFG
select -assert-count 390 t:FDRE
select -assert-count 90 t:LUT2
select -assert-count 10 t:LUT4
select -assert-count 155 t:LUT6
select -assert-count 32 t:MUXF7
select -assert-count 2 t:MUXF8
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture/synth_xilinx/synth_xilinx_nodsp.ys 0 → 100644
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 15 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 4 t:LUT4
select -assert-count 5 t:LUT5
select -assert-count 45 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 9 t:MUXF7
select -assert-count 3 t:MUXF8
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
architecture/synth_xilinx/synth_xilinx_noiopad.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_nosrl.ys 0 → 100644
read_verilog ../top_nosrl.v
design -save read
hierarchy -top xilinx_srl_static_test
proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D
design -load read
hierarchy -top xilinx_srl_static_test
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nosrl # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 5 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_nowidelut.ys 0 → 100644
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 6 t:LUT4
select -assert-count 1 t:LUT5
select -assert-count 33 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 1 t:MUXF7
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:LUT2
select -assert-count 6 t:LUT3
select -assert-count 5 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:XORCY %% t:* %D
architecture/synth_xilinx/synth_xilinx_nowidelut_abc9.ys 0 → 100644
read_verilog ../top_dsp.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 3 t:CARRY4
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 8 t:LUT4
select -assert-count 21 t:LUT5
select -assert-count 16 t:LUT6
select -assert-none t:CARRY4 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 %% t:* %D
architecture/synth_xilinx/synth_xilinx_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -run begin:blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -run begin:blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_vpr.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_widemux.ys 0 → 100644
read_verilog ../top_mux.v
design -save read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 3 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture/synth_xilinx/synth_xilinx_widemux_1_fail.pat 0 → 100644
ERROR: -widemux value must be 0 or >= 2.
architecture/synth_xilinx/synth_xilinx_widemux_1_fail.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -widemux 1
architecture/synth_xilinx/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
architecture/synth_xilinx/top_bram.v 0 → 100644
// Single-Port Block RAM Read-First Mode
// rams_sp_rf.v
module top (clk, en, we, addr, di, dout);
input clk;
input we;
input en;
input [8:0] addr;
input [7:0] di;
output [7:0] dout;
reg [7:0] RAM [511:0];
reg [7:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr]<=di;
dout <= RAM[addr];
end
end
endmodule
architecture/synth_xilinx/top_dpram.v 0 → 100644
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
*/
module top (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 6;
parameter data_width = 6;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
architecture/synth_xilinx/top_dsp.v 0 → 100644
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
architecture/synth_xilinx/top_dsp_simd.v 0 → 100644
module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24);
generate
genvar i;
// 4 x 12-bit adder
for (i = 0; i < 4; i++)
assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12];
// 2 x 24-bit subtract
for (i = 0; i < 2; i++)
assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24];
endgenerate
reg [3*12-1:0] ro;
always @* begin
ro[0*12+:12] = a[0*10+:10] + b[0*10+:10];
ro[1*12+:12] = a[1*10+:10] + b[1*10+:10];
ro[2*12+:12] = a[2*8+:8] + b[2*8+:8];
end
assign o12[4*12+:3*12] = ro;
endmodule
architecture/synth_xilinx/top_mux.v 0 → 100644
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
architecture/synth_xilinx/top_nocarry.v 0 → 100644
module top
(
input [2:0] x,
input [2:0] y,
output [5:0] A,
);
assign A = x * y;
endmodule
architecture/synth_xilinx/top_nosrl.v 0 → 100644
module xilinx_srl_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[3], shift1[3]};
endmodule
architecture/synth_xilinx/top_srl.v 0 → 100644
module top (
out,
out1,
clk,
in
);
output [7:0] out;
output [7:0] out1;
input signed clk, in;
reg signed [7:0] out;
reg signed [7:0] out1;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
always @(posedge clk)
begin
out1 <= out1 >> 1;
out1[7] <= in;
end
endmodule
architecture/synth_xilinx/top_wide_ffs.v 0 → 100644
module dff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
architecture/synth_xilinx/xilinx_srl.ys 0 → 100644
read_verilog ../top_srl.v
design -save read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
#select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -minlen 1
stat
select -assert-count 8 t:$__XILINX_SHREG_
select -assert-count 1 t:BUFG
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -variable
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -variable -minlen 1
stat
select -assert-count 8 t:$__XILINX_SHREG_
select -assert-count 1 t:BUFG
architecture/synth_xilinx_dsp/assert_area.py 0 → 100755
#!/usr/bin/python3
import glob
import re
import os
re_mux = re.compile(r'(mul|muladd|macc)_(\d+)(s?)_(\d+)(s?)(_(\d+)(s?))?_(A?B?C?M?P?)_A?B?C?M?P?\.v')
for fn in glob.glob('*.v'):
m = re_mux.match(fn)
if not m: continue
macc = m.group(1) == 'macc'
muladd = m.group(1) == 'muladd'
A,B = map(int, m.group(2,4))
Asigned,Bsigned = m.group(3,5)
if m.group(6):
C = int(m.group(7))
Csigned = m.group(8)
else:
C = 0
Areg = 'A' in m.group(9)
Breg = 'B' in m.group(9)
Mreg = 'M' in m.group(9)
Preg = 'P' in m.group(9) or macc
if A < B:
A,B = B,A
Asigned,Bsigned = Bsigned,Asigned
if not (Asigned and Bsigned):
A += 1
B += 1
Asigned = Bsigned = 1
if C > 0 and not Csigned:
C += 1
Csigned = 1
X = 1 + max(0,A-25+16) // 17
Y = 1 + max(0,B-18+16) // 17
count_MAC = X * Y
count_DFF = 0
if Mreg and (A > 25 or B > 18):
count_DFF += A + B
if not macc and (A > 25) ^ (B > 18):
count_DFF -= 1 # For pure multipliers with just one big dimension,
# expect last slice to absorb at least one register
if Preg and (A > 25 or B > 18 or C > 48):
count_DFF += max(A + B, C)
if macc:
count_DFF += 5 # In my testcases, accumulator is always
# 5bits bigger than multiplier result
elif ((A > 25) ^ (B > 18)) and C <= 48:
count_DFF -= 1 # For pure multipliers with just one big dimension,
# expect last slice to absorb at least one register
# TODO: More assert on number of CARRY and LUTs
count_CARRY = ''
if macc or muladd:
if A <= 25 and B <= 18 and C <= 48:
count_CARRY = '; select t:XORCY -assert-none; select t:LUT* -assert-none';
elif A <= 25 or B <= 18:
count_CARRY = '; select t:XORCY -assert-none; select t:LUT* -assert-none';
bn,_ = os.path.splitext(fn)
with open(fn, 'a') as f:
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd {0}; select t:DSP48E1 -assert-max {1}; select t:FD* -assert-max {2}{3}";
endmodule
`endif
'''.format(os.path.splitext(fn)[0], count_MAC, count_DFF, count_CARRY), file=f)
architecture/synth_xilinx_dsp/generate_macc.py 0 → 100644
#!/usr/bin/env python3
from common_macc import gen_macc
ARange = ['17','17s','18','18s','19','19s','24','24s','25','25s','36','36s','49','49s','50','50s','75','75s']
BRange = ['17','17s','18','18s','19','19s','27','27s','34','34s','35','35s','36','36s']
if __name__ == "__main__":
gen_macc(['24','49s'], ['17','36s'], reg="ABMP")
gen_macc(ARange, BRange, reg="")
architecture/synth_xilinx_dsp/generate_mul.py 0 → 100644
#!/usr/bin/env python3
from common_mul import gen_mul
ARange = ['17','17s','18','18s','19','19s','24','24s','25','25s','36','36s','49','49s','50','50s','75','75s']
BRange = ['17','17s','18','18s','19','19s','27','27s','34','34s','35','35s','36','36s']
if __name__ == "__main__":
gen_mul(['24','49s'], ['17','36s'], reg="ABMP")
gen_mul(ARange, BRange, reg="")
architecture/synth_xilinx_dsp/generate_muladd.py 0 → 100644
#!/usr/bin/env python3
from common_muladd import gen_muladd
ARange = ['24','24s','25','25s','36','36s']
BRange = ['17','17s','18','18s','19','19s']
CRange = ['32','32s','48','48s','96','96s']
if __name__ == "__main__":
gen_muladd(['24','49s'], ['17','36s'], ['47','96s'], reg="ABMP")
gen_muladd(ARange, BRange, CRange, reg="")
architecture/synth_xilinx_dsp/macc_25s_18s__49bitaccum.v 0 → 100644
(* top *)
module macc_25s_18s__49bitaccum #(parameter AW=25, BW=18, AREG=0, BREG=0, MREG=0) (input clk, CEA, CEB, CEM, CEP, input signed [AW-1:0] A, input signed [BW-1:0] B, output reg signed [49-1:0] P);
reg signed [AW-1:0] Ar;
reg signed [BW-1:0] Br;
reg signed [AW+BW-1:0] Mr;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (MREG) begin
always @(posedge clk) if (1) Mr <= Ar * Br;
end
else
always @* Mr <= Ar * Br;
always @(posedge clk) if (1) P <= P + Mr;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd macc_25s_18s__49bitaccum; select t:DSP48E1 -assert-count 1; select t:FD* -assert-count 49; select t:XORCY -assert-count 49; select t:LUT2 -assert-count 97";
endmodule
`endif
architecture/synth_xilinx_dsp/mul_25s_18s_keepABP_.v 0 → 100644
(* top *)
module mul_25s_18s_keepABP_ #(parameter AW=25, BW=18, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input signed [AW-1:0] A, input signed [BW-1:0] B, (* keep *) output reg signed [AW+BW-1:0] P);
(* keep *) reg signed [AW-1:0] Ar;
(* keep *) reg signed [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd mul_25s_18s_keepABP_; select t:DSP48E1 -assert-count 1; select t:FD* -assert-count 43";
endmodule
`endif
architecture/synth_xilinx_dsp/mul_32_32_keepB_.v 0 → 100644
(* top *)
module mul_32_32_keepB_ #(parameter AW=32, BW=32, AREG=1, BREG=1, PREG=0) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, output reg [AW+BW-1:0] P);
reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd mul_32_32_keepB_; select t:DSP48E1 -assert-count 4; select t:FD* -assert-count 32";
endmodule
`endif
architecture/synth_xilinx_dsp/run-test.sh 0 → 100755
#!/bin/bash
set -e
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \
synth_xilinx; \
design -copy-from __test *; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="$EXTRA_FLAGS"
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/common.py -O common_mul.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/macc/common.py -O common_macc.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/muladd/common.py -O common_muladd.py -o /dev/null
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_macc.py
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_muladd.py
python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed mul_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed macc_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed muladd_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
architecture/synth_xilinx_dsp/ug901a.v 0 → 100644
// Signed 40-bit streaming accumulator with 16-bit inputs
// File: HDL_Coding_Techniques/multipliers/multipliers4.v
//
// Source:
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
//
(* top *)
module ug901a # (parameter SIZEIN = 16, SIZEOUT = 40) (
input clk, ce, sload,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg sload_reg;
reg signed [2*SIZEIN-1:0] mult_reg;
reg signed [SIZEOUT-1:0] adder_out, old_result;
always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
if (sload_reg)
old_result <= 0;
else
// 'sload' is now active (=low) and opens the accumulation loop.
// The accumulator takes the next multiplier output in
// the same cycle.
old_result <= adder_out;
end
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
mult_reg <= a_reg * b_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + mult_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd ug901a; select t:DSP48E1 -assert-count 1; select t:FDRE -assert-count 1; select -assert-none t:DSP48E1 t:BUFG t:FDRE %% t:* %D";
endmodule
`endif
architecture/synth_xilinx_dsp/ug901b.v 0 → 100644
// 8-Tap Even Symmetric Systolic FIR
//
// Source:
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.93
//
(* top *)
module ug901b #(parameter nbtap = 4, dsize = 16, psize = 2*dsize) (
input clk,
input signed [dsize-1:0] datain,
output signed [2*dsize-1:0] firout
);
wire signed [dsize-1:0] h [nbtap-1:0];
wire signed [dsize-1:0] arraydata [nbtap-1:0];
wire signed [psize-1:0] arrayprod [nbtap-1:0];
wire signed [dsize-1:0] shifterout;
reg signed [dsize-1:0] dataz [nbtap-1:0];
assign h[0] = 7;
assign h[1] = 14;
assign h[2] = -138;
assign h[3] = 129;
assign firout = arrayprod[nbtap-1]; // Connect last product to output
sfir_shifter #(dsize, nbtap) shifter_inst0 (
clk,
datain,
shifterout);
generate
genvar I;
for (I=0; I<nbtap; I=I+1)
if (I==0)
sfir_even_symmetric_systolic_element #(dsize) fte_inst0 (
clk,
h[I],
datain,
shifterout,
{32{1'b0}},
arraydata[I],
arrayprod[I]);
else
sfir_even_symmetric_systolic_element #(dsize) fte_inst (
clk,
h[I],
arraydata[I-1],
shifterout,
arrayprod[I-1],
arraydata[I],
arrayprod[I]);
endgenerate
endmodule
(* gentb_skip *) // Prevents Yosys' test_autotb from operating on this module
(* dont_touch = "yes" *)
module sfir_shifter #(parameter dsize = 16, nbtap = 4) (
input clk,
input [dsize-1:0] datain,
output [dsize-1:0] dataout
);
(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
integer i;
always @(posedge clk)
begin
tmp[0] <= datain;
for (i=0; i<=2*nbtap-2; i=i+1)
tmp[i+1] <= tmp[i];
end
assign dataout = tmp[2*nbtap-1];
endmodule
(* gentb_skip *) // Prevents Yosys' test_autotb from operating on this module
module sfir_even_symmetric_systolic_element #(parameter dsize = 16) (
input clk,
input signed [dsize-1:0] coeffin, datain, datazin,
input signed [2*dsize-1:0] cascin,
output signed [dsize-1:0] cascdata,
output reg signed [2*dsize-1:0] cascout
);
reg signed [dsize-1:0] coeff;
reg signed [dsize-1:0] data;
reg signed [dsize-1:0] dataz;
reg signed [dsize-1:0] datatwo;
reg signed [dsize:0] preadd;
reg signed [2*dsize-1:0] product;
assign cascdata = datatwo;
always @(posedge clk)
begin
coeff <= coeffin;
data <= datain;
datatwo <= data;
dataz <= datazin;
preadd <= datatwo + dataz;
product <= preadd * coeff;
cascout <= product + cascin;
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd ug901b; flatten; select t:DSP48E1 -assert-count 4; select t:FDRE -assert-count 128; select t:SRL16E -assert-count 16; select -assert-none t:DSP48E1 t:BUFG t:FDRE t:SRL16E %% t:* %D";
endmodule
`endif
architecture/synth_xilinx_mux/assert_area.py 0 → 100755
#!/usr/bin/python3
import glob
import re
import os
re_mux = re.compile(r'mux_(index|case|if_bal|if_unbal)_(\d+)_(\d+)\.v')
area = {}
# 1 2 3 4 5 6 F7 F8
area[2] = [ 0, 0, 1, 0, 0, 0, 0, 0 ]
area[3] = [ 0, 0, 0, 0, 1, 0, 0, 0 ]
area[4] = [ 0, 0, 0, 0, 0, 0, 2, 1 ]
area[5] = [ 0, 0, 1, 0, 0, 0, 2, 1 ]
area[7] = [ 0, 0, 3, 0, 0, 0, 2, 1 ]
area[8] = [ 0, 0, 4, 0, 0, 0, 2, 1 ]
area[9] = [ 0, 0, 3, 0, 1, 0, 2, 1 ]
area[15] = [ 0, 0, 0, 0, 1, 3, 2, 1 ]
area[16] = [ 0, 0, 0, 0, 0, 4, 2, 1 ]
area[17] = [ 0, 0, 1, 0, 0, 4, 2, 1 ]
area[31] = [ 0, 0, 1, 0, 1, 7, 4, 2 ]
area[32] = [ 0, 0, 1, 0, 0, 8, 4, 2 ]
area[33] = [ 0, 0, 0, 0, 1, 8, 4, 2 ]
area[63] = [ 0, 0, 0, 0, 1,15,10, 5 ]
area[64] = [ 0, 0, 0, 0, 0,16,10, 5 ]
area[65] = [ 0, 0, 1, 0, 0,16,10, 5 ]
area[127] = [ 0, 0, 4, 0, 1,31,18, 9 ]
area[128] = [ 0, 0, 4, 0, 0,32,18, 9 ]
area[129] = [ 0, 0, 3, 0, 1,32,18, 9 ]
area[255] = [ 0, 0, 0, 0, 1,67,34,17 ]
area[256] = [ 0, 0, 0, 0, 0,68,34,17 ]
area[257] = [ 0, 0, 1, 0, 0,68,34,17 ]
for fn in glob.glob('*.v'):
m = re_mux.match(fn)
if not m: continue
N,W = map(int, m.group(2,3))
assert N in area
bn,_ = os.path.splitext(fn)
with open(fn, 'a') as f:
assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd; %s";
endmodule
`endif
''' % '; '.join(assert_area), file=f)
architecture/synth_xilinx_mux/run-test.sh 0 → 100755
#!/bin/bash
set -e
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/generate.py -O generate_small.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/common.py -O common.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
python3 generate_small.py
python3 generate_large.py
python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \
synth_xilinx -abc9 -widemux 4; \
design -copy-from __test *; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
# Spot tests for -widemux thresholds
set +e
../../../../../yosys -qp "synth_xilinx -widemux 1" 2> /dev/null
if [ $? -eq 0 ]; then
echo "Expected error"
exit 1
fi
set -e
../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 1 t:MUXF7" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-count 6 t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 6 t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 9; select -assert-none t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 8; select -assert-none t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 7; select -assert-count 15 t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 6; select -assert-count 15 t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 18; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 17; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 16; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 15; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
architecture/synth_xilinx_srl/multiclock.v 0 → 100644
(* top *)
module multiclock (input clk1, clk2, i, output q);
reg [6:0] r;
always @(posedge clk1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
always @(posedge clk2)
r[3] <= r[2];
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multiclock; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture/synth_xilinx_srl/multiclock_var_len.v 0 → 100644
(* top *)
module multiclock_var_len (input clk1, clk2, i, input [2:0] l, output q);
reg [6:0] r;
always @(posedge clk1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
always @(posedge clk2)
r[3] <= r[2];
assign q = r[l];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multiclock_var_len; select t:SRL* -assert-count 0; select t:FD* -assert-count 7";
endmodule
`endif
architecture/synth_xilinx_srl/multien.v 0 → 100644
(* top *)
module multiclock (input clk, en1, en2, i, output q);
reg [6:0] r;
always @(posedge clk) begin
if (en1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
if (en2)
r[3] <= r[2];
end
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multiclock; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture/synth_xilinx_srl/multien_var_len.v 0 → 100644
(* top *)
module multien_var_len (input clk, en1, en2, i, input [2:0] l, output q);
reg [6:0] r;
always @(posedge clk) begin
if (en1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
if (en2)
r[3] <= r[2];
end
assign q = r[l];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multien_var_len; select t:SRL* -assert-count 0; select t:FD* -assert-count 7";
endmodule
`endif
architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v 0 → 100644
// Check multi-bit works
// neg_clk_no_enable_with_init_with_inferred_N_width
(* top *)
module neg_clk_no_enable_with_init_with_inferred_N_width #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) int[w] <= { int[w][depth-2:0], i[w] };
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_N_width; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v 0 → 100644
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset
(* top *)
module neg_clk_no_enable_with_init_with_inferred_with_reset #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] };
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_with_reset; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v 0 → 100644
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
(* top *)
module neg_clk_no_enable_with_init_with_inferred_with_reset_var_len #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_with_reset_var_len; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v 0 → 100644
// Check multi-bit works
// pos_clk_no_enable_no_init_not_inferred_N_width
(* top *)
module pos_clk_no_enable_no_init_not_inferred_N_width #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_N_width; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v 0 → 100644
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset
(* top *)
module pos_clk_no_enable_no_init_not_inferred_with_reset #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_with_reset; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v 0 → 100644
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
(* top *)
module pos_clk_no_enable_no_init_not_inferred_with_reset_var_len #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1]));
end
wire [depth-1:0] t;
assign t = int[w][depth:1];
assign q[w] = t[l];
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_with_reset_var_len; select t:SRL* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/rotate_3.v 0 → 100644
(* top *)
module rotate_3 (input clk, output q);
reg [2:0] r;
initial r = 3'b101;
always @(posedge clk)
r <= {r[1:0], r[2]};
assign q = r[2];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_3; select t:SRL* -assert-count 1; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/rotate_3_fdre.v 0 → 100644
(* top *)
module rotate_3_fdre (input clk, output q);
wire [2:0] r;
FDRE #(.INIT(1'b1)) r0 (.C(clk), .CE(1'b1), .D(r[2]), .R(1'b0), .Q(r[0]));
FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]), .Q(r[1]));
FDRE #(.INIT(1'b0)) r2 (.C(clk), .CE(1'b1), .D(r[1]), .R(1'b0), .Q(r[2]));
assign q = r[2];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_3_fdre; select t:SRL* -assert-count 1; select t:FD* -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/rotate_3_var_len.v 0 → 100644
(* top *)
module rotate_3_var_len (input clk, input [1:0] l, output q);
reg [2:0] r;
initial r = 3'b101;
always @(posedge clk)
r <= {r[1:0], r[2]};
assign q = r[l];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_3_var_len; select t:SRL* -assert-count 0; select t:FD* -assert-count 3";
endmodule
`endif
architecture/synth_xilinx_srl/rotate_7_fdre_param.v 0 → 100644
(* top *)
module rotate_7_fdre_param (input clk, output q);
wire [6:0] r;
FDRE #(.INIT(1'b1)) r0 (.C(clk), .CE(1'b1), .D(r[6]), .R(1'b0), .Q(r[0]));
FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]), .R(1'b0), .Q(r[1]));
FDRE #(.INIT(1'b0)) r2 (.C(clk), .CE(1'b1), .D(r[1]), .R(1'b0), .Q(r[2]));
FDRE #(.INIT(1'b1), .IS_C_INVERTED(1)) r3 (.C(clk), .CE(1'b1), .D(r[2]), .R(reset), .Q(r[3]));
FDRE #(.INIT(1'b0)) r4 (.C(clk), .CE(1'b1), .D(r[3]), .R(1'b0), .Q(r[4]));
FDRE #(.INIT(1'b0)) r5 (.C(clk), .CE(1'b1), .D(r[4]), .R(1'b0), .Q(r[5]));
FDRE #(.INIT(1'b0)) r6 (.C(clk), .CE(1'b1), .D(r[5]), .R(1'b0), .Q(r[6]));
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_7_fdre_param; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture/synth_xilinx_srl/rotate_7_fdre_reset.v 0 → 100644
(* top *)
module rotate_7_fdre_reset (input clk, reset, output q);
wire [6:0] r;
FDRE #(.INIT(1'b1)) r0 (.C(clk), .CE(1'b1), .D(r[6]), .R(1'b0), .Q(r[0]));
FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]), .R(1'b0), .Q(r[1]));
FDRE #(.INIT(1'b0)) r2 (.C(clk), .CE(1'b1), .D(r[1]), .R(1'b0), .Q(r[2]));
FDRE #(.INIT(1'b1)) r3 (.C(clk), .CE(1'b1), .D(r[2]), .R(reset), .Q(r[3]));
FDRE #(.INIT(1'b0)) r4 (.C(clk), .CE(1'b1), .D(r[3]), .R(1'b0), .Q(r[4]));
FDRE #(.INIT(1'b0)) r5 (.C(clk), .CE(1'b1), .D(r[4]), .R(1'b0), .Q(r[5]));
FDRE #(.INIT(1'b0)) r6 (.C(clk), .CE(1'b1), .D(r[5]), .R(1'b0), .Q(r[6]));
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_7_fdre_reset; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture/synth_xilinx_srl/run-test.sh 0 → 100755
#!/bin/bash
set -e
shopt -s extglob
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
python3 generate_lfsr.py
python3 ../generate.py
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx -retime; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_port
(* top *)
module sr_fixed_length_other_users_port #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_fixed_length_other_users_port; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_xor
(* top *)
module sr_fixed_length_other_users_xor #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_fixed_length_other_users_xor; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/sr_var_length_other_users_port.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_port
(* top *)
module sr_var_length_other_users_port #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
assign state = int[0];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_var_length_other_users_port; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v 0 → 100644
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_xor
(* top *)
module sr_var_length_other_users_xor #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
assign state = {depth{^int[0]}};
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_var_length_other_users_xor; select t:SRL* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test17a.v 0 → 100644
// Check inference even when not in vector
(* top *)
module test17a (input clk, input i, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) a1 <= i;
always @(posedge clk) a2 <= a1;
always @(posedge clk) a3 <= a2;
always @(posedge clk) a4 <= a3;
always @(posedge clk) a5 <= a4;
always @(posedge clk) a6 <= a5;
always @(posedge clk) a7 <= a6;
always @(posedge clk) a8 <= a7;
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17a; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test17b.v 0 → 100644
// Check inference even when not in vector
(* top *)
module test17b (input clk, input i, input e, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17b; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test17c.v 0 → 100644
// Check inference even when keep attribute specified
(* top *)
module test17c (input clk, input i, input e, output q);
generate
reg a1, a2, a3;
(* keep *) reg a4;
reg a5, a6, a7, a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17c; select t:SRL16E -assert-count 2; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test17d.v 0 → 100644
// Check inference even when keep attribute specified
(* top *)
module test17d (input clk, input i, input e, output q);
generate
reg a1, a2;
(* keep *) reg a3;
(* keep *) reg a4;
reg a5, a6, a7, a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17d; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:BUFG t:SRL16E t:FD* %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/test17e.v 0 → 100644
// Check inference even when keep attribute specified
(* top *)
module test17e (input clk, input i, input e, output q);
generate
reg a1, a2;
(* blah *) reg a3;
reg a4, a5, a6;
(* boo *) reg a7;
reg a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17e; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none;";
endmodule
`endif
architecture/synth_xilinx_srl/test20.v 0 → 100644
(* top *)
module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(negedge clk) if (e) int[d][w] <= i[w];
end
else begin
always @(negedge clk) if (e) int[d][w] <= int[d-1][w];
end
end
end
assign z = int[depth-1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test20; select t:FD* -assert-count 0";
endmodule
`endif
architecture/synth_xilinx_srl/test21a.v 0 → 100644
(* top *)
module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
genvar d;
wire [depth:0] int;
assign int[0] = ^i[width-1:0];
generate
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1]));
end
endgenerate
assign q = int[depth];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21a; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture/synth_xilinx_srl/test21b.v 0 → 100644
(* top *)
module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
reg [depth-1:0] int;
genvar d;
for (d = 0; d < depth; d=d+1)
initial int[d] <= ~(d % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int <= ~^i[width-1:0];
assign q = int;
end
else begin
always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] };
assign q = int[depth-1];
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21b; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture/synth_xilinx_srl/ug901a.v 0 → 100644
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 8-bit Shift Register
// Rising edge clock
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
(* top *)
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk)
begin
if (clken)
shreg <= {shreg[WIDTH-2:0], SI};
end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_0; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/ug901b.v 0 → 100644
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 32-bit Shift Register
// Rising edge clock
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
(* top *)
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
integer i;
always @(posedge clk)
begin
if (clken)
begin
for (i = 0; i < WIDTH-1; i = i+1)
shreg[i+1] <= shreg[i];
shreg[0] <= SI;
end
end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_1; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/synth_xilinx_srl/ug901c.v 0 → 100644
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
(* top *)
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
input [SELWIDTH-1:0] SEL;
output DO;
localparam DATAWIDTH = 2**SELWIDTH;
reg [DATAWIDTH-1:0] data;
assign DO = data[SEL];
always @(posedge CLK)
begin
if (CE == 1'b1)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd dynamic_shift_register_1; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture/xilinx_ug901_synthesis_examples/asym_ram_sdp_read_wider.v 0 → 100644
// Asymmetric port RAM
// Read Wider than Write. Read Statement in loop
//asym_ram_sdp_read_wider.v
module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB);
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkA)
begin
if (enaA) begin
if (weA)
RAM[addrA] <= diA;
end
end
always @(posedge clkB)
begin : ramread
integer i;
reg [log2RATIO-1:0] lsbaddr;
if (enaB) begin
for (i = 0; i < RATIO; i = i+1) begin
lsbaddr = i;
readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
end
end
end
assign doB = readB;
endmodule
architecture/xilinx_ug901_synthesis_examples/asym_ram_sdp_write_wider.v 0 → 100644
// Asymmetric port RAM
// Write wider than Read. Write Statement in a loop.
// asym_ram_sdp_write_wider.v
module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
//parameter WIDTHA = 16;
//parameter WIDTHA = 8;
parameter WIDTHA = 4;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkB) begin
if (enaB) begin
readB <= RAM[addrB];
end
end
assign doB = readB;
always @(posedge clkA)
begin : ramwrite
integer i;
reg [log2RATIO-1:0] lsbaddr;
for (i=0; i< RATIO; i= i+ 1) begin : write1
lsbaddr = i;
if (enaA) begin
if (weA)
RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
end
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/asym_ram_tdp_read_first.v 0 → 100644
// Asymetric RAM - TDP
// READ_FIRST MODE.
// asym_ram_tdp_read_first.v
module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
parameter WIDTHB = 4;
parameter SIZEB = 1024;
parameter ADDRWIDTHB = 10;
parameter WIDTHA = 16;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA, weB;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
input [WIDTHB-1:0] diB;
output [WIDTHA-1:0] doA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHA-1:0] readA;
reg [WIDTHB-1:0] readB;
always @(posedge clkB)
begin
if (enaB) begin
readB <= RAM[addrB] ;
if (weB)
RAM[addrB] <= diB;
end
end
always @(posedge clkA)
begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr ;
for (i=0; i< RATIO; i= i+ 1) begin
lsbaddr = i;
if (enaA) begin
readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
if (weA)
RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
end
end
end
assign doA = readA;
assign doB = readB;
endmodule
architecture/xilinx_ug901_synthesis_examples/asym_ram_tdp_write_first.v 0 → 100644
// Asymmetric port RAM - TDP
// WRITE_FIRST MODE.
// asym_ram_tdp_write_first.v
module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 32;
parameter ADDRWIDTHB = 8;
//parameter WIDTHA = 16;
parameter WIDTHA = 4;
//parameter SIZEA = 256;
parameter SIZEA = 32;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA, weB;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
input [WIDTHB-1:0] diB;
output [WIDTHA-1:0] doA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHA-1:0] readA;
reg [WIDTHB-1:0] readB;
always @(posedge clkB)
begin
if (enaB) begin
if (weB)
RAM[addrB] = diB;
readB = RAM[addrB] ;
end
end
always @(posedge clkA)
begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr ;
for (i=0; i< RATIO; i= i+ 1) begin
lsbaddr = i;
if (enaA) begin
if (weA)
RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH];
readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}];
end
end
end
assign doA = readA;
assign doB = readB;
endmodule
architecture/xilinx_ug901_synthesis_examples/black_box_1.v 0 → 100644
// Black Box
// black_box_1.v
//
(* black_box *) module black_box1 (in1, in2, dout);
input in1, in2;
output dout;
endmodule
module black_box_1 (DI_1, DI_2, DOUT);
input DI_1, DI_2;
output DOUT;
black_box1 U1 (
.in1(DI_1),
.in2(DI_2),
.dout(DOUT)
);
endmodule
architecture/xilinx_ug901_synthesis_examples/bytewrite_ram_1b.v 0 → 100644
// Single-Port BRAM with Byte-wide Write Enable
// Read-First mode
// Single-process description
// Compact description of the write with a generate-for
// statement
// Column width and number of columns easily configurable
//
// bytewrite_ram_1b.v
//
module bytewrite_ram_1b (clk, we, addr, di, do);
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
parameter SIZE = 32;
parameter ADDR_WIDTH = 10;
parameter COL_WIDTH = 8;
parameter NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] di;
output reg [NB_COL*COL_WIDTH-1:0] do;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
always @(posedge clk)
begin
do <= RAM[addr];
end
generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
if (we[i])
RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
end
endgenerate
endmodule
architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_nc.v 0 → 100644
//
// True-Dual-Port BRAM with Byte-wide Write Enable
// No-Change mode
//
// bytewrite_tdp_ram_nc.v
//
// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended
module bytewrite_tdp_ram_nc
#(
//---------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//---------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkA) begin
if(enaA) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkA) begin
if(enaA) begin
if (~|weA)
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
generate
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkB) begin
if(enaB) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkB) begin
if(enaB) begin
if (~|weB)
doutB <= ram_block[addrB];
end
end
endmodule // bytewrite_tdp_ram_nc
architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_readfirst2.v 0 → 100644
// ByteWide Write Enable, - Alternate READ_FIRST mode template - Vivado recomended
// bytewrite_tdp_ram_readfirst2.v
module bytewrite_tdp_ram_readfirst2
#(
//-------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//-------------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkA) begin
if(enaA) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkA) begin
if(enaA) begin
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
generate
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkB) begin
if(enaB) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkB) begin
if(enaB) begin
doutB <= ram_block[addrB];
end
end
endmodule // bytewrite_tdp_ram_readfirst2
architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_rf.v 0 → 100644
// True-Dual-Port BRAM with Byte-wide Write Enable
// Read-First mode
// bytewrite_tdp_ram_rf.v
//
module bytewrite_tdp_ram_rf
#(
//--------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
integer i;
// Port-A Operation
always @ (posedge clkA) begin
if(enaA) begin
for(i=0;i<NUM_COL;i=i+1) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
end
end
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
always @ (posedge clkB) begin
if(enaB) begin
for(i=0;i<NUM_COL;i=i+1) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
end
end
doutB <= ram_block[addrB];
end
end
endmodule // bytewrite_tdp_ram_rf
architecture/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_wf.v 0 → 100644
// True-Dual-Port BRAM with Byte-wide Write Enable
// Write-First mode
// File: HDL_Coding_Techniques/rams/bytewrite_tdp_ram_wf.v
//
// ByteWide Write Enable, - WRITE_FIRST mode template - Vivado recomended
module bytewrite_tdp_ram_wf
#(
//----------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkA) begin
if(enaA) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
doutA[i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH] ;
end else begin
doutA[i*COL_WIDTH +: COL_WIDTH] <= ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] ;
end
end
end
end
endgenerate
// Port-B Operation:
generate
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkB) begin
if(enaB) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
doutB[i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH] ;
end else begin
doutB[i*COL_WIDTH +: COL_WIDTH] <= ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] ;
end
end
end
end
endgenerate
endmodule // bytewrite_tdp_ram_wf
architecture/xilinx_ug901_synthesis_examples/cmacc.v 0 → 100644
// Complex Multiplier with accumulation (pr+i.pi) = (ar+i.ai)*(br+i.bi)
// File: cmacc.v
// The RTL below describes a complex multiplier with accumulation
// which can be packed into 3 DSP blocks (Ultrascale architecture)
//Default parameters were changed because of slow test
//module cmacc # (parameter AWIDTH = 16, BWIDTH = 18, SIZEOUT = 40)
module cmacc # (parameter AWIDTH = 4, BWIDTH = 5, SIZEOUT = 9)
(
input clk,
input sload,
input signed [AWIDTH-1:0] ar,
input signed [AWIDTH-1:0] ai,
input signed [BWIDTH-1:0] br,
input signed [BWIDTH-1:0] bi,
output signed [SIZEOUT-1:0] pr,
output signed [SIZEOUT-1:0] pi);
reg signed [AWIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd;
reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd;
reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
reg signed [AWIDTH:0] addcommon;
reg signed [BWIDTH:0] addr, addi;
reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi;
reg signed [SIZEOUT-1:0] pr_int, pi_int, old_result_real, old_result_im;
reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2;
reg sload_reg;
`ifdef SIM
initial
begin
ai_d = 0;
ai_dd = 0;
ai_ddd = 0;
ai_dddd = 0;
ar_d = 0;
ar_dd = 0;
ar_ddd = 0;
ar_dddd = 0;
bi_d = 0;
bi_dd = 0;
bi_ddd = 0;
br_d = 0;
br_dd = 0;
br_ddd = 0;
end
`endif
always @(posedge clk)
begin
ar_d <= ar;
ar_dd <= ar_d;
ai_d <= ai;
ai_dd <= ai_d;
br_d <= br;
br_dd <= br_d;
br_ddd <= br_dd;
bi_d <= bi;
bi_dd <= bi_d;
bi_ddd <= bi_dd;
sload_reg <= sload;
end
// Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
//
always @(posedge clk)
begin
addcommon <= ar_d - ai_d;
mult0 <= addcommon * bi_dd;
common <= mult0;
end
// Accumulation loop (combinatorial) for *Real*
//
always @(sload_reg or pr_int)
if (sload_reg)
old_result_real <= 0;
else
// 'sload' is now and opens the accumulation loop.
// The accumulator takes the next multiplier output
// in the same cycle.
old_result_real <= pr_int;
// Real product
//
always @(posedge clk)
begin
ar_ddd <= ar_dd;
ar_dddd <= ar_ddd;
addr <= br_ddd - bi_ddd;
multr <= addr * ar_dddd;
commonr1 <= common;
pr_int <= multr + commonr1 + old_result_real;
end
// Accumulation loop (combinatorial) for *Imaginary*
//
always @(sload_reg or pi_int)
if (sload_reg)
old_result_im <= 0;
else
// 'sload' is now and opens the accumulation loop.
// The accumulator takes the next multiplier output
// in the same cycle.
old_result_im <= pi_int;
// Imaginary product
//
always @(posedge clk)
begin
ai_ddd <= ai_dd;
ai_dddd <= ai_ddd;
addi <= br_ddd + bi_ddd;
multi <= addi * ai_dddd;
commonr2 <= common;
pi_int <= multi + commonr2 + old_result_im;
end
assign pr = pr_int;
assign pi = pi_int;
endmodule // cmacc
architecture/xilinx_ug901_synthesis_examples/cmult.v 0 → 100644
//
// Complex Multiplier (pr+i.pi) = (ar+i.ai)*(br+i.bi)
// file: cmult.v
//module cmult # (parameter AWIDTH = 16, BWIDTH = 18)
module cmult # (parameter AWIDTH = 8, BWIDTH = 9)
(
input clk,
input signed [AWIDTH-1:0] ar, ai,
input signed [BWIDTH-1:0] br, bi,
output signed [AWIDTH+BWIDTH:0] pr, pi
);
reg signed [AWIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd ;
reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd ;
reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd ;
reg signed [AWIDTH:0] addcommon ;
reg signed [BWIDTH:0] addr, addi ;
reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi, pr_int, pi_int ;
reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2 ;
always @(posedge clk)
begin
ar_d <= ar;
ar_dd <= ar_d;
ai_d <= ai;
ai_dd <= ai_d;
br_d <= br;
br_dd <= br_d;
br_ddd <= br_dd;
bi_d <= bi;
bi_dd <= bi_d;
bi_ddd <= bi_dd;
end
// Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
//
always @(posedge clk)
begin
addcommon <= ar_d - ai_d;
mult0 <= addcommon * bi_dd;
common <= mult0;
end
// Real product
//
always @(posedge clk)
begin
ar_ddd <= ar_dd;
ar_dddd <= ar_ddd;
addr <= br_ddd - bi_ddd;
multr <= addr * ar_dddd;
commonr1 <= common;
pr_int <= multr + commonr1;
end
// Imaginary product
//
always @(posedge clk)
begin
ai_ddd <= ai_dd;
ai_dddd <= ai_ddd;
addi <= br_ddd + bi_ddd;
multi <= addi * ai_dddd;
commonr2 <= common;
pi_int <= multi + commonr2;
end
assign pr = pr_int;
assign pi = pi_int;
endmodule // cmult
architecture/xilinx_ug901_synthesis_examples/dynamic_shift_registers_1.v 0 → 100644
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
input [SELWIDTH-1:0] SEL;
output DO;
localparam DATAWIDTH = 2**SELWIDTH;
reg [DATAWIDTH-1:0] data;
assign DO = data[SEL];
always @(posedge CLK)
begin
if (CE == 1'b1)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
architecture/xilinx_ug901_synthesis_examples/dynpreaddmultadd.v 0 → 100644
// Pre-add/subtract select with Dynamic control
// dynpreaddmultadd.v
//Default parameters were changed because of slow test.
//module dynpreaddmultadd # (parameter SIZEIN = 16)
module dynpreaddmultadd # (parameter SIZEIN = 8)
(
input clk, ce, rst, subadd,
input signed [SIZEIN-1:0] a, b, c, d,
output signed [2*SIZEIN:0] dynpreaddmultadd_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
reg signed [SIZEIN:0] add_reg;
reg signed [2*SIZEIN:0] d_reg, m_reg, p_reg;
always @(posedge clk)
begin
if (rst)
begin
a_reg <= 0;
b_reg <= 0;
c_reg <= 0;
d_reg <= 0;
add_reg <= 0;
m_reg <= 0;
p_reg <= 0;
end
else if (ce)
begin
a_reg <= a;
b_reg <= b;
c_reg <= c;
d_reg <= d;
if (subadd)
add_reg <= a_reg - b_reg;
else
add_reg <= a_reg + b_reg;
m_reg <= add_reg * c_reg;
p_reg <= m_reg + d_reg;
end
end
// Output accumulation result
assign dynpreaddmultadd_out = p_reg;
endmodule // dynpreaddmultadd
architecture/xilinx_ug901_synthesis_examples/fsm_1.v 0 → 100644
// State Machine with single sequential block
//fsm_1.v
module fsm_1(clk,reset,flag,sm_out);
input clk,reset,flag;
output reg sm_out;
parameter s1 = 3'b000;
parameter s2 = 3'b001;
parameter s3 = 3'b010;
parameter s4 = 3'b011;
parameter s5 = 3'b111;
reg [2:0] state;
always@(posedge clk)
begin
if(reset)
begin
state <= s1;
sm_out <= 1'b1;
end
else
begin
case(state)
s1: if(flag)
begin
state <= s2;
sm_out <= 1'b1;
end
else
begin
state <= s3;
sm_out <= 1'b0;
end
s2: begin state <= s4; sm_out <= 1'b0; end
s3: begin state <= s4; sm_out <= 1'b0; end
s4: begin state <= s5; sm_out <= 1'b1; end
s5: begin state <= s1; sm_out <= 1'b1; end
endcase
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/latches.v 0 → 100644
// Latch with Positive Gate and Asynchronous Reset
// File: latches.v
module latches (
input G,
input D,
input CLR,
output reg Q
);
always @ *
begin
if(CLR)
Q = 0;
else if(G)
Q = D;
end
endmodule
architecture/xilinx_ug901_synthesis_examples/macc.v 0 → 100644
// Signed 40-bit streaming accumulator with 16-bit inputs
// File: macc.v
//
module macc # (
parameter SIZEIN = 16, SIZEOUT = 40
)
(
input clk, ce, sload,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg sload_reg;
reg signed [2*SIZEIN:0] mult_reg;
reg signed [SIZEOUT-1:0] adder_out, old_result;
always @(adder_out or sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
// 'sload' is now active (=low) and opens the accumulation loop.
// The accumulator takes the next multiplier output in
// the same cycle.
old_result <= adder_out;
end
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
mult_reg <= a_reg * b_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + mult_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule // macc
architecture/xilinx_ug901_synthesis_examples/mult_unsigned.v 0 → 100644
// Unsigned 16x24-bit Multiplier
// 1 latency stage on operands
// 3 latency stage after the multiplication
// File: multipliers2.v
//
module mult_unsigned (clk, A, B, RES);
//Default parameters were changed because of slow test
//parameter WIDTHA = 16;
//parameter WIDTHB = 24;
parameter WIDTHA = 8;
parameter WIDTHB = 12;
input clk;
input [WIDTHA-1:0] A;
input [WIDTHB-1:0] B;
output [WIDTHA+WIDTHB-1:0] RES;
reg [WIDTHA-1:0] rA;
reg [WIDTHB-1:0] rB;
reg [WIDTHA+WIDTHB-1:0] M [3:0];
integer i;
always @(posedge clk)
begin
rA <= A;
rB <= B;
M[0] <= rA * rB;
for (i = 0; i < 3; i = i+1)
M[i+1] <= M[i];
end
assign RES = M[3];
endmodule
architecture/xilinx_ug901_synthesis_examples/presubmult.v 0 → 100644
//
// Pre-adder support in subtract mode for DSP block
// File: presubmult.v
module presubmult # (//Default parameters were changed because of slow test
// parameter SIZEIN = 16
parameter SIZEIN = 8
)
(
input clk, ce, rst,
input signed [SIZEIN-1:0] a, b, c,
output signed [2*SIZEIN:0] presubmult_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
reg signed [SIZEIN:0] add_reg;
reg signed [2*SIZEIN:0] m_reg, p_reg;
always @(posedge clk)
if (rst)
begin
a_reg <= 0;
b_reg <= 0;
c_reg <= 0;
add_reg <= 0;
m_reg <= 0;
p_reg <= 0;
end
else if (ce)
begin
a_reg <= a;
b_reg <= b;
c_reg <= c;
add_reg <= a - b;
m_reg <= add_reg * c_reg;
p_reg <= m_reg;
end
// Output accumulation result
assign presubmult_out = p_reg;
endmodule // presubmult
architecture/xilinx_ug901_synthesis_examples/ram_simple_dual_one_clock.v 0 → 100644
// Simple Dual-Port Block RAM with One Clock
// File: simple_dual_one_clock.v
module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);
input clk,ena,enb,wea;
input [9:0] addra,addrb;
input [15:0] dia;
output [15:0] dob;
reg [15:0] ram [1023:0];
reg [15:0] doa,dob;
always @(posedge clk) begin
if (ena) begin
if (wea)
ram[addra] <= dia;
end
end
always @(posedge clk) begin
if (enb)
dob <= ram[addrb];
end
endmodule
\ No newline at end of file
architecture/xilinx_ug901_synthesis_examples/ram_simple_dual_two_clocks.v 0 → 100644
// Simple Dual-Port Block RAM with Two Clocks
// File: simple_dual_two_clocks.v
module simple_dual_two_clocks (clka,clkb,ena,enb,wea,addra,addrb,dia,dob);
input clka,clkb,ena,enb,wea;
input [9:0] addra,addrb;
input [15:0] dia;
output [15:0] dob;
reg [15:0] ram [1023:0];
reg [15:0] dob;
always @(posedge clka)
begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
end
end
always @(posedge clkb)
begin
if (enb)
begin
dob <= ram[addrb];
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_dist.v 0 → 100644
// Dual-Port RAM with Asynchronous Read (Distributed RAM)
// File: rams_dist.v
module rams_dist (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [5:0] a;
input [5:0] dpra;
input [15:0] di;
output [15:0] spo;
output [15:0] dpo;
reg [15:0] ram [63:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_init_file.data 0 → 100644
00001110110000011001111011000110
00101011001011010101001000100011
01110100010100011000011100001111
01000001010000100101001110010100
00001001101001111111101000101011
00101101001011111110101010100111
11101111000100111000111101101101
10001111010010011001000011101111
00000001100011100011110010011111
11011111001110101011111001001010
11100111010100111110110011001010
11000100001001101100111100101001
10001011100101011111111111100001
11110101110110010000010110111010
01001011000000111001010110101110
11100001111111001010111010011110
01101111011010010100001101110001
01010100011011111000011000100100
11110000111101101111001100001011
10101101001111010100100100011100
01011100001010111111101110101110
01011101000100100111010010110101
11110111000100000101011101101101
11100111110001111010101100001101
01110100000011101111111000011111
00010011110101111000111001011101
01101110001111100011010101101111
10111100000000010011101011011011
11000001001101001101111100010000
00011111110010110110011111010101
01100100100000011100100101110000
10001000000100111011001010001111
11001000100011101001010001100001
10000000100111010011100111100011
11011111010010100010101010000111
10000000110111101000111110111011
10110011010111101111000110011001
00010111100001001010110111011100
10011100101110101111011010110011
01010011101101010001110110011010
01111011011100010101000101000001
10001000000110010110111001101010
11101000001101010000111001010110
11100011111100000111110101110101
01001010000000001111111101101111
00100011000011001000000010001111
10011000111010110001001011100100
11111111111011110101000101000111
11000011000101000011100110100000
01101101001011111010100011101001
10000111101100101001110011010111
11010110100100101110110010100100
01001111111001101101011111001011
11011001001101110110000100110111
10110110110111100101110011100110
10011100111001000010111111010110
00000000001011011111001010110010
10100110011010000010001000011011
11001010111111001001110001110101
00100001100010000111000101001000
00111100101111110001101101111010
11000010001010000000010100100001
11000001000110001101000101001110
10010011010100010001100100100111
architecture/xilinx_ug901_synthesis_examples/rams_init_file.v 0 → 100644
// Initializing Block RAM from external data file
// Binary data
// File: rams_init_file.v
module rams_init_file (clk, we, addr, din, dout);
input clk;
input we;
input [5:0] addr;
input [31:0] din;
output [31:0] dout;
reg [31:0] ram [0:63];
reg [31:0] dout;
initial begin
$readmemb("../rams_init_file.data",ram);
end
always @(posedge clk)
begin
if (we)
ram[addr] <= din;
dout <= ram[addr];
end endmodule
architecture/xilinx_ug901_synthesis_examples/rams_pipeline.v 0 → 100644
// Block RAM with Optional Output Registers
// File: rams_pipeline
module rams_pipeline (clk1, clk2, we, en1, en2, addr1, addr2, di, res1, res2);
input clk1;
input clk2;
input we, en1, en2;
input [9:0] addr1;
input [9:0] addr2;
input [15:0] di;
output [15:0] res1;
output [15:0] res2;
reg [15:0] res1;
reg [15:0] res2;
reg [15:0] RAM [1023:0];
reg [15:0] do1;
reg [15:0] do2;
always @(posedge clk1)
begin
if (we == 1'b1)
RAM[addr1] <= di;
do1 <= RAM[addr1];
end
always @(posedge clk2)
begin
do2 <= RAM[addr2];
end
always @(posedge clk1)
begin
if (en1 == 1'b1)
res1 <= do1;
end
always @(posedge clk2)
begin
if (en2 == 1'b1)
res2 <= do2;
end
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_sp_nc.v 0 → 100644
// Single-Port Block RAM No-Change Mode
// File: rams_sp_nc.v
module rams_sp_nc (clk, we, en, addr, di, dout);
input clk;
input we;
input en;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] RAM [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr] <= di;
else
dout <= RAM[addr];
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_sp_rf.v 0 → 100644
// Single-Port Block RAM Read-First Mode
// rams_sp_rf.v
module rams_sp_rf (clk, en, we, addr, di, dout);
input clk;
input we;
input en;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] RAM [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr]<=di;
dout <= RAM[addr];
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_sp_rf_rst.v 0 → 100644
// Block RAM with Resettable Data Output
// File: rams_sp_rf_rst.v
module rams_sp_rf_rst (clk, en, we, rst, addr, di, dout);
input clk;
input en;
input we;
input rst;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] ram [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en) //optional enable
begin
if (we) //write enable
ram[addr] <= di;
if (rst) //optional reset
dout <= 0;
else
dout <= ram[addr];
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_sp_rom.v 0 → 100644
// Initializing Block RAM (Single-Port Block RAM)
// File: rams_sp_rom
module rams_sp_rom (clk, we, addr, di, dout);
input clk;
input we;
input [5:0] addr;
input [19:0] di;
output [19:0] dout;
reg [19:0] ram [63:0];
reg [19:0] dout;
initial
begin
ram[63] = 20'h0200A; ram[62] = 20'h00300; ram[61] = 20'h08101;
ram[60] = 20'h04000; ram[59] = 20'h08601; ram[58] = 20'h0233A;
ram[57] = 20'h00300; ram[56] = 20'h08602; ram[55] = 20'h02310;
ram[54] = 20'h0203B; ram[53] = 20'h08300; ram[52] = 20'h04002;
ram[51] = 20'h08201; ram[50] = 20'h00500; ram[49] = 20'h04001;
ram[48] = 20'h02500; ram[47] = 20'h00340; ram[46] = 20'h00241;
ram[45] = 20'h04002; ram[44] = 20'h08300; ram[43] = 20'h08201;
ram[42] = 20'h00500; ram[41] = 20'h08101; ram[40] = 20'h00602;
ram[39] = 20'h04003; ram[38] = 20'h0241E; ram[37] = 20'h00301;
ram[36] = 20'h00102; ram[35] = 20'h02122; ram[34] = 20'h02021;
ram[33] = 20'h00301; ram[32] = 20'h00102; ram[31] = 20'h02222;
ram[30] = 20'h04001; ram[29] = 20'h00342; ram[28] = 20'h0232B;
ram[27] = 20'h00900; ram[26] = 20'h00302; ram[25] = 20'h00102;
ram[24] = 20'h04002; ram[23] = 20'h00900; ram[22] = 20'h08201;
ram[21] = 20'h02023; ram[20] = 20'h00303; ram[19] = 20'h02433;
ram[18] = 20'h00301; ram[17] = 20'h04004; ram[16] = 20'h00301;
ram[15] = 20'h00102; ram[14] = 20'h02137; ram[13] = 20'h02036;
ram[12] = 20'h00301; ram[11] = 20'h00102; ram[10] = 20'h02237;
ram[9] = 20'h04004; ram[8] = 20'h00304; ram[7] = 20'h04040;
ram[6] = 20'h02500; ram[5] = 20'h02500; ram[4] = 20'h02500;
ram[3] = 20'h0030D; ram[2] = 20'h02341; ram[1] = 20'h08201;
ram[0] = 20'h0400D;
end
always @(posedge clk)
begin
if (we)
ram[addr] <= di;
dout <= ram[addr];
end
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_sp_rom_1.v 0 → 100644
// ROMs Using Block RAM Resources.
// File: rams_sp_rom_1.v
//
module rams_sp_rom_1 (clk, en, addr, dout);
input clk;
input en;
input [5:0] addr;
output [19:0] dout;
(*rom_style = "block" *) reg [19:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
6'b000000: data <= 20'h0200A; 6'b100000: data <= 20'h02222;
6'b000001: data <= 20'h00300; 6'b100001: data <= 20'h04001;
6'b000010: data <= 20'h08101; 6'b100010: data <= 20'h00342;
6'b000011: data <= 20'h04000; 6'b100011: data <= 20'h0232B;
6'b000100: data <= 20'h08601; 6'b100100: data <= 20'h00900;
6'b000101: data <= 20'h0233A; 6'b100101: data <= 20'h00302;
6'b000110: data <= 20'h00300; 6'b100110: data <= 20'h00102;
6'b000111: data <= 20'h08602; 6'b100111: data <= 20'h04002;
6'b001000: data <= 20'h02310; 6'b101000: data <= 20'h00900;
6'b001001: data <= 20'h0203B; 6'b101001: data <= 20'h08201;
6'b001010: data <= 20'h08300; 6'b101010: data <= 20'h02023;
6'b001011: data <= 20'h04002; 6'b101011: data <= 20'h00303;
6'b001100: data <= 20'h08201; 6'b101100: data <= 20'h02433;
6'b001101: data <= 20'h00500; 6'b101101: data <= 20'h00301;
6'b001110: data <= 20'h04001; 6'b101110: data <= 20'h04004;
6'b001111: data <= 20'h02500; 6'b101111: data <= 20'h00301;
6'b010000: data <= 20'h00340; 6'b110000: data <= 20'h00102;
6'b010001: data <= 20'h00241; 6'b110001: data <= 20'h02137;
6'b010010: data <= 20'h04002; 6'b110010: data <= 20'h02036;
6'b010011: data <= 20'h08300; 6'b110011: data <= 20'h00301;
6'b010100: data <= 20'h08201; 6'b110100: data <= 20'h00102;
6'b010101: data <= 20'h00500; 6'b110101: data <= 20'h02237;
6'b010110: data <= 20'h08101; 6'b110110: data <= 20'h04004;
6'b010111: data <= 20'h00602; 6'b110111: data <= 20'h00304;
6'b011000: data <= 20'h04003; 6'b111000: data <= 20'h04040;
6'b011001: data <= 20'h0241E; 6'b111001: data <= 20'h02500;
6'b011010: data <= 20'h00301; 6'b111010: data <= 20'h02500;
6'b011011: data <= 20'h00102; 6'b111011: data <= 20'h02500;
6'b011100: data <= 20'h02122; 6'b111100: data <= 20'h0030D;
6'b011101: data <= 20'h02021; 6'b111101: data <= 20'h02341;
6'b011110: data <= 20'h00301; 6'b111110: data <= 20'h08201;
6'b011111: data <= 20'h00102; 6'b111111: data <= 20'h0400D;
endcase
end
assign dout = data;
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_sp_wf.v 0 → 100644
// Single-Port Block RAM Write-First Mode (recommended template)
// File: rams_sp_wf.v
module rams_sp_wf (clk, we, en, addr, di, dout);
input clk;
input we;
input en;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] RAM [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
begin
RAM[addr] <= di;
dout <= di;
end
else
dout <= RAM[addr];
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/rams_tdp_rf_rf.v 0 → 100644
// Dual-Port Block RAM with Two Write Ports
// File: rams_tdp_rf_rf.v
module rams_tdp_rf_rf (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
input clka,clkb,ena,enb,wea,web;
input [9:0] addra,addrb;
input [15:0] dia,dib;
output [15:0] doa,dob;
reg [15:0] ram [1023:0];
reg [15:0] doa,dob;
always @(posedge clka)
begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb)
begin
if (enb)
begin
if (web)
ram[addrb] <= dib;
dob <= ram[addrb];
end
end
endmodule
architecture/xilinx_ug901_synthesis_examples/registers_1.v 0 → 100644
// 8-bit Register with
// Rising-edge Clock
// Active-high Synchronous Clear
// Active-high Clock Enable
// File: registers_1.v
module registers_1(d_in,ce,clk,clr,dout);
input [7:0] d_in;
input ce;
input clk;
input clr;
output [7:0] dout;
reg [7:0] d_reg;
always @ (posedge clk)
begin
if(clr)
d_reg <= 8'b0;
else if(ce)
d_reg <= d_in;
end
assign dout = d_reg;
endmodule
architecture/xilinx_ug901_synthesis_examples/sfir_shifter.v 0 → 100644
//sfir_shifter.v
(* dont_touch = "yes" *)
module sfir_shifter #(parameter dsize = 16, nbtap = 4)
(input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout);
(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
integer i;
always @(posedge clk)
begin
tmp[0] <= datain;
for (i=0; i<=2*nbtap-2; i=i+1)
tmp[i+1] <= tmp[i];
end
assign dataout = tmp[2*nbtap-1];
endmodule
// sfir_shifter
architecture/xilinx_ug901_synthesis_examples/shift_registers_0.v 0 → 100644
// 8-bit Shift Register
// Rising edge clock
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk)
begin
if (clken)
shreg = {shreg[WIDTH-2:0], SI};
end
assign SO = shreg[WIDTH-1];
endmodule
architecture/xilinx_ug901_synthesis_examples/shift_registers_1.v 0 → 100644
// 32-bit Shift Register
// Rising edge clock
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
integer i;
always @(posedge clk)
begin
if (clken)
begin
for (i = 0; i < WIDTH-1; i = i+1)
shreg[i+1] <= shreg[i];
shreg[0] <= SI;
end
end
assign SO = shreg[WIDTH-1];
endmodule
architecture/xilinx_ug901_synthesis_examples/squarediffmacc.v 0 → 100644
// This module performs subtraction of two inputs, squaring on the diff
// and then accumulation
// This can be implemented in 1 DSP Block (Ultrascale architecture)
// File : squarediffmacc.v
module squarediffmacc # (
//Default parameters were changed because of slow test
//parameter SIZEIN = 16,
//SIZEOUT = 40
parameter SIZEIN = 8,
SIZEOUT = 20
)
(
input clk,
input ce,
input sload,
input signed [SIZEIN-1:0] a,
input signed [SIZEIN-1:0] b,
output signed [SIZEOUT+1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg signed [SIZEIN:0] diff_reg;
reg sload_reg;
reg signed [2*SIZEIN+1:0] m_reg;
reg signed [SIZEOUT-1:0] adder_out, old_result;
always @(sload_reg or adder_out)
if (sload_reg)
old_result <= 0;
else
// 'sload' is now and opens the accumulation loop.
// The accumulator takes the next multiplier output
// in the same cycle.
old_result <= adder_out;
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
diff_reg <= a_reg - b_reg;
m_reg <= diff_reg * diff_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + m_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule // squarediffmacc
architecture/xilinx_ug901_synthesis_examples/squarediffmult.v 0 → 100644
// Squarer support for DSP block (DSP48E2) with
// pre-adder configured
// as subtractor
// File: squarediffmult.v
module squarediffmult # (parameter SIZEIN = 16)
(
input clk, ce, rst,
input signed [SIZEIN-1:0] a, b,
output signed [2*SIZEIN+1:0] square_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg signed [SIZEIN:0] diff_reg;
reg signed [2*SIZEIN+1:0] m_reg, p_reg;
always @(posedge clk)
begin
if (rst)
begin
a_reg <= 0;
b_reg <= 0;
diff_reg <= 0;
m_reg <= 0;
p_reg <= 0;
end
else
if (ce)
begin
a_reg <= a;
b_reg <= b;
diff_reg <= a_reg - b_reg;
m_reg <= diff_reg * diff_reg;
p_reg <= m_reg;
end
end
// Output result
assign square_out = p_reg;
endmodule // squarediffmult
architecture/xilinx_ug901_synthesis_examples/top_mux.v 0 → 100644
// Multiplexer using case statement
module mux4 (sel, a, b, c, d, outmux);
input [1:0] sel;
input [1:0] a, b, c, d;
output [1:0] outmux;
reg [1:0] outmux;
always @ *
begin
case(sel)
2'b00 : outmux = a;
2'b01 : outmux = b;
2'b10 : outmux = c;
2'b11 : outmux = d;
endcase
end
endmodule
architecture/xilinx_ug901_synthesis_examples/tristates_1.v 0 → 100644
// Tristate Description Using Combinatorial Always Block
// File: tristates_1.v
//
module tristates_1 (T, I, O);
input T, I;
output O;
reg O;
always @(T or I)
begin
if (~T)
O = I;
else
O = 1'bZ;
end
endmodule
architecture/xilinx_ug901_synthesis_examples/tristates_2.v 0 → 100644
// Tristate Description Using Concurrent Assignment
// File: tristates_2.v
//
module tristates_2 (T, I, O);
input T, I;
output O;
assign O = (~T) ? I: 1'bZ;
endmodule
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys 0 → 100644
read_verilog ../asym_ram_sdp_read_wider.v
hierarchy -top asym_ram_sdp_read_wider
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_sdp_read_wider
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 4 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys 0 → 100644
read_verilog ../asym_ram_sdp_write_wider.v
hierarchy -top asym_ram_sdp_write_wider
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_sdp_write_wider
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 9 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT3
select -assert-count 8 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_read_first.ys 0 → 100644
read_verilog ../asym_ram_tdp_read_first.v
hierarchy -top asym_ram_tdp_read_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_tdp_read_first
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:LUT2
select -assert-none t:$mem t:LUT2 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys 0 → 100644
read_verilog ../asym_ram_tdp_write_first.v
hierarchy -top asym_ram_tdp_write_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_tdp_write_first
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 200 t:FDRE
select -assert-count 10 t:LUT2
select -assert-count 44 t:LUT3
select -assert-count 81 t:LUT4
select -assert-count 104 t:LUT5
select -assert-count 560 t:LUT6
select -assert-count 261 t:MUXF7
select -assert-count 127 t:MUXF8
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_black_box_1.ys 0 → 100644
read_verilog ../black_box_1.v
hierarchy -top black_box_1
proc
tribuf
flatten
synth
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd black_box_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 black box.
#stat
#select -assert-count 0 t:LUT1
#select -assert-count 1 t:$_TBUF_
#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_ram_1b.ys 0 → 100644
read_verilog ../bytewrite_ram_1b.v
hierarchy -top bytewrite_ram_1b
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_ram_1b
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 32 t:LUT2
select -assert-count 32 t:RAM32X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:RAM32X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_nc.ys 0 → 100644
read_verilog ../bytewrite_tdp_ram_nc.v
hierarchy -top bytewrite_tdp_ram_nc
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_nc
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 8 t:LUT2
select -assert-count 64 t:LUT3
select -assert-count 2 t:LUT5
select -assert-none t:LUT2 t:LUT3 t:LUT5 t:$mem %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys 0 → 100644
read_verilog ../bytewrite_tdp_ram_readfirst2.v
hierarchy -top bytewrite_tdp_ram_readfirst2
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_readfirst2
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 8 t:LUT2
select -assert-count 64 t:LUT3
select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_rf.ys 0 → 100644
read_verilog ../bytewrite_tdp_ram_rf.v
hierarchy -top bytewrite_tdp_ram_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_rf
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 8 t:LUT2
select -assert-count 64 t:LUT3
select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_wf.ys 0 → 100644
read_verilog ../bytewrite_tdp_ram_wf.v
hierarchy -top bytewrite_tdp_ram_wf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_wf
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:BUFG
select -assert-count 64 t:FDRE
select -assert-count 8 t:LUT2
select -assert-count 128 t:LUT3
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:$mem %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmacc.ys 0 → 100644
read_verilog ../cmacc.v
hierarchy -top cmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd cmacc
#Vivado synthesizes 5 DSP48E1, 32 FDRE, 18 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 65 t:FDRE
select -assert-count 3 t:DSP48E1
select -assert-count 18 t:LUT2
select -assert-count 34 t:LUT3
select -assert-count 25 t:MUXCY
select -assert-count 29 t:XORCY
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys 0 → 100644
read_verilog ../cmult.v
hierarchy -top cmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd cmult
#Vivado synthesizes 3 DSP48E1, 68 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 86 t:FDRE
select -assert-count 3 t:DSP48E1
select -assert-count 34 t:LUT2
select -assert-count 17 t:MUXCY
select -assert-count 19 t:XORCY
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynamic_shift_registers_1.ys 0 → 100644
read_verilog ../dynamic_shift_registers_1.v
hierarchy -top dynamic_shift_register_1
proc
flatten
#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dynamic_shift_register_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 3 SRLC32E.
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys 0 → 100644
read_verilog ../dynpreaddmultadd.v
hierarchy -top dynpreaddmultadd
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd dynpreaddmultadd
#Vivado synthesizes 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 24 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-count 8 t:LUT1
select -assert-count 17 t:LUT2
select -assert-count 25 t:LUT4
select -assert-count 16 t:MUXCY
select -assert-count 18 t:XORCY
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT1 t:LUT2 t:LUT4 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_fsm_1.ys 0 → 100644
read_verilog ../fsm_1.v
hierarchy -top fsm_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE.
stat
select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE
select -assert-count 2 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_latches.ys 0 → 100644
read_verilog ../latches.v
proc
hierarchy -top latches
flatten
synth_xilinx
#Vivado synthesizes 1 BUFG, 8 LDCE.
select -assert-count 2 t:LUT2
select -assert-count 1 t:LDCE
#select -assert-none t:LUT2 t:LDCE %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_macc.ys 0 → 100644
read_verilog ../macc.v
hierarchy -top macc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc
#Vivado synthesizes 1 DSP48E1, 1 FDRE. (When SIZEIN = 12, SIZEOUT = 30)
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_mult_unsigned.ys 0 → 100644
read_verilog ../mult_unsigned.v
hierarchy -top mult_unsigned
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd mult_unsigned
#Vivado synthesizes 1 DSP48E1, 40 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 40 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_presubmult.ys 0 → 100644
read_verilog ../presubmult.v
hierarchy -top presubmult
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd presubmult
#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_one_clock.ys 0 → 100644
read_verilog ../ram_simple_dual_one_clock.v
hierarchy -top simple_dual_one_clock
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_one_clock
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_two_clocks.ys 0 → 100644
read_verilog ../ram_simple_dual_two_clocks.v
hierarchy -top simple_dual_two_clocks
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_two_clocks
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_dist.ys 0 → 100644
read_verilog ../rams_dist.v
hierarchy -top rams_dist
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_dist
stat
#Vivado synthesizes 32 RAM64X1D.
select -assert-count 1 t:BUFG
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:RAM64X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys 0 → 100644
read_verilog ../rams_init_file.v
hierarchy -top rams_init_file
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_init_file
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys 0 → 100644
read_verilog ../rams_pipeline.v
hierarchy -top rams_pipeline
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_pipeline
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 2 t:RAMB18E1
select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_nc.ys 0 → 100644
read_verilog ../rams_sp_nc.v
hierarchy -top rams_sp_nc
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_nc
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 2 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf.ys 0 → 100644
read_verilog ../rams_sp_rf.v
hierarchy -top rams_sp_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys 0 → 100644
read_verilog ../rams_sp_rf_rst.v
hierarchy -top rams_sp_rf_rst
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf_rst
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 5 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 13 t:LUT4
select -assert-count 23 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys 0 → 100644
read_verilog ../rams_sp_rom.v
hierarchy -top rams_sp_rom
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 20 t:RAM64X1D
select -assert-count 20 t:FDRE
select -assert-none t:BUFG t:RAM64X1D t:FDRE %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom_1.ys 0 → 100644
read_verilog ../rams_sp_rom_1.v
hierarchy -top rams_sp_rom_1
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom_1
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 14 t:LUT6
select -assert-count 14 t:FDRE
select -assert-none t:BUFG t:LUT6 t:FDRE %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys 0 → 100644
read_verilog ../rams_sp_wf.v
hierarchy -top rams_sp_wf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_wf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 44 t:LUT5
select -assert-count 38 t:LUT6
select -assert-count 10 t:MUXF7
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_tdp_rf_rf.ys 0 → 100644
read_verilog ../rams_tdp_rf_rf.v
hierarchy -top rams_tdp_rf_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_tdp_rf_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:LUT2
select -assert-none t:$mem t:LUT2 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys 0 → 100644
read_verilog ../registers_1.v
hierarchy -top registers_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 8 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 9 t:LUT2
select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_sfir_shifter.ys 0 → 100644
read_verilog ../sfir_shifter.v
hierarchy -top sfir_shifter
proc
flatten
#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd sfir_shifter
#Vivado synthesizes 32 FDRE, 16 SRL16E.
stat
select -assert-count 1 t:BUFG
select -assert-count 16 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_0.ys 0 → 100644
read_verilog ../shift_registers_0.v
hierarchy -top shift_registers_0
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_0 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_1.ys 0 → 100644
read_verilog ../shift_registers_1.v
hierarchy -top shift_registers_1
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmacc.ys 0 → 100644
read_verilog ../squarediffmacc.v
hierarchy -top squarediffmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd squarediffmacc
#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 17 t:FDRE
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys 0 → 100644
read_verilog ../squarediffmult.v
hierarchy -top squarediffmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd squarediffmult
stat
#Vivado synthesizes 16 FDRE, 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 32 t:FDRE
select -assert-count 65 t:LUT2
select -assert-count 16 t:MUXCY
select -assert-count 17 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_top_mux.ys 0 → 100644
read_verilog ../top_mux.v
hierarchy -top mux4
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4
#Vivado synthesizes 2 LUT.
stat
select -assert-count 2 t:LUT6
select -assert-none t:LUT6 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys 0 → 100644
read_verilog ../tristates_1.v
hierarchy -top tristates_1
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys 0 → 100644
read_verilog ../tristates_2.v
hierarchy -top tristates_2
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_2 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys 0 → 100644
read_verilog ../xilinx_ultraram_single_port_no_change.v
hierarchy -top xilinx_ultraram_single_port_no_change
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_no_change
stat
#Vivado synthesizes 1 RAMB36E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 9 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys 0 → 100644
read_verilog ../xilinx_ultraram_single_port_read_first.v
hierarchy -top xilinx_ultraram_single_port_read_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_read_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 8 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys 0 → 100644
read_verilog ../xilinx_ultraram_single_port_write_first.v
hierarchy -top xilinx_ultraram_single_port_write_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_write_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 44 t:FDRE
select -assert-count 8 t:LUT5
select -assert-count 8 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_no_change.v 0 → 100644
// Xilinx UltraRAM Single Port No Change Mode. This code implements
// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is
// when data is written, the output of RAM is unchanged. Only when write is
// inactive data corresponding to the address is presented on the output port.
//
module xilinx_ultraram_single_port_no_change #(
//Default parameters were changed because of slow test
//parameter AWIDTH = 12, // Address Width
//parameter DWIDTH = 72, // Data Width
//parameter NBPIPE = 3 // Number of pipeline Registers
parameter AWIDTH = 8, // Address Width
parameter DWIDTH = 8, // Data Width
parameter NBPIPE = 3 // Number of pipeline Registers
) (
input clk, // Clock
input rst, // Reset
input we, // Write Enable
input regce, // Output Register Enable
input mem_en, // Memory Enable
input [DWIDTH-1:0] din, // Data Input
input [AWIDTH-1:0] addr, // Address Input
output reg [DWIDTH-1:0] dout // Data Output
);
(* ram_style = "ultra" *)
reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0]; // Memory Declaration
reg [DWIDTH-1:0] memreg;
reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0]; // Pipelines for memory
reg mem_en_pipe_reg[NBPIPE:0]; // Pipelines for memory enable
integer i;
// RAM : Read has one latency, Write has one latency as well.
always @ (posedge clk)
begin
if(mem_en)
begin
if(we)
mem[addr] <= din;
else
memreg <= mem[addr];
end
end
// The enable of the RAM goes through a pipeline to produce a
// series of pipelined enable signals required to control the data
// pipeline.
always @ (posedge clk)
begin
mem_en_pipe_reg[0] <= mem_en;
for (i=0; i<NBPIPE; i=i+1)
mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end
// RAM output data goes through a pipeline.
always @ (posedge clk)
begin
if (mem_en_pipe_reg[0])
mem_pipe_reg[0] <= memreg;
end
always @ (posedge clk)
begin
for (i = 0; i < NBPIPE-1; i = i+1)
if (mem_en_pipe_reg[i+1])
mem_pipe_reg[i+1] <= mem_pipe_reg[i];
end
// Final output register gives user the option to add a reset and
// an additional enable signal just for the data ouptut
always @ (posedge clk)
begin
if (rst)
dout <= 0;
else if (mem_en_pipe_reg[NBPIPE] && regce)
dout <= mem_pipe_reg[NBPIPE-1];
end
endmodule
architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_read_first.v 0 → 100644
// Xilinx UltraRAM Single Port Read First Mode. This code implements
// a parameterizable UltraRAM block in read first mode. The behavior of this RAM is
// when data is written, the old memory contents at the write address are
// presented on the output port.
//
module xilinx_ultraram_single_port_read_first #(
//Default parameters were changed because of slow test
//parameter AWIDTH = 12, // Address Width
//parameter DWIDTH = 72, // Data Width
//parameter NBPIPE = 3 // Number of pipeline Registers
parameter AWIDTH = 8, // Address Width
parameter DWIDTH = 8, // Data Width
parameter NBPIPE = 3 // Number of pipeline Registers
) (
input clk, // Clock
input rst, // Reset
input we, // Write Enable
input regce, // Output Register Enable
input mem_en, // Memory Enable
input [DWIDTH-1:0] din, // Data Input
input [AWIDTH-1:0] addr, // Address Input
output reg [DWIDTH-1:0] dout // Data Output
);
(* ram_style = "ultra" *)
reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0]; // Memory Declaration
reg [DWIDTH-1:0] memreg;
reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0]; // Pipelines for memory
reg mem_en_pipe_reg[NBPIPE:0]; // Pipelines for memory enable
integer i;
// RAM : Both READ and WRITE have a latency of one
always @ (posedge clk)
begin
if(mem_en)
begin
if(we)
mem[addr] <= din;
memreg <= mem[addr];
end
end
// The enable of the RAM goes through a pipeline to produce a
// series of pipelined enable signals required to control the data
// pipeline.
always @ (posedge clk)
begin
mem_en_pipe_reg[0] <= mem_en;
for (i=0; i<NBPIPE; i=i+1)
mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end
// RAM output data goes through a pipeline.
always @ (posedge clk)
begin
if (mem_en_pipe_reg[0])
mem_pipe_reg[0] <= memreg;
end
always @ (posedge clk)
begin
for (i = 0; i < NBPIPE-1; i = i+1)
if (mem_en_pipe_reg[i+1])
mem_pipe_reg[i+1] <= mem_pipe_reg[i];
end
// Final output register gives user the option to add a reset and
// an additional enable signal just for the data ouptut
always @ (posedge clk)
begin
if (rst)
dout <= 0;
else if (mem_en_pipe_reg[NBPIPE] && regce)
dout <= mem_pipe_reg[NBPIPE-1];
end
endmodule
architecture/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_write_first.v 0 → 100644
// Xilinx UltraRAM Single Port Write First Mode. This code implements
// a parameterizable UltraRAM block in write first mode. The behavior of this RAM is
// when data is written, the new memory contents at the write address are
// presented on the output port.
//
module xilinx_ultraram_single_port_write_first #(
//Default parameters were changed because of slow test
//parameter AWIDTH = 12, // Address Width
//parameter DWIDTH = 72, // Data Width
//parameter NBPIPE = 3 // Number of pipeline Registers
parameter AWIDTH = 8, // Address Width
parameter DWIDTH = 8, // Data Width
parameter NBPIPE = 3 // Number of pipeline Registers
) (
input clk, // Clock
input rst, // Reset
input we, // Write Enable
input regce, // Output Register Enable
input mem_en, // Memory Enable
input [DWIDTH-1:0] din, // Data Input
input [AWIDTH-1:0] addr, // Address Input
output reg [DWIDTH-1:0] dout // Data Output
);
(* ram_style = "ultra" *)
reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0]; // Memory Declaration
reg [DWIDTH-1:0] memreg;
reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0]; // Pipelines for memory
reg mem_en_pipe_reg[NBPIPE:0]; // Pipelines for memory enable
integer i;
// RAM : Both READ and WRITE have a latency of one
always @ (posedge clk)
begin
if(mem_en)
begin
if(we)
begin
mem[addr] <= din;
memreg <= din;
end
else
memreg <= mem[addr];
end
end
// The enable of the RAM goes through a pipeline to produce a
// series of pipelined enable signals required to control the data
// pipeline.
always @ (posedge clk)
begin
mem_en_pipe_reg[0] <= mem_en;
for (i=0; i<NBPIPE; i=i+1)
mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end
// RAM output data goes through a pipeline.
always @ (posedge clk)
begin
if (mem_en_pipe_reg[0])
mem_pipe_reg[0] <= memreg;
end
always @ (posedge clk)
begin
for (i = 0; i < NBPIPE-1; i = i+1)
if (mem_en_pipe_reg[i+1])
mem_pipe_reg[i+1] <= mem_pipe_reg[i];
end
// Final output register gives user the option to add a reset and
// an additional enable signal just for the data ouptut
always @ (posedge clk)
begin
if (rst)
dout <= 0;
else if (mem_en_pipe_reg[NBPIPE] && regce)
dout <= mem_pipe_reg[NBPIPE-1];
end
endmodule
architecture_reviewed/synth_sf2/synth_sf2_fully_selected_fail.ys deleted 100644 → 0
read_verilog ../top.v
select dffe
synth_sf2
write_verilog synth.v
architecture_reviewed/synth_sf2/synth_sf2_vlog.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -vlog vlog.v # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -vlog vlog.v # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture_reviewed/synth_sf2/top.v deleted 100644 → 0
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
architecture_reviewed/synth_sf2_lcov/synth_sf2_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_sf2 -edif edif.edif
architecture_reviewed/synth_sf2_lcov/synth_sf2_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_sf2 -json json.json
architecture_reviewed/synth_sf2_lcov/synth_sf2_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_sf2 -run begin:json
architecture_reviewed/synth_sf2_lcov/synth_sf2_vlog.ys deleted 100644 → 0
read_verilog ../top.v
synth_sf2 -vlog vlog.v
architecture_reviewed/synth_xilinx/synth_xilinx.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top adff
proc
#-assert option was skipped because of unproven cellss
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
select -assert-none t:BUFG t:FDCE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_abc9.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_abc9_retime_fail.pat deleted 100644 → 0
ERROR: -retime option not currently compatible with -abc9!
architecture_reviewed/synth_xilinx/synth_xilinx_abc9_retime_fail.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -abc9 -retime
write_verilog synth.v
architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s_abc9.pat deleted 100644 → 0
Warning: 'synth_xilinx -abc9' not currently supported for the 'xc6s' family, will use timing for 'xc7' instead.
architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6s_abc9.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
tee -o result.out equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc6v.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_arch_xc7.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc7 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc7 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_arch_xcu.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcu # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcu # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_arch_xcup.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcup # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcup # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_blif.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_dsp.ys deleted 100644 → 0
read_verilog ../top_dsp_simd.v
design -save read
hierarchy -top simd
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd simd # Constrain all select calls below inside the top module
stat
select -assert-count 3 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_edif.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_flatten.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_flatten_before_abc.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten_before_abc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten_before_abc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_fully_selected_fail.pat deleted 100644 → 0
ERROR: This command only operates on fully selected designs!
architecture_reviewed/synth_xilinx/synth_xilinx_iopad.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -iopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -iopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 2 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_ise.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 2 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_nobram.ys deleted 100644 → 0
read_verilog ../top_bram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -nobram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:BUFG
select -assert-count 35 t:FDRE
select -assert-count 3 t:LUT2
select -assert-count 4 t:LUT4
select -assert-count 16 t:LUT6
select -assert-count 8 t:MUXF7
select -assert-count 32 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_nocarry.ys deleted 100644 → 0
read_verilog ../top_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT4
select -assert-count 4 t:LUT6
select -assert-count 5 t:MUXCY
select -assert-count 6 t:XORCY
select -assert-none t:LUT2 t:LUT4 t:LUT6 t:MUXCY t:XORCY %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nocarry # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4
select -assert-count 4 t:LUT6
select -assert-none t:LUT2 t:LUT4 t:LUT6 %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_noclkbuf.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noclkbuf # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:FDRE
select -assert-none t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_nodram.ys deleted 100644 → 0
read_verilog ../top_dpram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 2 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 6 t:RAM64X1D
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -nodram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 2 t:BUFG
select -assert-count 390 t:FDRE
select -assert-count 90 t:LUT2
select -assert-count 10 t:LUT4
select -assert-count 155 t:LUT6
select -assert-count 32 t:MUXF7
select -assert-count 2 t:MUXF8
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_nodsp.ys deleted 100644 → 0
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 15 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 4 t:LUT4
select -assert-count 5 t:LUT5
select -assert-count 45 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 9 t:MUXF7
select -assert-count 3 t:MUXF8
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_noiopad.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_nosrl.ys deleted 100644 → 0
read_verilog ../top_nosrl.v
design -save read
hierarchy -top xilinx_srl_static_test
proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D
design -load read
hierarchy -top xilinx_srl_static_test
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nosrl # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 5 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_nowidelut.ys deleted 100644 → 0
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 6 t:LUT4
select -assert-count 1 t:LUT5
select -assert-count 33 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 1 t:MUXF7
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:LUT2
select -assert-count 6 t:LUT3
select -assert-count 5 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:XORCY %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_nowidelut_abc9.ys deleted 100644 → 0
read_verilog ../top_dsp.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 3 t:CARRY4
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 8 t:LUT4
select -assert-count 21 t:LUT5
select -assert-count 16 t:LUT6
select -assert-none t:CARRY4 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_retime.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_run.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -run begin:blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -run begin:blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_top.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_vpr.ys deleted 100644 → 0
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture_reviewed/synth_xilinx/synth_xilinx_widemux.ys deleted 100644 → 0
read_verilog ../top_mux.v
design -save read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 3 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture_reviewed/synth_xilinx/top.v deleted 100644 → 0
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
architecture_reviewed/synth_xilinx/top_bram.v deleted 100644 → 0
// Single-Port Block RAM Read-First Mode
// rams_sp_rf.v
module top (clk, en, we, addr, di, dout);
input clk;
input we;
input en;
input [8:0] addr;
input [7:0] di;
output [7:0] dout;
reg [7:0] RAM [511:0];
reg [7:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr]<=di;
dout <= RAM[addr];
end
end
endmodule
architecture_reviewed/synth_xilinx/top_dpram.v deleted 100644 → 0
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
*/
module top (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 6;
parameter data_width = 6;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
architecture_reviewed/synth_xilinx/top_dsp.v deleted 100644 → 0
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
architecture_reviewed/synth_xilinx/top_dsp_simd.v deleted 100644 → 0
module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24);
generate
genvar i;
// 4 x 12-bit adder
for (i = 0; i < 4; i++)
assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12];
// 2 x 24-bit subtract
for (i = 0; i < 2; i++)
assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24];
endgenerate
reg [3*12-1:0] ro;
always @* begin
ro[0*12+:12] = a[0*10+:10] + b[0*10+:10];
ro[1*12+:12] = a[1*10+:10] + b[1*10+:10];
ro[2*12+:12] = a[2*8+:8] + b[2*8+:8];
end
assign o12[4*12+:3*12] = ro;
endmodule
architecture_reviewed/synth_xilinx/top_mux.v deleted 100644 → 0
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
architecture_reviewed/synth_xilinx/top_nocarry.v deleted 100644 → 0
module top
(
input [2:0] x,
input [2:0] y,
output [5:0] A,
);
assign A = x * y;
endmodule
architecture_reviewed/synth_xilinx/top_nosrl.v deleted 100644 → 0
module xilinx_srl_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[3], shift1[3]};
endmodule
architecture_reviewed/synth_xilinx/top_srl.v deleted 100644 → 0
module top (
out,
out1,
clk,
in
);
output [7:0] out;
output [7:0] out1;
input signed clk, in;
reg signed [7:0] out;
reg signed [7:0] out1;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
always @(posedge clk)
begin
out1 <= out1 >> 1;
out1[7] <= in;
end
endmodule
architecture_reviewed/synth_xilinx/top_wide_ffs.v deleted 100644 → 0
module dff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
architecture_reviewed/synth_xilinx/xilinx_srl.ys deleted 100644 → 0
read_verilog ../top_srl.v
design -save read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
#select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -minlen 1
stat
select -assert-count 8 t:$__XILINX_SHREG_
select -assert-count 1 t:BUFG
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -variable
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -variable -minlen 1
stat
select -assert-count 8 t:$__XILINX_SHREG_
select -assert-count 1 t:BUFG
architecture_reviewed/synth_xilinx_dsp/assert_area.py deleted 100755 → 0
#!/usr/bin/python3
import glob
import re
import os
re_mux = re.compile(r'(mul|muladd|macc)_(\d+)(s?)_(\d+)(s?)(_(\d+)(s?))?_(A?B?C?M?P?)_A?B?C?M?P?\.v')
for fn in glob.glob('*.v'):
m = re_mux.match(fn)
if not m: continue
macc = m.group(1) == 'macc'
muladd = m.group(1) == 'muladd'
A,B = map(int, m.group(2,4))
Asigned,Bsigned = m.group(3,5)
if m.group(6):
C = int(m.group(7))
Csigned = m.group(8)
else:
C = 0
Areg = 'A' in m.group(9)
Breg = 'B' in m.group(9)
Mreg = 'M' in m.group(9)
Preg = 'P' in m.group(9) or macc
if A < B:
A,B = B,A
Asigned,Bsigned = Bsigned,Asigned
if not (Asigned and Bsigned):
A += 1
B += 1
Asigned = Bsigned = 1
if C > 0 and not Csigned:
C += 1
Csigned = 1
X = 1 + max(0,A-25+16) // 17
Y = 1 + max(0,B-18+16) // 17
count_MAC = X * Y
count_DFF = 0
if Mreg and (A > 25 or B > 18):
count_DFF += A + B
if not macc and (A > 25) ^ (B > 18):
count_DFF -= 1 # For pure multipliers with just one big dimension,
# expect last slice to absorb at least one register
if Preg and (A > 25 or B > 18 or C > 48):
count_DFF += max(A + B, C)
if macc:
count_DFF += 5 # In my testcases, accumulator is always
# 5bits bigger than multiplier result
elif ((A > 25) ^ (B > 18)) and C <= 48:
count_DFF -= 1 # For pure multipliers with just one big dimension,
# expect last slice to absorb at least one register
# TODO: More assert on number of CARRY and LUTs
count_CARRY = ''
if macc or muladd:
if A <= 25 and B <= 18 and C <= 48:
count_CARRY = '; select t:XORCY -assert-none; select t:LUT* -assert-none';
elif A <= 25 or B <= 18:
count_CARRY = '; select t:XORCY -assert-none; select t:LUT* -assert-none';
bn,_ = os.path.splitext(fn)
with open(fn, 'a') as f:
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd {0}; select t:DSP48E1 -assert-max {1}; select t:FD* -assert-max {2}{3}";
endmodule
`endif
'''.format(os.path.splitext(fn)[0], count_MAC, count_DFF, count_CARRY), file=f)
architecture_reviewed/synth_xilinx_dsp/generate_macc.py deleted 100644 → 0
#!/usr/bin/env python3
from common_macc import gen_macc
ARange = ['17','17s','18','18s','19','19s','24','24s','25','25s','36','36s','49','49s','50','50s','75','75s']
BRange = ['17','17s','18','18s','19','19s','27','27s','34','34s','35','35s','36','36s']
if __name__ == "__main__":
gen_macc(['24','49s'], ['17','36s'], reg="ABMP")
gen_macc(ARange, BRange, reg="")
architecture_reviewed/synth_xilinx_dsp/generate_mul.py deleted 100644 → 0
#!/usr/bin/env python3
from common_mul import gen_mul
ARange = ['17','17s','18','18s','19','19s','24','24s','25','25s','36','36s','49','49s','50','50s','75','75s']
BRange = ['17','17s','18','18s','19','19s','27','27s','34','34s','35','35s','36','36s']
if __name__ == "__main__":
gen_mul(['24','49s'], ['17','36s'], reg="ABMP")
gen_mul(ARange, BRange, reg="")
architecture_reviewed/synth_xilinx_dsp/generate_muladd.py deleted 100644 → 0
#!/usr/bin/env python3
from common_muladd import gen_muladd
ARange = ['24','24s','25','25s','36','36s']
BRange = ['17','17s','18','18s','19','19s']
CRange = ['32','32s','48','48s','96','96s']
if __name__ == "__main__":
gen_muladd(['24','49s'], ['17','36s'], ['47','96s'], reg="ABMP")
gen_muladd(ARange, BRange, CRange, reg="")
architecture_reviewed/synth_xilinx_dsp/macc_25s_18s__49bitaccum.v deleted 100644 → 0
(* top *)
module macc_25s_18s__49bitaccum #(parameter AW=25, BW=18, AREG=0, BREG=0, MREG=0) (input clk, CEA, CEB, CEM, CEP, input signed [AW-1:0] A, input signed [BW-1:0] B, output reg signed [49-1:0] P);
reg signed [AW-1:0] Ar;
reg signed [BW-1:0] Br;
reg signed [AW+BW-1:0] Mr;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (MREG) begin
always @(posedge clk) if (1) Mr <= Ar * Br;
end
else
always @* Mr <= Ar * Br;
always @(posedge clk) if (1) P <= P + Mr;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd macc_25s_18s__49bitaccum; select t:DSP48E1 -assert-count 1; select t:FD* -assert-count 49; select t:XORCY -assert-count 49; select t:LUT2 -assert-count 97";
endmodule
`endif
architecture_reviewed/synth_xilinx_dsp/mul_25s_18s_keepABP_.v deleted 100644 → 0
(* top *)
module mul_25s_18s_keepABP_ #(parameter AW=25, BW=18, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input signed [AW-1:0] A, input signed [BW-1:0] B, (* keep *) output reg signed [AW+BW-1:0] P);
(* keep *) reg signed [AW-1:0] Ar;
(* keep *) reg signed [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd mul_25s_18s_keepABP_; select t:DSP48E1 -assert-count 1; select t:FD* -assert-count 43";
endmodule
`endif
architecture_reviewed/synth_xilinx_dsp/mul_32_32_keepB_.v deleted 100644 → 0
(* top *)
module mul_32_32_keepB_ #(parameter AW=32, BW=32, AREG=1, BREG=1, PREG=0) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, output reg [AW+BW-1:0] P);
reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd mul_32_32_keepB_; select t:DSP48E1 -assert-count 4; select t:FD* -assert-count 32";
endmodule
`endif
architecture_reviewed/synth_xilinx_dsp/run-test.sh deleted 100755 → 0
#!/bin/bash
set -e
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \
synth_xilinx; \
design -copy-from __test *; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="$EXTRA_FLAGS"
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/common.py -O common_mul.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/macc/common.py -O common_macc.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/muladd/common.py -O common_muladd.py -o /dev/null
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_macc.py
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_muladd.py
python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed mul_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed macc_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed muladd_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
architecture_reviewed/synth_xilinx_dsp/ug901a.v deleted 100644 → 0
// Signed 40-bit streaming accumulator with 16-bit inputs
// File: HDL_Coding_Techniques/multipliers/multipliers4.v
//
// Source:
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
//
(* top *)
module ug901a # (parameter SIZEIN = 16, SIZEOUT = 40) (
input clk, ce, sload,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg sload_reg;
reg signed [2*SIZEIN-1:0] mult_reg;
reg signed [SIZEOUT-1:0] adder_out, old_result;
always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
if (sload_reg)
old_result <= 0;
else
// 'sload' is now active (=low) and opens the accumulation loop.
// The accumulator takes the next multiplier output in
// the same cycle.
old_result <= adder_out;
end
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
mult_reg <= a_reg * b_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + mult_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd ug901a; select t:DSP48E1 -assert-count 1; select t:FDRE -assert-count 1; select -assert-none t:DSP48E1 t:BUFG t:FDRE %% t:* %D";
endmodule
`endif
architecture_reviewed/synth_xilinx_dsp/ug901b.v deleted 100644 → 0
// 8-Tap Even Symmetric Systolic FIR
//
// Source:
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.93
//
(* top *)
module ug901b #(parameter nbtap = 4, dsize = 16, psize = 2*dsize) (
input clk,
input signed [dsize-1:0] datain,
output signed [2*dsize-1:0] firout
);
wire signed [dsize-1:0] h [nbtap-1:0];
wire signed [dsize-1:0] arraydata [nbtap-1:0];
wire signed [psize-1:0] arrayprod [nbtap-1:0];
wire signed [dsize-1:0] shifterout;
reg signed [dsize-1:0] dataz [nbtap-1:0];
assign h[0] = 7;
assign h[1] = 14;
assign h[2] = -138;
assign h[3] = 129;
assign firout = arrayprod[nbtap-1]; // Connect last product to output
sfir_shifter #(dsize, nbtap) shifter_inst0 (
clk,
datain,
shifterout);
generate
genvar I;
for (I=0; I<nbtap; I=I+1)
if (I==0)
sfir_even_symmetric_systolic_element #(dsize) fte_inst0 (
clk,
h[I],
datain,
shifterout,
{32{1'b0}},
arraydata[I],
arrayprod[I]);
else
sfir_even_symmetric_systolic_element #(dsize) fte_inst (
clk,
h[I],
arraydata[I-1],
shifterout,
arrayprod[I-1],
arraydata[I],
arrayprod[I]);
endgenerate
endmodule
(* gentb_skip *) // Prevents Yosys' test_autotb from operating on this module
(* dont_touch = "yes" *)
module sfir_shifter #(parameter dsize = 16, nbtap = 4) (
input clk,
input [dsize-1:0] datain,
output [dsize-1:0] dataout
);
(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
integer i;
always @(posedge clk)
begin
tmp[0] <= datain;
for (i=0; i<=2*nbtap-2; i=i+1)
tmp[i+1] <= tmp[i];
end
assign dataout = tmp[2*nbtap-1];
endmodule
(* gentb_skip *) // Prevents Yosys' test_autotb from operating on this module
module sfir_even_symmetric_systolic_element #(parameter dsize = 16) (
input clk,
input signed [dsize-1:0] coeffin, datain, datazin,
input signed [2*dsize-1:0] cascin,
output signed [dsize-1:0] cascdata,
output reg signed [2*dsize-1:0] cascout
);
reg signed [dsize-1:0] coeff;
reg signed [dsize-1:0] data;
reg signed [dsize-1:0] dataz;
reg signed [dsize-1:0] datatwo;
reg signed [dsize:0] preadd;
reg signed [2*dsize-1:0] product;
assign cascdata = datatwo;
always @(posedge clk)
begin
coeff <= coeffin;
data <= datain;
datatwo <= data;
dataz <= datazin;
preadd <= datatwo + dataz;
product <= preadd * coeff;
cascout <= product + cascin;
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd ug901b; flatten; select t:DSP48E1 -assert-count 4; select t:FDRE -assert-count 128; select t:SRL16E -assert-count 16; select -assert-none t:DSP48E1 t:BUFG t:FDRE t:SRL16E %% t:* %D";
endmodule
`endif
architecture_reviewed/synth_xilinx_mux/assert_area.py deleted 100755 → 0
#!/usr/bin/python3
import glob
import re
import os
re_mux = re.compile(r'mux_(index|case|if_bal|if_unbal)_(\d+)_(\d+)\.v')
area = {}
# 1 2 3 4 5 6 F7 F8
area[2] = [ 0, 0, 1, 0, 0, 0, 0, 0 ]
area[3] = [ 0, 0, 0, 0, 1, 0, 0, 0 ]
area[4] = [ 0, 0, 0, 0, 0, 0, 2, 1 ]
area[5] = [ 0, 0, 1, 0, 0, 0, 2, 1 ]
area[7] = [ 0, 0, 3, 0, 0, 0, 2, 1 ]
area[8] = [ 0, 0, 4, 0, 0, 0, 2, 1 ]
area[9] = [ 0, 0, 3, 0, 1, 0, 2, 1 ]
area[15] = [ 0, 0, 0, 0, 1, 3, 2, 1 ]
area[16] = [ 0, 0, 0, 0, 0, 4, 2, 1 ]
area[17] = [ 0, 0, 1, 0, 0, 4, 2, 1 ]
area[31] = [ 0, 0, 1, 0, 1, 7, 4, 2 ]
area[32] = [ 0, 0, 1, 0, 0, 8, 4, 2 ]
area[33] = [ 0, 0, 0, 0, 1, 8, 4, 2 ]
area[63] = [ 0, 0, 0, 0, 1,15,10, 5 ]
area[64] = [ 0, 0, 0, 0, 0,16,10, 5 ]
area[65] = [ 0, 0, 1, 0, 0,16,10, 5 ]
area[127] = [ 0, 0, 4, 0, 1,31,18, 9 ]
area[128] = [ 0, 0, 4, 0, 0,32,18, 9 ]
area[129] = [ 0, 0, 3, 0, 1,32,18, 9 ]
area[255] = [ 0, 0, 0, 0, 1,67,34,17 ]
area[256] = [ 0, 0, 0, 0, 0,68,34,17 ]
area[257] = [ 0, 0, 1, 0, 0,68,34,17 ]
for fn in glob.glob('*.v'):
m = re_mux.match(fn)
if not m: continue
N,W = map(int, m.group(2,3))
assert N in area
bn,_ = os.path.splitext(fn)
with open(fn, 'a') as f:
assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd; %s";
endmodule
`endif
''' % '; '.join(assert_area), file=f)
architecture_reviewed/synth_xilinx_mux/run-test.sh deleted 100755 → 0
#!/bin/bash
set -e
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/generate.py -O generate_small.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/common.py -O common.py -o /dev/null
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
python3 generate_small.py
python3 generate_large.py
python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \
synth_xilinx -abc9 -widemux 4; \
design -copy-from __test *; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
# Spot tests for -widemux thresholds
set +e
../../../../../yosys -qp "synth_xilinx -widemux 1" 2> /dev/null
if [ $? -eq 0 ]; then
echo "Expected error"
exit 1
fi
set -e
../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-none t:MUXF*" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 1 t:MUXF7" mux_if_bal_2_1.v
../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-count 6 t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 6 t:MUXF*" mux_case_3_3.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 9; select -assert-none t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 8; select -assert-none t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 7; select -assert-count 15 t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 6; select -assert-count 15 t:MUXF*" mux_index_7_5.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 18; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 17; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 16; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 15; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
architecture_reviewed/synth_xilinx_srl/multiclock.v deleted 100644 → 0
(* top *)
module multiclock (input clk1, clk2, i, output q);
reg [6:0] r;
always @(posedge clk1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
always @(posedge clk2)
r[3] <= r[2];
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multiclock; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/multiclock_var_len.v deleted 100644 → 0
(* top *)
module multiclock_var_len (input clk1, clk2, i, input [2:0] l, output q);
reg [6:0] r;
always @(posedge clk1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
always @(posedge clk2)
r[3] <= r[2];
assign q = r[l];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multiclock_var_len; select t:SRL* -assert-count 0; select t:FD* -assert-count 7";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/multien.v deleted 100644 → 0
(* top *)
module multiclock (input clk, en1, en2, i, output q);
reg [6:0] r;
always @(posedge clk) begin
if (en1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
if (en2)
r[3] <= r[2];
end
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multiclock; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/multien_var_len.v deleted 100644 → 0
(* top *)
module multien_var_len (input clk, en1, en2, i, input [2:0] l, output q);
reg [6:0] r;
always @(posedge clk) begin
if (en1) begin
r[2:0] <= {r[1:0], i};
r[6:4] <= r[5:3];
end
if (en2)
r[3] <= r[2];
end
assign q = r[l];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd multien_var_len; select t:SRL* -assert-count 0; select t:FD* -assert-count 7";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v deleted 100644 → 0
// Check multi-bit works
// neg_clk_no_enable_with_init_with_inferred_N_width
(* top *)
module neg_clk_no_enable_with_init_with_inferred_N_width #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) int[w] <= { int[w][depth-2:0], i[w] };
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_N_width; select t:FD* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v deleted 100644 → 0
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset
(* top *)
module neg_clk_no_enable_with_init_with_inferred_with_reset #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= { int[w][depth-2:0], i[w] };
assign q[w] = int[w][depth-1];
end
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_with_reset; select t:SRL* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v deleted 100644 → 0
// Check that use of resets block shreg
// neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
(* top *)
module neg_clk_no_enable_with_init_with_inferred_with_reset_var_len #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk or posedge r) if (r) int[w] <= 1'b0; else int[w] <= a[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk or posedge r) if (r) int[w] <= {width{1'b0}}; else int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_with_reset_var_len; select t:SRL* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v deleted 100644 → 0
// Check multi-bit works
// pos_clk_no_enable_no_init_not_inferred_N_width
(* top *)
module pos_clk_no_enable_no_init_not_inferred_N_width #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b0), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_N_width; select t:FD* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v deleted 100644 → 0
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset
(* top *)
module pos_clk_no_enable_no_init_not_inferred_with_reset #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_with_reset; select t:SRL* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v deleted 100644 → 0
// Check that use of resets block shreg
// pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
(* top *)
module pos_clk_no_enable_no_init_not_inferred_with_reset_var_len #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFF_PP0_ r(.C(clk), .D(int[w][d]), .R(r), .Q(int[w][d+1]));
end
wire [depth-1:0] t;
assign t = int[w][depth:1];
assign q[w] = t[l];
end
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_with_reset_var_len; select t:SRL* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/rotate_3.v deleted 100644 → 0
(* top *)
module rotate_3 (input clk, output q);
reg [2:0] r;
initial r = 3'b101;
always @(posedge clk)
r <= {r[1:0], r[2]};
assign q = r[2];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_3; select t:SRL* -assert-count 1; select t:FD* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/rotate_3_fdre.v deleted 100644 → 0
(* top *)
module rotate_3_fdre (input clk, output q);
wire [2:0] r;
FDRE #(.INIT(1'b1)) r0 (.C(clk), .CE(1'b1), .D(r[2]), .R(1'b0), .Q(r[0]));
FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]), .Q(r[1]));
FDRE #(.INIT(1'b0)) r2 (.C(clk), .CE(1'b1), .D(r[1]), .R(1'b0), .Q(r[2]));
assign q = r[2];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_3_fdre; select t:SRL* -assert-count 1; select t:FD* -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/rotate_3_var_len.v deleted 100644 → 0
(* top *)
module rotate_3_var_len (input clk, input [1:0] l, output q);
reg [2:0] r;
initial r = 3'b101;
always @(posedge clk)
r <= {r[1:0], r[2]};
assign q = r[l];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_3_var_len; select t:SRL* -assert-count 0; select t:FD* -assert-count 3";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/rotate_7_fdre_param.v deleted 100644 → 0
(* top *)
module rotate_7_fdre_param (input clk, output q);
wire [6:0] r;
FDRE #(.INIT(1'b1)) r0 (.C(clk), .CE(1'b1), .D(r[6]), .R(1'b0), .Q(r[0]));
FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]), .R(1'b0), .Q(r[1]));
FDRE #(.INIT(1'b0)) r2 (.C(clk), .CE(1'b1), .D(r[1]), .R(1'b0), .Q(r[2]));
FDRE #(.INIT(1'b1), .IS_C_INVERTED(1)) r3 (.C(clk), .CE(1'b1), .D(r[2]), .R(reset), .Q(r[3]));
FDRE #(.INIT(1'b0)) r4 (.C(clk), .CE(1'b1), .D(r[3]), .R(1'b0), .Q(r[4]));
FDRE #(.INIT(1'b0)) r5 (.C(clk), .CE(1'b1), .D(r[4]), .R(1'b0), .Q(r[5]));
FDRE #(.INIT(1'b0)) r6 (.C(clk), .CE(1'b1), .D(r[5]), .R(1'b0), .Q(r[6]));
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_7_fdre_param; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/rotate_7_fdre_reset.v deleted 100644 → 0
(* top *)
module rotate_7_fdre_reset (input clk, reset, output q);
wire [6:0] r;
FDRE #(.INIT(1'b1)) r0 (.C(clk), .CE(1'b1), .D(r[6]), .R(1'b0), .Q(r[0]));
FDRE #(.INIT(1'b0)) r1 (.C(clk), .CE(1'b1), .D(r[0]), .R(1'b0), .Q(r[1]));
FDRE #(.INIT(1'b0)) r2 (.C(clk), .CE(1'b1), .D(r[1]), .R(1'b0), .Q(r[2]));
FDRE #(.INIT(1'b1)) r3 (.C(clk), .CE(1'b1), .D(r[2]), .R(reset), .Q(r[3]));
FDRE #(.INIT(1'b0)) r4 (.C(clk), .CE(1'b1), .D(r[3]), .R(1'b0), .Q(r[4]));
FDRE #(.INIT(1'b0)) r5 (.C(clk), .CE(1'b1), .D(r[4]), .R(1'b0), .Q(r[5]));
FDRE #(.INIT(1'b0)) r6 (.C(clk), .CE(1'b1), .D(r[5]), .R(1'b0), .Q(r[6]));
assign q = r[6];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd rotate_7_fdre_reset; select t:SRL* -assert-count 2; select t:FD* -assert-count 1";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/run-test.sh deleted 100755 → 0
#!/bin/bash
set -e
shopt -s extglob
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
python3 generate_lfsr.py
python3 ../generate.py
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed test21*.v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \
-p 'design -copy-to __test __test; \
synth_xilinx -retime; \
design -copy-from __test __test; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
architecture_reviewed/synth_xilinx_srl/sr_fixed_length_other_users_port.v deleted 100644 → 0
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_port
(* top *)
module sr_fixed_length_other_users_port #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_fixed_length_other_users_port; select t:SRL* -assert-count 0";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/sr_fixed_length_other_users_xor.v deleted 100644 → 0
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_fixed_length_other_users_xor
(* top *)
module sr_fixed_length_other_users_xor #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
generate
wire [depth:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
assign int[w][0] = i[w];
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
end
assign q[w] = int[w][depth];
end
assign state = int[0][depth:1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_fixed_length_other_users_xor; select t:SRL* -assert-count 0";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/sr_var_length_other_users_port.v deleted 100644 → 0
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_port
(* top *)
module sr_var_length_other_users_port #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
assign state = int[0];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_var_length_other_users_port; select t:SRL* -assert-count 0";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/sr_var_length_other_users_xor.v deleted 100644 → 0
// Check that non chain users block SRLs
// (i.e. output port, in non flattened case)
// sr_var_length_other_users_xor
(* top *)
module sr_var_length_other_users_xor #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
generate
reg [depth-1:0] int [width-1:0];
genvar w, d;
for (w = 0; w < width; w=w+1) begin
for (d = 0; d < depth; d=d+1)
initial int[w][d] <= ~((d+w) % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int[w] <= i[w];
assign q[w] = int[w];
end
else begin
always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
assign q[w] = int[w][l];
end
end
assign state = {depth{^int[0]}};
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd sr_var_length_other_users_xor; select t:SRL* -assert-count 0";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test17a.v deleted 100644 → 0
// Check inference even when not in vector
(* top *)
module test17a (input clk, input i, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) a1 <= i;
always @(posedge clk) a2 <= a1;
always @(posedge clk) a3 <= a2;
always @(posedge clk) a4 <= a3;
always @(posedge clk) a5 <= a4;
always @(posedge clk) a6 <= a5;
always @(posedge clk) a7 <= a6;
always @(posedge clk) a8 <= a7;
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17a; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test17b.v deleted 100644 → 0
// Check inference even when not in vector
(* top *)
module test17b (input clk, input i, input e, output q);
generate
reg a1, a2, a3, a4, a5, a6, a7, a8;
always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17b; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test17c.v deleted 100644 → 0
// Check inference even when keep attribute specified
(* top *)
module test17c (input clk, input i, input e, output q);
generate
reg a1, a2, a3;
(* keep *) reg a4;
reg a5, a6, a7, a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17c; select t:SRL16E -assert-count 2; select t:BUFG t:SRL16E %% %n t:* %i -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test17d.v deleted 100644 → 0
// Check inference even when keep attribute specified
(* top *)
module test17d (input clk, input i, input e, output q);
generate
reg a1, a2;
(* keep *) reg a3;
(* keep *) reg a4;
reg a5, a6, a7, a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17d; select t:SRL16E -assert-count 2; select t:FD* -assert-count 1; select t:BUFG t:SRL16E t:FD* %% %n t:* %i -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test17e.v deleted 100644 → 0
// Check inference even when keep attribute specified
(* top *)
module test17e (input clk, input i, input e, output q);
generate
reg a1, a2;
(* blah *) reg a3;
reg a4, a5, a6;
(* boo *) reg a7;
reg a8;
always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
assign q = a8;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test17e; select t:SRL16E -assert-count 1; select t:BUFG t:SRL16E %% %n t:* %i -assert-none;";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test20.v deleted 100644 → 0
(* top *)
module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(negedge clk) if (e) int[d][w] <= i[w];
end
else begin
always @(negedge clk) if (e) int[d][w] <= int[d-1][w];
end
end
end
assign z = int[depth-1];
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test20; select t:FD* -assert-count 0";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test21a.v deleted 100644 → 0
(* top *)
module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
genvar d;
wire [depth:0] int;
assign int[0] = ^i[width-1:0];
generate
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1]));
end
endgenerate
assign q = int[depth];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21a; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/test21b.v deleted 100644 → 0
(* top *)
module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
reg [depth-1:0] int;
genvar d;
for (d = 0; d < depth; d=d+1)
initial int[d] <= ~(d % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int <= ~^i[width-1:0];
assign q = int;
end
else begin
always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] };
assign q = int[depth-1];
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd test21b; select t:SRL* -assert-count 0; select t:FD* -assert-min 20";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/ug901a.v deleted 100644 → 0
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 8-bit Shift Register
// Rising edge clock
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
(* top *)
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk)
begin
if (clken)
shreg <= {shreg[WIDTH-2:0], SI};
end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_0; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/ug901b.v deleted 100644 → 0
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 32-bit Shift Register
// Rising edge clock
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
(* top *)
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
integer i;
always @(posedge clk)
begin
if (clken)
begin
for (i = 0; i < WIDTH-1; i = i+1)
shreg[i+1] <= shreg[i];
shreg[0] <= SI;
end
end
assign SO = shreg[WIDTH-1];
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd shift_registers_1; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture_reviewed/synth_xilinx_srl/ug901c.v deleted 100644 → 0
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
(* top *)
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
input [SELWIDTH-1:0] SEL;
output DO;
localparam DATAWIDTH = 2**SELWIDTH;
reg [DATAWIDTH-1:0] data;
assign DO = data[SEL];
always @(posedge CLK)
begin
if (CE == 1'b1)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd dynamic_shift_register_1; select t:SRLC32E -assert-count 1; select t:BUFG t:SRLC32E %% %n t:* %i -assert-none";
endmodule
`endif
architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_sdp_read_wider.v deleted 100644 → 0
// Asymmetric port RAM
// Read Wider than Write. Read Statement in loop
//asym_ram_sdp_read_wider.v
module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB);
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkA)
begin
if (enaA) begin
if (weA)
RAM[addrA] <= diA;
end
end
always @(posedge clkB)
begin : ramread
integer i;
reg [log2RATIO-1:0] lsbaddr;
if (enaB) begin
for (i = 0; i < RATIO; i = i+1) begin
lsbaddr = i;
readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
end
end
end
assign doB = readB;
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_sdp_write_wider.v deleted 100644 → 0
// Asymmetric port RAM
// Write wider than Read. Write Statement in a loop.
// asym_ram_sdp_write_wider.v
module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;
//parameter WIDTHA = 16;
//parameter WIDTHA = 8;
parameter WIDTHA = 4;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHB-1:0] readB;
always @(posedge clkB) begin
if (enaB) begin
readB <= RAM[addrB];
end
end
assign doB = readB;
always @(posedge clkA)
begin : ramwrite
integer i;
reg [log2RATIO-1:0] lsbaddr;
for (i=0; i< RATIO; i= i+ 1) begin : write1
lsbaddr = i;
if (enaA) begin
if (weA)
RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
end
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_tdp_read_first.v deleted 100644 → 0
// Asymetric RAM - TDP
// READ_FIRST MODE.
// asym_ram_tdp_read_first.v
module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
parameter WIDTHB = 4;
parameter SIZEB = 1024;
parameter ADDRWIDTHB = 10;
parameter WIDTHA = 16;
parameter SIZEA = 256;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA, weB;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
input [WIDTHB-1:0] diB;
output [WIDTHA-1:0] doA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHA-1:0] readA;
reg [WIDTHB-1:0] readB;
always @(posedge clkB)
begin
if (enaB) begin
readB <= RAM[addrB] ;
if (weB)
RAM[addrB] <= diB;
end
end
always @(posedge clkA)
begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr ;
for (i=0; i< RATIO; i= i+ 1) begin
lsbaddr = i;
if (enaA) begin
readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
if (weA)
RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
end
end
end
assign doA = readA;
assign doB = readB;
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/asym_ram_tdp_write_first.v deleted 100644 → 0
// Asymmetric port RAM - TDP
// WRITE_FIRST MODE.
// asym_ram_tdp_write_first.v
module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
parameter WIDTHB = 4;
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
//parameter ADDRWIDTHB = 10;
parameter SIZEB = 32;
parameter ADDRWIDTHB = 8;
//parameter WIDTHA = 16;
parameter WIDTHA = 4;
//parameter SIZEA = 256;
parameter SIZEA = 32;
parameter ADDRWIDTHA = 8;
input clkA;
input clkB;
input weA, weB;
input enaA, enaB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
input [WIDTHB-1:0] diB;
output [WIDTHA-1:0] doA;
output [WIDTHB-1:0] doB;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [WIDTHA-1:0] readA;
reg [WIDTHB-1:0] readB;
always @(posedge clkB)
begin
if (enaB) begin
if (weB)
RAM[addrB] = diB;
readB = RAM[addrB] ;
end
end
always @(posedge clkA)
begin : portA
integer i;
reg [log2RATIO-1:0] lsbaddr ;
for (i=0; i< RATIO; i= i+ 1) begin
lsbaddr = i;
if (enaA) begin
if (weA)
RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH];
readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}];
end
end
end
assign doA = readA;
assign doB = readB;
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/black_box_1.v deleted 100644 → 0
// Black Box
// black_box_1.v
//
(* black_box *) module black_box1 (in1, in2, dout);
input in1, in2;
output dout;
endmodule
module black_box_1 (DI_1, DI_2, DOUT);
input DI_1, DI_2;
output DOUT;
black_box1 U1 (
.in1(DI_1),
.in2(DI_2),
.dout(DOUT)
);
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_ram_1b.v deleted 100644 → 0
// Single-Port BRAM with Byte-wide Write Enable
// Read-First mode
// Single-process description
// Compact description of the write with a generate-for
// statement
// Column width and number of columns easily configurable
//
// bytewrite_ram_1b.v
//
module bytewrite_ram_1b (clk, we, addr, di, do);
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
parameter SIZE = 32;
parameter ADDR_WIDTH = 10;
parameter COL_WIDTH = 8;
parameter NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] di;
output reg [NB_COL*COL_WIDTH-1:0] do;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
always @(posedge clk)
begin
do <= RAM[addr];
end
generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
if (we[i])
RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
end
endgenerate
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_nc.v deleted 100644 → 0
//
// True-Dual-Port BRAM with Byte-wide Write Enable
// No-Change mode
//
// bytewrite_tdp_ram_nc.v
//
// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended
module bytewrite_tdp_ram_nc
#(
//---------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//---------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkA) begin
if(enaA) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkA) begin
if(enaA) begin
if (~|weA)
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
generate
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkB) begin
if(enaB) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkB) begin
if(enaB) begin
if (~|weB)
doutB <= ram_block[addrB];
end
end
endmodule // bytewrite_tdp_ram_nc
architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_readfirst2.v deleted 100644 → 0
// ByteWide Write Enable, - Alternate READ_FIRST mode template - Vivado recomended
// bytewrite_tdp_ram_readfirst2.v
module bytewrite_tdp_ram_readfirst2
#(
//-------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//-------------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkA) begin
if(enaA) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkA) begin
if(enaA) begin
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
generate
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkB) begin
if(enaB) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
end
end
end
end
endgenerate
always @ (posedge clkB) begin
if(enaB) begin
doutB <= ram_block[addrB];
end
end
endmodule // bytewrite_tdp_ram_readfirst2
architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_rf.v deleted 100644 → 0
// True-Dual-Port BRAM with Byte-wide Write Enable
// Read-First mode
// bytewrite_tdp_ram_rf.v
//
module bytewrite_tdp_ram_rf
#(
//--------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
integer i;
// Port-A Operation
always @ (posedge clkA) begin
if(enaA) begin
for(i=0;i<NUM_COL;i=i+1) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
end
end
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
always @ (posedge clkB) begin
if(enaB) begin
for(i=0;i<NUM_COL;i=i+1) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
end
end
doutB <= ram_block[addrB];
end
end
endmodule // bytewrite_tdp_ram_rf
architecture_reviewed/xilinx_ug901_synthesis_examples/bytewrite_tdp_ram_wf.v deleted 100644 → 0
// True-Dual-Port BRAM with Byte-wide Write Enable
// Write-First mode
// File: HDL_Coding_Techniques/rams/bytewrite_tdp_ram_wf.v
//
// ByteWide Write Enable, - WRITE_FIRST mode template - Vivado recomended
module bytewrite_tdp_ram_wf
#(
//----------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkA) begin
if(enaA) begin
if(weA[i]) begin
ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
doutA[i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH] ;
end else begin
doutA[i*COL_WIDTH +: COL_WIDTH] <= ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] ;
end
end
end
end
endgenerate
// Port-B Operation:
generate
for(i=0;i<NUM_COL;i=i+1) begin
always @ (posedge clkB) begin
if(enaB) begin
if(weB[i]) begin
ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
doutB[i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH] ;
end else begin
doutB[i*COL_WIDTH +: COL_WIDTH] <= ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] ;
end
end
end
end
endgenerate
endmodule // bytewrite_tdp_ram_wf
architecture_reviewed/xilinx_ug901_synthesis_examples/cmacc.v deleted 100644 → 0
// Complex Multiplier with accumulation (pr+i.pi) = (ar+i.ai)*(br+i.bi)
// File: cmacc.v
// The RTL below describes a complex multiplier with accumulation
// which can be packed into 3 DSP blocks (Ultrascale architecture)
//Default parameters were changed because of slow test
//module cmacc # (parameter AWIDTH = 16, BWIDTH = 18, SIZEOUT = 40)
module cmacc # (parameter AWIDTH = 4, BWIDTH = 5, SIZEOUT = 9)
(
input clk,
input sload,
input signed [AWIDTH-1:0] ar,
input signed [AWIDTH-1:0] ai,
input signed [BWIDTH-1:0] br,
input signed [BWIDTH-1:0] bi,
output signed [SIZEOUT-1:0] pr,
output signed [SIZEOUT-1:0] pi);
reg signed [AWIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd;
reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd;
reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
reg signed [AWIDTH:0] addcommon;
reg signed [BWIDTH:0] addr, addi;
reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi;
reg signed [SIZEOUT-1:0] pr_int, pi_int, old_result_real, old_result_im;
reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2;
reg sload_reg;
`ifdef SIM
initial
begin
ai_d = 0;
ai_dd = 0;
ai_ddd = 0;
ai_dddd = 0;
ar_d = 0;
ar_dd = 0;
ar_ddd = 0;
ar_dddd = 0;
bi_d = 0;
bi_dd = 0;
bi_ddd = 0;
br_d = 0;
br_dd = 0;
br_ddd = 0;
end
`endif
always @(posedge clk)
begin
ar_d <= ar;
ar_dd <= ar_d;
ai_d <= ai;
ai_dd <= ai_d;
br_d <= br;
br_dd <= br_d;
br_ddd <= br_dd;
bi_d <= bi;
bi_dd <= bi_d;
bi_ddd <= bi_dd;
sload_reg <= sload;
end
// Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
//
always @(posedge clk)
begin
addcommon <= ar_d - ai_d;
mult0 <= addcommon * bi_dd;
common <= mult0;
end
// Accumulation loop (combinatorial) for *Real*
//
always @(sload_reg or pr_int)
if (sload_reg)
old_result_real <= 0;
else
// 'sload' is now and opens the accumulation loop.
// The accumulator takes the next multiplier output
// in the same cycle.
old_result_real <= pr_int;
// Real product
//
always @(posedge clk)
begin
ar_ddd <= ar_dd;
ar_dddd <= ar_ddd;
addr <= br_ddd - bi_ddd;
multr <= addr * ar_dddd;
commonr1 <= common;
pr_int <= multr + commonr1 + old_result_real;
end
// Accumulation loop (combinatorial) for *Imaginary*
//
always @(sload_reg or pi_int)
if (sload_reg)
old_result_im <= 0;
else
// 'sload' is now and opens the accumulation loop.
// The accumulator takes the next multiplier output
// in the same cycle.
old_result_im <= pi_int;
// Imaginary product
//
always @(posedge clk)
begin
ai_ddd <= ai_dd;
ai_dddd <= ai_ddd;
addi <= br_ddd + bi_ddd;
multi <= addi * ai_dddd;
commonr2 <= common;
pi_int <= multi + commonr2 + old_result_im;
end
assign pr = pr_int;
assign pi = pi_int;
endmodule // cmacc
architecture_reviewed/xilinx_ug901_synthesis_examples/cmult.v deleted 100644 → 0
//
// Complex Multiplier (pr+i.pi) = (ar+i.ai)*(br+i.bi)
// file: cmult.v
//module cmult # (parameter AWIDTH = 16, BWIDTH = 18)
module cmult # (parameter AWIDTH = 8, BWIDTH = 9)
(
input clk,
input signed [AWIDTH-1:0] ar, ai,
input signed [BWIDTH-1:0] br, bi,
output signed [AWIDTH+BWIDTH:0] pr, pi
);
reg signed [AWIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd ;
reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd ;
reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd ;
reg signed [AWIDTH:0] addcommon ;
reg signed [BWIDTH:0] addr, addi ;
reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi, pr_int, pi_int ;
reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2 ;
always @(posedge clk)
begin
ar_d <= ar;
ar_dd <= ar_d;
ai_d <= ai;
ai_dd <= ai_d;
br_d <= br;
br_dd <= br_d;
br_ddd <= br_dd;
bi_d <= bi;
bi_dd <= bi_d;
bi_ddd <= bi_dd;
end
// Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
//
always @(posedge clk)
begin
addcommon <= ar_d - ai_d;
mult0 <= addcommon * bi_dd;
common <= mult0;
end
// Real product
//
always @(posedge clk)
begin
ar_ddd <= ar_dd;
ar_dddd <= ar_ddd;
addr <= br_ddd - bi_ddd;
multr <= addr * ar_dddd;
commonr1 <= common;
pr_int <= multr + commonr1;
end
// Imaginary product
//
always @(posedge clk)
begin
ai_ddd <= ai_dd;
ai_dddd <= ai_ddd;
addi <= br_ddd + bi_ddd;
multi <= addi * ai_dddd;
commonr2 <= common;
pi_int <= multi + commonr2;
end
assign pr = pr_int;
assign pi = pi_int;
endmodule // cmult
architecture_reviewed/xilinx_ug901_synthesis_examples/dynamic_shift_registers_1.v deleted 100644 → 0
// 32-bit dynamic shift register.
// Download:
// File: dynamic_shift_registers_1.v
module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 5;
input CLK, CE, SI;
input [SELWIDTH-1:0] SEL;
output DO;
localparam DATAWIDTH = 2**SELWIDTH;
reg [DATAWIDTH-1:0] data;
assign DO = data[SEL];
always @(posedge CLK)
begin
if (CE == 1'b1)
data <= {data[DATAWIDTH-2:0], SI};
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/dynpreaddmultadd.v deleted 100644 → 0
// Pre-add/subtract select with Dynamic control
// dynpreaddmultadd.v
//Default parameters were changed because of slow test.
//module dynpreaddmultadd # (parameter SIZEIN = 16)
module dynpreaddmultadd # (parameter SIZEIN = 8)
(
input clk, ce, rst, subadd,
input signed [SIZEIN-1:0] a, b, c, d,
output signed [2*SIZEIN:0] dynpreaddmultadd_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
reg signed [SIZEIN:0] add_reg;
reg signed [2*SIZEIN:0] d_reg, m_reg, p_reg;
always @(posedge clk)
begin
if (rst)
begin
a_reg <= 0;
b_reg <= 0;
c_reg <= 0;
d_reg <= 0;
add_reg <= 0;
m_reg <= 0;
p_reg <= 0;
end
else if (ce)
begin
a_reg <= a;
b_reg <= b;
c_reg <= c;
d_reg <= d;
if (subadd)
add_reg <= a_reg - b_reg;
else
add_reg <= a_reg + b_reg;
m_reg <= add_reg * c_reg;
p_reg <= m_reg + d_reg;
end
end
// Output accumulation result
assign dynpreaddmultadd_out = p_reg;
endmodule // dynpreaddmultadd
architecture_reviewed/xilinx_ug901_synthesis_examples/fsm_1.v deleted 100644 → 0
// State Machine with single sequential block
//fsm_1.v
module fsm_1(clk,reset,flag,sm_out);
input clk,reset,flag;
output reg sm_out;
parameter s1 = 3'b000;
parameter s2 = 3'b001;
parameter s3 = 3'b010;
parameter s4 = 3'b011;
parameter s5 = 3'b111;
reg [2:0] state;
always@(posedge clk)
begin
if(reset)
begin
state <= s1;
sm_out <= 1'b1;
end
else
begin
case(state)
s1: if(flag)
begin
state <= s2;
sm_out <= 1'b1;
end
else
begin
state <= s3;
sm_out <= 1'b0;
end
s2: begin state <= s4; sm_out <= 1'b0; end
s3: begin state <= s4; sm_out <= 1'b0; end
s4: begin state <= s5; sm_out <= 1'b1; end
s5: begin state <= s1; sm_out <= 1'b1; end
endcase
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/latches.v deleted 100644 → 0
// Latch with Positive Gate and Asynchronous Reset
// File: latches.v
module latches (
input G,
input D,
input CLR,
output reg Q
);
always @ *
begin
if(CLR)
Q = 0;
else if(G)
Q = D;
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/macc.v deleted 100644 → 0
// Signed 40-bit streaming accumulator with 16-bit inputs
// File: macc.v
//
module macc # (
parameter SIZEIN = 16, SIZEOUT = 40
)
(
input clk, ce, sload,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg sload_reg;
reg signed [2*SIZEIN:0] mult_reg;
reg signed [SIZEOUT-1:0] adder_out, old_result;
always @(adder_out or sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
// 'sload' is now active (=low) and opens the accumulation loop.
// The accumulator takes the next multiplier output in
// the same cycle.
old_result <= adder_out;
end
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
mult_reg <= a_reg * b_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + mult_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule // macc
architecture_reviewed/xilinx_ug901_synthesis_examples/mult_unsigned.v deleted 100644 → 0
// Unsigned 16x24-bit Multiplier
// 1 latency stage on operands
// 3 latency stage after the multiplication
// File: multipliers2.v
//
module mult_unsigned (clk, A, B, RES);
//Default parameters were changed because of slow test
//parameter WIDTHA = 16;
//parameter WIDTHB = 24;
parameter WIDTHA = 8;
parameter WIDTHB = 12;
input clk;
input [WIDTHA-1:0] A;
input [WIDTHB-1:0] B;
output [WIDTHA+WIDTHB-1:0] RES;
reg [WIDTHA-1:0] rA;
reg [WIDTHB-1:0] rB;
reg [WIDTHA+WIDTHB-1:0] M [3:0];
integer i;
always @(posedge clk)
begin
rA <= A;
rB <= B;
M[0] <= rA * rB;
for (i = 0; i < 3; i = i+1)
M[i+1] <= M[i];
end
assign RES = M[3];
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/presubmult.v deleted 100644 → 0
//
// Pre-adder support in subtract mode for DSP block
// File: presubmult.v
module presubmult # (//Default parameters were changed because of slow test
// parameter SIZEIN = 16
parameter SIZEIN = 8
)
(
input clk, ce, rst,
input signed [SIZEIN-1:0] a, b, c,
output signed [2*SIZEIN:0] presubmult_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
reg signed [SIZEIN:0] add_reg;
reg signed [2*SIZEIN:0] m_reg, p_reg;
always @(posedge clk)
if (rst)
begin
a_reg <= 0;
b_reg <= 0;
c_reg <= 0;
add_reg <= 0;
m_reg <= 0;
p_reg <= 0;
end
else if (ce)
begin
a_reg <= a;
b_reg <= b;
c_reg <= c;
add_reg <= a - b;
m_reg <= add_reg * c_reg;
p_reg <= m_reg;
end
// Output accumulation result
assign presubmult_out = p_reg;
endmodule // presubmult
architecture_reviewed/xilinx_ug901_synthesis_examples/ram_simple_dual_one_clock.v deleted 100644 → 0
// Simple Dual-Port Block RAM with One Clock
// File: simple_dual_one_clock.v
module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);
input clk,ena,enb,wea;
input [9:0] addra,addrb;
input [15:0] dia;
output [15:0] dob;
reg [15:0] ram [1023:0];
reg [15:0] doa,dob;
always @(posedge clk) begin
if (ena) begin
if (wea)
ram[addra] <= dia;
end
end
always @(posedge clk) begin
if (enb)
dob <= ram[addrb];
end
endmodule
\ No newline at end of file
architecture_reviewed/xilinx_ug901_synthesis_examples/ram_simple_dual_two_clocks.v deleted 100644 → 0
// Simple Dual-Port Block RAM with Two Clocks
// File: simple_dual_two_clocks.v
module simple_dual_two_clocks (clka,clkb,ena,enb,wea,addra,addrb,dia,dob);
input clka,clkb,ena,enb,wea;
input [9:0] addra,addrb;
input [15:0] dia;
output [15:0] dob;
reg [15:0] ram [1023:0];
reg [15:0] dob;
always @(posedge clka)
begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
end
end
always @(posedge clkb)
begin
if (enb)
begin
dob <= ram[addrb];
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_dist.v deleted 100644 → 0
// Dual-Port RAM with Asynchronous Read (Distributed RAM)
// File: rams_dist.v
module rams_dist (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [5:0] a;
input [5:0] dpra;
input [15:0] di;
output [15:0] spo;
output [15:0] dpo;
reg [15:0] ram [63:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_init_file.data deleted 100644 → 0
00001110110000011001111011000110
00101011001011010101001000100011
01110100010100011000011100001111
01000001010000100101001110010100
00001001101001111111101000101011
00101101001011111110101010100111
11101111000100111000111101101101
10001111010010011001000011101111
00000001100011100011110010011111
11011111001110101011111001001010
11100111010100111110110011001010
11000100001001101100111100101001
10001011100101011111111111100001
11110101110110010000010110111010
01001011000000111001010110101110
11100001111111001010111010011110
01101111011010010100001101110001
01010100011011111000011000100100
11110000111101101111001100001011
10101101001111010100100100011100
01011100001010111111101110101110
01011101000100100111010010110101
11110111000100000101011101101101
11100111110001111010101100001101
01110100000011101111111000011111
00010011110101111000111001011101
01101110001111100011010101101111
10111100000000010011101011011011
11000001001101001101111100010000
00011111110010110110011111010101
01100100100000011100100101110000
10001000000100111011001010001111
11001000100011101001010001100001
10000000100111010011100111100011
11011111010010100010101010000111
10000000110111101000111110111011
10110011010111101111000110011001
00010111100001001010110111011100
10011100101110101111011010110011
01010011101101010001110110011010
01111011011100010101000101000001
10001000000110010110111001101010
11101000001101010000111001010110
11100011111100000111110101110101
01001010000000001111111101101111
00100011000011001000000010001111
10011000111010110001001011100100
11111111111011110101000101000111
11000011000101000011100110100000
01101101001011111010100011101001
10000111101100101001110011010111
11010110100100101110110010100100
01001111111001101101011111001011
11011001001101110110000100110111
10110110110111100101110011100110
10011100111001000010111111010110
00000000001011011111001010110010
10100110011010000010001000011011
11001010111111001001110001110101
00100001100010000111000101001000
00111100101111110001101101111010
11000010001010000000010100100001
11000001000110001101000101001110
10010011010100010001100100100111
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_init_file.v deleted 100644 → 0
// Initializing Block RAM from external data file
// Binary data
// File: rams_init_file.v
module rams_init_file (clk, we, addr, din, dout);
input clk;
input we;
input [5:0] addr;
input [31:0] din;
output [31:0] dout;
reg [31:0] ram [0:63];
reg [31:0] dout;
initial begin
$readmemb("../rams_init_file.data",ram);
end
always @(posedge clk)
begin
if (we)
ram[addr] <= din;
dout <= ram[addr];
end endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_pipeline.v deleted 100644 → 0
// Block RAM with Optional Output Registers
// File: rams_pipeline
module rams_pipeline (clk1, clk2, we, en1, en2, addr1, addr2, di, res1, res2);
input clk1;
input clk2;
input we, en1, en2;
input [9:0] addr1;
input [9:0] addr2;
input [15:0] di;
output [15:0] res1;
output [15:0] res2;
reg [15:0] res1;
reg [15:0] res2;
reg [15:0] RAM [1023:0];
reg [15:0] do1;
reg [15:0] do2;
always @(posedge clk1)
begin
if (we == 1'b1)
RAM[addr1] <= di;
do1 <= RAM[addr1];
end
always @(posedge clk2)
begin
do2 <= RAM[addr2];
end
always @(posedge clk1)
begin
if (en1 == 1'b1)
res1 <= do1;
end
always @(posedge clk2)
begin
if (en2 == 1'b1)
res2 <= do2;
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_nc.v deleted 100644 → 0
// Single-Port Block RAM No-Change Mode
// File: rams_sp_nc.v
module rams_sp_nc (clk, we, en, addr, di, dout);
input clk;
input we;
input en;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] RAM [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr] <= di;
else
dout <= RAM[addr];
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rf.v deleted 100644 → 0
// Single-Port Block RAM Read-First Mode
// rams_sp_rf.v
module rams_sp_rf (clk, en, we, addr, di, dout);
input clk;
input we;
input en;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] RAM [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr]<=di;
dout <= RAM[addr];
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rf_rst.v deleted 100644 → 0
// Block RAM with Resettable Data Output
// File: rams_sp_rf_rst.v
module rams_sp_rf_rst (clk, en, we, rst, addr, di, dout);
input clk;
input en;
input we;
input rst;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] ram [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en) //optional enable
begin
if (we) //write enable
ram[addr] <= di;
if (rst) //optional reset
dout <= 0;
else
dout <= ram[addr];
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rom.v deleted 100644 → 0
// Initializing Block RAM (Single-Port Block RAM)
// File: rams_sp_rom
module rams_sp_rom (clk, we, addr, di, dout);
input clk;
input we;
input [5:0] addr;
input [19:0] di;
output [19:0] dout;
reg [19:0] ram [63:0];
reg [19:0] dout;
initial
begin
ram[63] = 20'h0200A; ram[62] = 20'h00300; ram[61] = 20'h08101;
ram[60] = 20'h04000; ram[59] = 20'h08601; ram[58] = 20'h0233A;
ram[57] = 20'h00300; ram[56] = 20'h08602; ram[55] = 20'h02310;
ram[54] = 20'h0203B; ram[53] = 20'h08300; ram[52] = 20'h04002;
ram[51] = 20'h08201; ram[50] = 20'h00500; ram[49] = 20'h04001;
ram[48] = 20'h02500; ram[47] = 20'h00340; ram[46] = 20'h00241;
ram[45] = 20'h04002; ram[44] = 20'h08300; ram[43] = 20'h08201;
ram[42] = 20'h00500; ram[41] = 20'h08101; ram[40] = 20'h00602;
ram[39] = 20'h04003; ram[38] = 20'h0241E; ram[37] = 20'h00301;
ram[36] = 20'h00102; ram[35] = 20'h02122; ram[34] = 20'h02021;
ram[33] = 20'h00301; ram[32] = 20'h00102; ram[31] = 20'h02222;
ram[30] = 20'h04001; ram[29] = 20'h00342; ram[28] = 20'h0232B;
ram[27] = 20'h00900; ram[26] = 20'h00302; ram[25] = 20'h00102;
ram[24] = 20'h04002; ram[23] = 20'h00900; ram[22] = 20'h08201;
ram[21] = 20'h02023; ram[20] = 20'h00303; ram[19] = 20'h02433;
ram[18] = 20'h00301; ram[17] = 20'h04004; ram[16] = 20'h00301;
ram[15] = 20'h00102; ram[14] = 20'h02137; ram[13] = 20'h02036;
ram[12] = 20'h00301; ram[11] = 20'h00102; ram[10] = 20'h02237;
ram[9] = 20'h04004; ram[8] = 20'h00304; ram[7] = 20'h04040;
ram[6] = 20'h02500; ram[5] = 20'h02500; ram[4] = 20'h02500;
ram[3] = 20'h0030D; ram[2] = 20'h02341; ram[1] = 20'h08201;
ram[0] = 20'h0400D;
end
always @(posedge clk)
begin
if (we)
ram[addr] <= di;
dout <= ram[addr];
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_rom_1.v deleted 100644 → 0
// ROMs Using Block RAM Resources.
// File: rams_sp_rom_1.v
//
module rams_sp_rom_1 (clk, en, addr, dout);
input clk;
input en;
input [5:0] addr;
output [19:0] dout;
(*rom_style = "block" *) reg [19:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
6'b000000: data <= 20'h0200A; 6'b100000: data <= 20'h02222;
6'b000001: data <= 20'h00300; 6'b100001: data <= 20'h04001;
6'b000010: data <= 20'h08101; 6'b100010: data <= 20'h00342;
6'b000011: data <= 20'h04000; 6'b100011: data <= 20'h0232B;
6'b000100: data <= 20'h08601; 6'b100100: data <= 20'h00900;
6'b000101: data <= 20'h0233A; 6'b100101: data <= 20'h00302;
6'b000110: data <= 20'h00300; 6'b100110: data <= 20'h00102;
6'b000111: data <= 20'h08602; 6'b100111: data <= 20'h04002;
6'b001000: data <= 20'h02310; 6'b101000: data <= 20'h00900;
6'b001001: data <= 20'h0203B; 6'b101001: data <= 20'h08201;
6'b001010: data <= 20'h08300; 6'b101010: data <= 20'h02023;
6'b001011: data <= 20'h04002; 6'b101011: data <= 20'h00303;
6'b001100: data <= 20'h08201; 6'b101100: data <= 20'h02433;
6'b001101: data <= 20'h00500; 6'b101101: data <= 20'h00301;
6'b001110: data <= 20'h04001; 6'b101110: data <= 20'h04004;
6'b001111: data <= 20'h02500; 6'b101111: data <= 20'h00301;
6'b010000: data <= 20'h00340; 6'b110000: data <= 20'h00102;
6'b010001: data <= 20'h00241; 6'b110001: data <= 20'h02137;
6'b010010: data <= 20'h04002; 6'b110010: data <= 20'h02036;
6'b010011: data <= 20'h08300; 6'b110011: data <= 20'h00301;
6'b010100: data <= 20'h08201; 6'b110100: data <= 20'h00102;
6'b010101: data <= 20'h00500; 6'b110101: data <= 20'h02237;
6'b010110: data <= 20'h08101; 6'b110110: data <= 20'h04004;
6'b010111: data <= 20'h00602; 6'b110111: data <= 20'h00304;
6'b011000: data <= 20'h04003; 6'b111000: data <= 20'h04040;
6'b011001: data <= 20'h0241E; 6'b111001: data <= 20'h02500;
6'b011010: data <= 20'h00301; 6'b111010: data <= 20'h02500;
6'b011011: data <= 20'h00102; 6'b111011: data <= 20'h02500;
6'b011100: data <= 20'h02122; 6'b111100: data <= 20'h0030D;
6'b011101: data <= 20'h02021; 6'b111101: data <= 20'h02341;
6'b011110: data <= 20'h00301; 6'b111110: data <= 20'h08201;
6'b011111: data <= 20'h00102; 6'b111111: data <= 20'h0400D;
endcase
end
assign dout = data;
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_sp_wf.v deleted 100644 → 0
// Single-Port Block RAM Write-First Mode (recommended template)
// File: rams_sp_wf.v
module rams_sp_wf (clk, we, en, addr, di, dout);
input clk;
input we;
input en;
input [9:0] addr;
input [15:0] di;
output [15:0] dout;
reg [15:0] RAM [1023:0];
reg [15:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
begin
RAM[addr] <= di;
dout <= di;
end
else
dout <= RAM[addr];
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/rams_tdp_rf_rf.v deleted 100644 → 0
// Dual-Port Block RAM with Two Write Ports
// File: rams_tdp_rf_rf.v
module rams_tdp_rf_rf (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
input clka,clkb,ena,enb,wea,web;
input [9:0] addra,addrb;
input [15:0] dia,dib;
output [15:0] doa,dob;
reg [15:0] ram [1023:0];
reg [15:0] doa,dob;
always @(posedge clka)
begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb)
begin
if (enb)
begin
if (web)
ram[addrb] <= dib;
dob <= ram[addrb];
end
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/registers_1.v deleted 100644 → 0
// 8-bit Register with
// Rising-edge Clock
// Active-high Synchronous Clear
// Active-high Clock Enable
// File: registers_1.v
module registers_1(d_in,ce,clk,clr,dout);
input [7:0] d_in;
input ce;
input clk;
input clr;
output [7:0] dout;
reg [7:0] d_reg;
always @ (posedge clk)
begin
if(clr)
d_reg <= 8'b0;
else if(ce)
d_reg <= d_in;
end
assign dout = d_reg;
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/sfir_shifter.v deleted 100644 → 0
//sfir_shifter.v
(* dont_touch = "yes" *)
module sfir_shifter #(parameter dsize = 16, nbtap = 4)
(input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout);
(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
integer i;
always @(posedge clk)
begin
tmp[0] <= datain;
for (i=0; i<=2*nbtap-2; i=i+1)
tmp[i+1] <= tmp[i];
end
assign dataout = tmp[2*nbtap-1];
endmodule
// sfir_shifter
architecture_reviewed/xilinx_ug901_synthesis_examples/shift_registers_0.v deleted 100644 → 0
// 8-bit Shift Register
// Rising edge clock
// Active high clock enable
// Concatenation-based template
// File: shift_registers_0.v
module shift_registers_0 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk)
begin
if (clken)
shreg = {shreg[WIDTH-2:0], SI};
end
assign SO = shreg[WIDTH-1];
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/shift_registers_1.v deleted 100644 → 0
// 32-bit Shift Register
// Rising edge clock
// Active high clock enable
// For-loop based template
// File: shift_registers_1.v
module shift_registers_1 (clk, clken, SI, SO);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
integer i;
always @(posedge clk)
begin
if (clken)
begin
for (i = 0; i < WIDTH-1; i = i+1)
shreg[i+1] <= shreg[i];
shreg[0] <= SI;
end
end
assign SO = shreg[WIDTH-1];
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/squarediffmacc.v deleted 100644 → 0
// This module performs subtraction of two inputs, squaring on the diff
// and then accumulation
// This can be implemented in 1 DSP Block (Ultrascale architecture)
// File : squarediffmacc.v
module squarediffmacc # (
//Default parameters were changed because of slow test
//parameter SIZEIN = 16,
//SIZEOUT = 40
parameter SIZEIN = 8,
SIZEOUT = 20
)
(
input clk,
input ce,
input sload,
input signed [SIZEIN-1:0] a,
input signed [SIZEIN-1:0] b,
output signed [SIZEOUT+1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg signed [SIZEIN:0] diff_reg;
reg sload_reg;
reg signed [2*SIZEIN+1:0] m_reg;
reg signed [SIZEOUT-1:0] adder_out, old_result;
always @(sload_reg or adder_out)
if (sload_reg)
old_result <= 0;
else
// 'sload' is now and opens the accumulation loop.
// The accumulator takes the next multiplier output
// in the same cycle.
old_result <= adder_out;
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
diff_reg <= a_reg - b_reg;
m_reg <= diff_reg * diff_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + m_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule // squarediffmacc
architecture_reviewed/xilinx_ug901_synthesis_examples/squarediffmult.v deleted 100644 → 0
// Squarer support for DSP block (DSP48E2) with
// pre-adder configured
// as subtractor
// File: squarediffmult.v
module squarediffmult # (parameter SIZEIN = 16)
(
input clk, ce, rst,
input signed [SIZEIN-1:0] a, b,
output signed [2*SIZEIN+1:0] square_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg, b_reg;
reg signed [SIZEIN:0] diff_reg;
reg signed [2*SIZEIN+1:0] m_reg, p_reg;
always @(posedge clk)
begin
if (rst)
begin
a_reg <= 0;
b_reg <= 0;
diff_reg <= 0;
m_reg <= 0;
p_reg <= 0;
end
else
if (ce)
begin
a_reg <= a;
b_reg <= b;
diff_reg <= a_reg - b_reg;
m_reg <= diff_reg * diff_reg;
p_reg <= m_reg;
end
end
// Output result
assign square_out = p_reg;
endmodule // squarediffmult
architecture_reviewed/xilinx_ug901_synthesis_examples/top_mux.v deleted 100644 → 0
// Multiplexer using case statement
module mux4 (sel, a, b, c, d, outmux);
input [1:0] sel;
input [1:0] a, b, c, d;
output [1:0] outmux;
reg [1:0] outmux;
always @ *
begin
case(sel)
2'b00 : outmux = a;
2'b01 : outmux = b;
2'b10 : outmux = c;
2'b11 : outmux = d;
endcase
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/tristates_1.v deleted 100644 → 0
// Tristate Description Using Combinatorial Always Block
// File: tristates_1.v
//
module tristates_1 (T, I, O);
input T, I;
output O;
reg O;
always @(T or I)
begin
if (~T)
O = I;
else
O = 1'bZ;
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/tristates_2.v deleted 100644 → 0
// Tristate Description Using Concurrent Assignment
// File: tristates_2.v
//
module tristates_2 (T, I, O);
input T, I;
output O;
assign O = (~T) ? I: 1'bZ;
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_read_wider.ys deleted 100644 → 0
read_verilog ../asym_ram_sdp_read_wider.v
hierarchy -top asym_ram_sdp_read_wider
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_sdp_read_wider
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 4 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys deleted 100644 → 0
read_verilog ../asym_ram_sdp_write_wider.v
hierarchy -top asym_ram_sdp_write_wider
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_sdp_write_wider
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 9 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 6 t:LUT3
select -assert-count 8 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:RAM128X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_read_first.ys deleted 100644 → 0
read_verilog ../asym_ram_tdp_read_first.v
hierarchy -top asym_ram_tdp_read_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_tdp_read_first
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:LUT2
select -assert-none t:$mem t:LUT2 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_tdp_write_first.ys deleted 100644 → 0
read_verilog ../asym_ram_tdp_write_first.v
hierarchy -top asym_ram_tdp_write_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_tdp_write_first
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 200 t:FDRE
select -assert-count 10 t:LUT2
select -assert-count 44 t:LUT3
select -assert-count 81 t:LUT4
select -assert-count 104 t:LUT5
select -assert-count 560 t:LUT6
select -assert-count 261 t:MUXF7
select -assert-count 127 t:MUXF8
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_black_box_1.ys deleted 100644 → 0
read_verilog ../black_box_1.v
hierarchy -top black_box_1
proc
tribuf
flatten
synth
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd black_box_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 black box.
#stat
#select -assert-count 0 t:LUT1
#select -assert-count 1 t:$_TBUF_
#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_ram_1b.ys deleted 100644 → 0
read_verilog ../bytewrite_ram_1b.v
hierarchy -top bytewrite_ram_1b
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_ram_1b
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 32 t:LUT2
select -assert-count 32 t:RAM32X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:RAM32X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_nc.ys deleted 100644 → 0
read_verilog ../bytewrite_tdp_ram_nc.v
hierarchy -top bytewrite_tdp_ram_nc
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_nc
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 8 t:LUT2
select -assert-count 64 t:LUT3
select -assert-count 2 t:LUT5
select -assert-none t:LUT2 t:LUT3 t:LUT5 t:$mem %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_readfirst2.ys deleted 100644 → 0
read_verilog ../bytewrite_tdp_ram_readfirst2.v
hierarchy -top bytewrite_tdp_ram_readfirst2
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_readfirst2
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 8 t:LUT2
select -assert-count 64 t:LUT3
select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_rf.ys deleted 100644 → 0
read_verilog ../bytewrite_tdp_ram_rf.v
hierarchy -top bytewrite_tdp_ram_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_rf
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 8 t:LUT2
select -assert-count 64 t:LUT3
select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_tdp_ram_wf.ys deleted 100644 → 0
read_verilog ../bytewrite_tdp_ram_wf.v
hierarchy -top bytewrite_tdp_ram_wf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd bytewrite_tdp_ram_wf
stat
#Vivado synthesizes 1 RAMB36E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:BUFG
select -assert-count 64 t:FDRE
select -assert-count 8 t:LUT2
select -assert-count 128 t:LUT3
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:$mem %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_cmacc.ys deleted 100644 → 0
read_verilog ../cmacc.v
hierarchy -top cmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd cmacc
#Vivado synthesizes 5 DSP48E1, 32 FDRE, 18 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 65 t:FDRE
select -assert-count 3 t:DSP48E1
select -assert-count 18 t:LUT2
select -assert-count 34 t:LUT3
select -assert-count 25 t:MUXCY
select -assert-count 29 t:XORCY
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:LUT3 t:MUXCY t:XORCY %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_cmult.ys deleted 100644 → 0
read_verilog ../cmult.v
hierarchy -top cmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd cmult
#Vivado synthesizes 3 DSP48E1, 68 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 86 t:FDRE
select -assert-count 3 t:DSP48E1
select -assert-count 34 t:LUT2
select -assert-count 17 t:MUXCY
select -assert-count 19 t:XORCY
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_dynamic_shift_registers_1.ys deleted 100644 → 0
read_verilog ../dynamic_shift_registers_1.v
hierarchy -top dynamic_shift_register_1
proc
flatten
#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dynamic_shift_register_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 3 SRLC32E.
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_dynpreaddmultadd.ys deleted 100644 → 0
read_verilog ../dynpreaddmultadd.v
hierarchy -top dynpreaddmultadd
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd dynpreaddmultadd
#Vivado synthesizes 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 24 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-count 8 t:LUT1
select -assert-count 17 t:LUT2
select -assert-count 25 t:LUT4
select -assert-count 16 t:MUXCY
select -assert-count 18 t:XORCY
select -assert-none t:BUFG t:FDRE t:DSP48E1 t:LUT1 t:LUT2 t:LUT4 t:MUXCY t:XORCY %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_fsm_1.ys deleted 100644 → 0
read_verilog ../fsm_1.v
hierarchy -top fsm_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE.
stat
select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE
select -assert-count 2 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_latches.ys deleted 100644 → 0
read_verilog ../latches.v
proc
hierarchy -top latches
flatten
synth_xilinx
#Vivado synthesizes 1 BUFG, 8 LDCE.
select -assert-count 2 t:LUT2
select -assert-count 1 t:LDCE
#select -assert-none t:LUT2 t:LDCE %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_macc.ys deleted 100644 → 0
read_verilog ../macc.v
hierarchy -top macc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc
#Vivado synthesizes 1 DSP48E1, 1 FDRE. (When SIZEIN = 12, SIZEOUT = 30)
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_mult_unsigned.ys deleted 100644 → 0
read_verilog ../mult_unsigned.v
hierarchy -top mult_unsigned
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd mult_unsigned
#Vivado synthesizes 1 DSP48E1, 40 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 40 t:FDRE
select -assert-count 1 t:DSP48E1
select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_presubmult.ys deleted 100644 → 0
read_verilog ../presubmult.v
hierarchy -top presubmult
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd presubmult
#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_one_clock.ys deleted 100644 → 0
read_verilog ../ram_simple_dual_one_clock.v
hierarchy -top simple_dual_one_clock
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_one_clock
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_two_clocks.ys deleted 100644 → 0
read_verilog ../ram_simple_dual_two_clocks.v
hierarchy -top simple_dual_two_clocks
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_two_clocks
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_dist.ys deleted 100644 → 0
read_verilog ../rams_dist.v
hierarchy -top rams_dist
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_dist
stat
#Vivado synthesizes 32 RAM64X1D.
select -assert-count 1 t:BUFG
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:RAM64X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys deleted 100644 → 0
read_verilog ../rams_init_file.v
hierarchy -top rams_init_file
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_init_file
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys deleted 100644 → 0
read_verilog ../rams_pipeline.v
hierarchy -top rams_pipeline
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_pipeline
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 2 t:RAMB18E1
select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_nc.ys deleted 100644 → 0
read_verilog ../rams_sp_nc.v
hierarchy -top rams_sp_nc
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_nc
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 2 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf.ys deleted 100644 → 0
read_verilog ../rams_sp_rf.v
hierarchy -top rams_sp_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys deleted 100644 → 0
read_verilog ../rams_sp_rf_rst.v
hierarchy -top rams_sp_rf_rst
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf_rst
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 5 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 13 t:LUT4
select -assert-count 23 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys deleted 100644 → 0
read_verilog ../rams_sp_rom.v
hierarchy -top rams_sp_rom
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 20 t:RAM64X1D
select -assert-count 20 t:FDRE
select -assert-none t:BUFG t:RAM64X1D t:FDRE %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom_1.ys deleted 100644 → 0
read_verilog ../rams_sp_rom_1.v
hierarchy -top rams_sp_rom_1
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom_1
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 14 t:LUT6
select -assert-count 14 t:FDRE
select -assert-none t:BUFG t:LUT6 t:FDRE %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys deleted 100644 → 0
read_verilog ../rams_sp_wf.v
hierarchy -top rams_sp_wf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_wf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 44 t:LUT5
select -assert-count 38 t:LUT6
select -assert-count 10 t:MUXF7
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_tdp_rf_rf.ys deleted 100644 → 0
read_verilog ../rams_tdp_rf_rf.v
hierarchy -top rams_tdp_rf_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_tdp_rf_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:LUT2
select -assert-none t:$mem t:LUT2 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys deleted 100644 → 0
read_verilog ../registers_1.v
hierarchy -top registers_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 8 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 9 t:LUT2
select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_sfir_shifter.ys deleted 100644 → 0
read_verilog ../sfir_shifter.v
hierarchy -top sfir_shifter
proc
flatten
#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd sfir_shifter
#Vivado synthesizes 32 FDRE, 16 SRL16E.
stat
select -assert-count 1 t:BUFG
select -assert-count 16 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_0.ys deleted 100644 → 0
read_verilog ../shift_registers_0.v
hierarchy -top shift_registers_0
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_0 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_1.ys deleted 100644 → 0
read_verilog ../shift_registers_1.v
hierarchy -top shift_registers_1
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmacc.ys deleted 100644 → 0
read_verilog ../squarediffmacc.v
hierarchy -top squarediffmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd squarediffmacc
#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 17 t:FDRE
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys deleted 100644 → 0
read_verilog ../squarediffmult.v
hierarchy -top squarediffmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd squarediffmult
stat
#Vivado synthesizes 16 FDRE, 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 32 t:FDRE
select -assert-count 65 t:LUT2
select -assert-count 16 t:MUXCY
select -assert-count 17 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_top_mux.ys deleted 100644 → 0
read_verilog ../top_mux.v
hierarchy -top mux4
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4
#Vivado synthesizes 2 LUT.
stat
select -assert-count 2 t:LUT6
select -assert-none t:LUT6 %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys deleted 100644 → 0
read_verilog ../tristates_1.v
hierarchy -top tristates_1
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys deleted 100644 → 0
read_verilog ../tristates_2.v
hierarchy -top tristates_2
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_2 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys deleted 100644 → 0
read_verilog ../xilinx_ultraram_single_port_no_change.v
hierarchy -top xilinx_ultraram_single_port_no_change
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_no_change
stat
#Vivado synthesizes 1 RAMB36E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 9 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys deleted 100644 → 0
read_verilog ../xilinx_ultraram_single_port_read_first.v
hierarchy -top xilinx_ultraram_single_port_read_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_read_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 8 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys deleted 100644 → 0
read_verilog ../xilinx_ultraram_single_port_write_first.v
hierarchy -top xilinx_ultraram_single_port_write_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_write_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 44 t:FDRE
select -assert-count 8 t:LUT5
select -assert-count 8 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_no_change.v deleted 100644 → 0
// Xilinx UltraRAM Single Port No Change Mode. This code implements
// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is
// when data is written, the output of RAM is unchanged. Only when write is
// inactive data corresponding to the address is presented on the output port.
//
module xilinx_ultraram_single_port_no_change #(
//Default parameters were changed because of slow test
//parameter AWIDTH = 12, // Address Width
//parameter DWIDTH = 72, // Data Width
//parameter NBPIPE = 3 // Number of pipeline Registers
parameter AWIDTH = 8, // Address Width
parameter DWIDTH = 8, // Data Width
parameter NBPIPE = 3 // Number of pipeline Registers
) (
input clk, // Clock
input rst, // Reset
input we, // Write Enable
input regce, // Output Register Enable
input mem_en, // Memory Enable
input [DWIDTH-1:0] din, // Data Input
input [AWIDTH-1:0] addr, // Address Input
output reg [DWIDTH-1:0] dout // Data Output
);
(* ram_style = "ultra" *)
reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0]; // Memory Declaration
reg [DWIDTH-1:0] memreg;
reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0]; // Pipelines for memory
reg mem_en_pipe_reg[NBPIPE:0]; // Pipelines for memory enable
integer i;
// RAM : Read has one latency, Write has one latency as well.
always @ (posedge clk)
begin
if(mem_en)
begin
if(we)
mem[addr] <= din;
else
memreg <= mem[addr];
end
end
// The enable of the RAM goes through a pipeline to produce a
// series of pipelined enable signals required to control the data
// pipeline.
always @ (posedge clk)
begin
mem_en_pipe_reg[0] <= mem_en;
for (i=0; i<NBPIPE; i=i+1)
mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end
// RAM output data goes through a pipeline.
always @ (posedge clk)
begin
if (mem_en_pipe_reg[0])
mem_pipe_reg[0] <= memreg;
end
always @ (posedge clk)
begin
for (i = 0; i < NBPIPE-1; i = i+1)
if (mem_en_pipe_reg[i+1])
mem_pipe_reg[i+1] <= mem_pipe_reg[i];
end
// Final output register gives user the option to add a reset and
// an additional enable signal just for the data ouptut
always @ (posedge clk)
begin
if (rst)
dout <= 0;
else if (mem_en_pipe_reg[NBPIPE] && regce)
dout <= mem_pipe_reg[NBPIPE-1];
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_read_first.v deleted 100644 → 0
// Xilinx UltraRAM Single Port Read First Mode. This code implements
// a parameterizable UltraRAM block in read first mode. The behavior of this RAM is
// when data is written, the old memory contents at the write address are
// presented on the output port.
//
module xilinx_ultraram_single_port_read_first #(
//Default parameters were changed because of slow test
//parameter AWIDTH = 12, // Address Width
//parameter DWIDTH = 72, // Data Width
//parameter NBPIPE = 3 // Number of pipeline Registers
parameter AWIDTH = 8, // Address Width
parameter DWIDTH = 8, // Data Width
parameter NBPIPE = 3 // Number of pipeline Registers
) (
input clk, // Clock
input rst, // Reset
input we, // Write Enable
input regce, // Output Register Enable
input mem_en, // Memory Enable
input [DWIDTH-1:0] din, // Data Input
input [AWIDTH-1:0] addr, // Address Input
output reg [DWIDTH-1:0] dout // Data Output
);
(* ram_style = "ultra" *)
reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0]; // Memory Declaration
reg [DWIDTH-1:0] memreg;
reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0]; // Pipelines for memory
reg mem_en_pipe_reg[NBPIPE:0]; // Pipelines for memory enable
integer i;
// RAM : Both READ and WRITE have a latency of one
always @ (posedge clk)
begin
if(mem_en)
begin
if(we)
mem[addr] <= din;
memreg <= mem[addr];
end
end
// The enable of the RAM goes through a pipeline to produce a
// series of pipelined enable signals required to control the data
// pipeline.
always @ (posedge clk)
begin
mem_en_pipe_reg[0] <= mem_en;
for (i=0; i<NBPIPE; i=i+1)
mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end
// RAM output data goes through a pipeline.
always @ (posedge clk)
begin
if (mem_en_pipe_reg[0])
mem_pipe_reg[0] <= memreg;
end
always @ (posedge clk)
begin
for (i = 0; i < NBPIPE-1; i = i+1)
if (mem_en_pipe_reg[i+1])
mem_pipe_reg[i+1] <= mem_pipe_reg[i];
end
// Final output register gives user the option to add a reset and
// an additional enable signal just for the data ouptut
always @ (posedge clk)
begin
if (rst)
dout <= 0;
else if (mem_en_pipe_reg[NBPIPE] && regce)
dout <= mem_pipe_reg[NBPIPE-1];
end
endmodule
architecture_reviewed/xilinx_ug901_synthesis_examples/xilinx_ultraram_single_port_write_first.v deleted 100644 → 0
// Xilinx UltraRAM Single Port Write First Mode. This code implements
// a parameterizable UltraRAM block in write first mode. The behavior of this RAM is
// when data is written, the new memory contents at the write address are
// presented on the output port.
//
module xilinx_ultraram_single_port_write_first #(
//Default parameters were changed because of slow test
//parameter AWIDTH = 12, // Address Width
//parameter DWIDTH = 72, // Data Width
//parameter NBPIPE = 3 // Number of pipeline Registers
parameter AWIDTH = 8, // Address Width
parameter DWIDTH = 8, // Data Width
parameter NBPIPE = 3 // Number of pipeline Registers
) (
input clk, // Clock
input rst, // Reset
input we, // Write Enable
input regce, // Output Register Enable
input mem_en, // Memory Enable
input [DWIDTH-1:0] din, // Data Input
input [AWIDTH-1:0] addr, // Address Input
output reg [DWIDTH-1:0] dout // Data Output
);
(* ram_style = "ultra" *)
reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0]; // Memory Declaration
reg [DWIDTH-1:0] memreg;
reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0]; // Pipelines for memory
reg mem_en_pipe_reg[NBPIPE:0]; // Pipelines for memory enable
integer i;
// RAM : Both READ and WRITE have a latency of one
always @ (posedge clk)
begin
if(mem_en)
begin
if(we)
begin
mem[addr] <= din;
memreg <= din;
end
else
memreg <= mem[addr];
end
end
// The enable of the RAM goes through a pipeline to produce a
// series of pipelined enable signals required to control the data
// pipeline.
always @ (posedge clk)
begin
mem_en_pipe_reg[0] <= mem_en;
for (i=0; i<NBPIPE; i=i+1)
mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end
// RAM output data goes through a pipeline.
always @ (posedge clk)
begin
if (mem_en_pipe_reg[0])
mem_pipe_reg[0] <= memreg;
end
always @ (posedge clk)
begin
for (i = 0; i < NBPIPE-1; i = i+1)
if (mem_en_pipe_reg[i+1])
mem_pipe_reg[i+1] <= mem_pipe_reg[i];
end
// Final output register gives user the option to add a reset and
// an additional enable signal just for the data ouptut
always @ (posedge clk)
begin
if (rst)
dout <= 0;
else if (mem_en_pipe_reg[NBPIPE] && regce)
dout <= mem_pipe_reg[NBPIPE-1];
end
endmodule
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