Fix opt_dff fallout.

parent 23a7806d
......@@ -15,6 +15,5 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_SEQ %% t:* %D
......@@ -15,6 +15,5 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_SEQ %% t:* %D
......@@ -15,6 +15,5 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_SEQ %% t:* %D
......@@ -15,6 +15,5 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_SEQ %% t:* %D
......@@ -15,6 +15,5 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_SEQ %% t:* %D
......@@ -15,6 +15,5 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_SEQ %% t:* %D
......@@ -15,6 +15,5 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_SEQ %% t:* %D
......@@ -35,8 +35,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
design -load postopt
cd top
stat
select -assert-count 143 t:LUT4
select -assert-count 16 t:PFUMX
select -assert-count 32 t:TRELLIS_DPR16X4
select -assert-count 143 t:TRELLIS_FF
select -assert-max 145 t:LUT4
select -assert-max 20 t:PFUMX
select -assert-max 32 t:TRELLIS_DPR16X4
select -assert-max 143 t:TRELLIS_FF
select -assert-none t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
......@@ -20,5 +20,4 @@ cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
......@@ -20,5 +20,4 @@ cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
......@@ -20,5 +20,4 @@ cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
......@@ -20,5 +20,4 @@ cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
......@@ -20,5 +20,4 @@ cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
......@@ -20,5 +20,4 @@ cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
......@@ -20,5 +20,4 @@ cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
......@@ -35,5 +35,5 @@ synth_intel -nobram
#design -load postopt
cd top
select -assert-count 520 t:dffeas
select -assert-count 978 t:fiftyfivenm_lcell_comb
select -assert-count 464 t:fiftyfivenm_lcell_comb
select -assert-none t:dffeas t:fiftyfivenm_lcell_comb %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -24,9 +24,8 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
......@@ -16,10 +16,10 @@ cd xilinx_ultraram_single_port_no_change
stat
#Vivado synthesizes 1 RAMB36E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 60 t:FDRE
select -assert-count 1 t:LUT2
select -assert-count 53 t:FDRE
select -assert-count 2 t:LUT2
select -assert-count 10 t:LUT3
select -assert-count 24 t:LUT4
select -assert-count 1 t:LUT4
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D %% t:* %D
......@@ -13,12 +13,12 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
design -load postopt
cd xilinx_ultraram_single_port_read_first
stat
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 60 t:FDRE
select -assert-count 53 t:FDRE
select -assert-count 1 t:INV
select -assert-count 1 t:LUT2
select -assert-count 34 t:LUT3
select -assert-count 10 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
select -assert-none t:BUFG t:FDRE t:INV t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
read_verilog ../top.v
proc
tribuf
dff2dffe
write_verilog result.out
read_verilog ../top_concat.v
proc
tribuf
dff2dffe
write_verilog result.out
read_verilog ../top_concat_signed.v
proc
tribuf
dff2dffe
write_verilog result.out
read_verilog ../top_ffs.v
proc
tribuf
dff2dffe
write_verilog result.out
read_verilog ../top_latch.v
proc
tribuf
dff2dffe
write_verilog result.out
read_verilog ../top.v
proc
tribuf
dff2dffe
write_verilog -nostr result.out
read_verilog ../top_shiftx.v
proc
tribuf
dff2dffe
write_verilog result.out
read_verilog ../top.v
proc
tribuf
dff2dffe
write_verilog -siminit result.out
read_verilog ../top_tri.v
proc
tribuf
dff2dffe
write_verilog result.out
read_verilog ../top.v
proc
dff2dffe
write_verilog -v result.out
read_verilog ../top_and_or.v
synth -top top
dffunmap
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 1 t:$dff
select -assert-count 11 t:$lut
select -assert-count 10 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$sop
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$sop %% t:* %D
read_verilog ../top_mem.v
synth -top top
dffunmap
write_blif blif1.blif
design -reset
read_blif -wideports blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-max 528 t:$dff
select -assert-max 2438 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc
......
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.out abc -D 2
read_verilog ../top_dff.v
synth -top top
dff2dffe
tee -o result.log abc -dff
abc -dff
abc -dff
read_verilog ../top_div_mul.v
proc
dff2dffe
synth -top top
tee -o result.out abc
read_verilog ../top_dff.v
proc
dff2dffe
synth -top top
tee -o result.out abc
read_verilog ../top_dff.v
proc
dff2dffe
synth -top top
tee -o result.out abc -clk clk
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc -g simple
......
read_verilog ../top_dff.v
proc
dff2dffe
synth -top top
tee -o result.out abc -markgroups
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -D 2 -lut 2
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -W -lut 2
read_verilog ../top_dff.v
proc
dff2dffe
synth -top top
abc9 -lut 5
abc9 -lut 5
read_verilog ../top_dff.v
proc
dff2dffe
techmap
abc9 -lut 5
abc9 -lut 5
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -fast -lut 2
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -lut 2
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -luts 2,3,4
read_verilog ../top_mem.v
proc
dff2dffe
synth -top top
abc9 -D 2 -lut 2
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -nocleanup -lut 2
read_verilog ../top.v
proc
dff2dffe
synth -top top
abc9 -showtmp -lut 2
......@@ -4,6 +4,6 @@ read_verilog ../demux.v
read_verilog ../mux.v
prep -flatten
opt_rmdff -sat
opt_dff -sat
synth
tee -o result.log select -assert-count 0 t:$_DFF_P_
read_verilog top.v
prep -top picorv32 -nordff
opt -fast
dffunmap
write_smt2 picorv32.smt2
!rm picorv32.smt2
read_verilog top.v
proc
dff2dffe
simplemap
opt
opt_rmdff
select -assert-count 1 t:$_DFF_N_
select -assert-none t:$_DFF_N_ %% t:* %D
ERROR: No cell types matched pattern '$ff'.
read_verilog ../top.v
proc
dff2dffe -direct-match $ff
read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap
select -assert-none t:$dffe
dump
synth -top top
dff2dffe
dff2dffe -unmap
select -assert-none t:$dffe
flatten
opt
opt_rmdff
read_verilog ../top.v
proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
dump
synth -top top
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
select -assert-none t:$_DFFE_PP_
flatten
opt
opt_rmdff
read_verilog ../top.v
proc
synth -top top
dff2dffe -direct-match $_DFF_P_
dff2dffe -unmap
select -assert-none t:$dffe
flatten
opt
opt_rmdff
read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap-mince 2
select -assert-none t:$dffe
dump
synth -top top
dff2dffe
dff2dffe -unmap-mince 2
select -assert-none t:$dffe
flatten
opt
opt_rmdff
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
......@@ -2,6 +2,6 @@ read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs
opt_dff
select -assert-none t:$_DFF_N_
tee -o result.out stat
read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs -match-init
tee -o result.out stat
......@@ -3,6 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -cut
......@@ -3,6 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
......@@ -3,6 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
......@@ -3,6 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
......@@ -6,6 +6,5 @@ proc
expose -evert
flatten
opt
opt_rmdff
expose -evert
......@@ -6,6 +6,5 @@ expose -evert-dff
proc
flatten
opt
opt_rmdff
expose -evert-dff
......@@ -5,5 +5,4 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -evert-dff
......@@ -3,7 +3,6 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -evert -shared
expose -shared -evert
......@@ -4,5 +4,4 @@ expose -input
proc
flatten
opt
opt_rmdff
expose -input
......@@ -3,6 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -sep |
......@@ -3,6 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff
expose -shared
......@@ -3,10 +3,14 @@ proc
fsm_detect
fsm_extract
opt
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -3,10 +3,13 @@ proc
fsm_detect
fsm_extract
opt -fast
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 9 t:$mux
select -assert-count 5 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 5 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -4,10 +4,13 @@ fsm_detect
fsm_extract
opt -fine
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -4,11 +4,13 @@ fsm_detect
fsm_extract
opt -full
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 5 t:$mux
select -assert-count 2 t:$or
select -assert-count 1 t:$pmux
select -assert-count 3 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 1 t:$reduce_and
select -assert-count 2 t:$or
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$or t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:$or t:fsm %% t:* %D
......@@ -4,10 +4,13 @@ fsm_detect
fsm_extract
opt -keepdc
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -4,11 +4,14 @@ fsm_detect
fsm_extract
opt -mux_bool
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 5 t:$mux
select -assert-count 2 t:$or
select -assert-count 2 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 3 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 1 t:$reduce_and
select -assert-count 2 t:$or
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$or t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:$or t:fsm %% t:* %D
......@@ -4,10 +4,13 @@ fsm_detect
fsm_extract
opt -mux_undef
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 7 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 1 t:$mux
select -assert-count 2 t:$ne
select -assert-count 2 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:$not
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$ne t:$reduce_bool t:$reduce_and t:$not t:fsm %% t:* %D
......@@ -3,10 +3,14 @@ proc
fsm_detect
fsm_extract
opt -noclkinv
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -3,10 +3,14 @@ proc
fsm_detect
fsm_extract
opt -purge
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -4,10 +4,13 @@ fsm_detect
fsm_extract
opt -sat
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -3,10 +3,14 @@ proc
fsm_detect
fsm_extract
opt -share_all
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -3,10 +3,13 @@ proc
fsm_detect
fsm_extract
opt -undriven
select -assert-count 1 t:$dff
select -assert-count 2 t:$sdffe
select -assert-count 1 t:$fsm
select -assert-count 8 t:$mux
select -assert-count 4 t:$mux
select -assert-count 1 t:$pmux
select -assert-count 2 t:$ne
select -assert-count 1 t:$reduce_bool
select -assert-count 2 t:$reduce_and
select -assert-count 1 t:fsm
select -assert-none t:$dff t:$fsm t:$mux t:$pmux t:fsm %% t:* %D
select -assert-none t:$sdffe t:$fsm t:$mux t:$pmux t:$ne t:$reduce_bool t:$reduce_and t:fsm %% t:* %D
......@@ -7,10 +7,10 @@ proc_dff
proc_clean
opt_clean
opt_merge
opt_rmdff
opt_dff
opt_clean
opt_expr
opt_rmdff
opt_dff
memory
synth -top top
......@@ -7,10 +7,10 @@ proc_dff
proc_clean
opt_clean
opt_merge -nomux
opt_rmdff
opt_dff
opt_clean
opt_expr
opt_rmdff
opt_dff
memory
synth -top top
......@@ -7,10 +7,10 @@ proc_dff
proc_clean
opt_clean
opt_merge -share_all
opt_rmdff
opt_dff
opt_clean
opt_expr
opt_rmdff
opt_dff
memory
synth -top top
......@@ -7,10 +7,10 @@ proc_dff
proc_clean
opt_clean
opt_merge -share_all
opt_rmdff
opt_dff
opt_clean
opt_expr
opt_rmdff
opt_dff
memory
synth -top top
read_verilog ../top.v
proc
opt
opt_rmdff
synth -top top
proc
flatten
opt
opt_rmdff
read_verilog ../top_async.v
proc
dff2dffe
#opt
opt_rmdff
opt_dff
synth -top top
proc
flatten
#opt
opt_rmdff
opt_dff
......@@ -2,10 +2,10 @@ read_verilog ../top_async.v
proc
clk2fflogic
#opt
opt_rmdff
opt_dff
synth -top top
proc
flatten
#opt
opt_rmdff
opt_dff
......@@ -3,5 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff -keepdc
opt_dff -keepdc
......@@ -3,5 +3,5 @@ synth -top top
proc
flatten
opt
opt_rmdff -sat
opt_dff -sat
......@@ -3,5 +3,4 @@ synth -top top
proc
flatten
opt
opt_rmdff
......@@ -3,5 +3,4 @@ synth -top top
proc
flatten
opt
opt_rmdff
......@@ -3,5 +3,4 @@ synth -top top
proc
flatten
opt
opt_rmdff
......@@ -3,5 +3,4 @@ synth -top top
proc
flatten
opt
opt_rmdff
......@@ -3,5 +3,4 @@ synth -top top
proc
flatten
opt
opt_rmdff
......@@ -3,5 +3,4 @@ synth -top top
proc
flatten
opt
opt_rmdff
read_verilog ../top.v
prep
dff2dffe
simplemap top
synth
read_verilog ../top_mem_slice_concat.v
prep
dff2dffe
simplemap top
synth
read_verilog ../top.v
proc
dff2dffe
techmap -assert -map +/techmap.v +/simlib.v
synth
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
proc; opt; memory; wreduce; clean; opt
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
proc; opt; memory; wreduce; clean; opt
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
proc; opt; memory; wreduce -keepdc; clean; opt
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
proc; opt; memory; wreduce -keepdc; clean; opt
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
proc; opt; memory; wreduce -keepdc; clean; opt
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
proc; opt; memory; wreduce -keepdc; clean; opt
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -keepdc; clean; opt
proc; opt; memory; wreduce -keepdc; clean; opt
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
proc; opt; memory; wreduce; clean; opt
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
proc; opt; memory; wreduce -memx; clean; opt
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
proc; opt; memory; wreduce -memx; clean; opt
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
proc; opt; memory; wreduce -memx -keepdc; clean; opt
read_verilog ../top_div.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
proc; opt; memory; wreduce -memx -keepdc; clean; opt
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
proc; opt; memory; wreduce -memx -keepdc; clean; opt
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
proc; opt; memory; wreduce -memx -keepdc; clean; opt
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx -keepdc; clean; opt
proc; opt; memory; wreduce -memx -keepdc; clean; opt
read_verilog ../top_mem.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
proc; opt; memory; wreduce -memx; clean; opt
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
proc; opt; memory; wreduce -memx; clean; opt
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce -memx; clean; opt
proc; opt; memory; wreduce -memx; clean; opt
read_verilog ../top_mul.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
proc; opt; memory; wreduce; clean; opt
read_verilog ../top_reduce.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
proc; opt; memory; wreduce; clean; opt
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