Merge branch 'master' into xc7srl_cleanup

architecture/Makefile

@@ -71,6 +71,7 @@ $(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_b
 $(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
 ifeq ($(ENABLE_HEAVY_TESTS),1)
 $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
+$(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
 endif
 
 #greenpak4

architecture/run.sh

@@ -2,7 +2,6 @@
 
 set -x
 test -d $1
-test -f scripts/$2.ys
 
 rm -rf $1/work_$2
 mkdir $1/work_$2
@@ -25,7 +24,6 @@ if echo "$1" | grep ".*_error"; then
 		expected_string="ERROR: Invalid Xilinx -family setting: "
 	fi
 
-
 	if yosys -ql yosys.log ../../scripts/$2.ys; then
 		echo FAIL > ${1}_${2}.status
 	else
@@ -41,10 +39,13 @@ else
 		../run-test.sh
 		if [ $? != 0 ] ; then
 			echo FAIL > ${1}_${2}.status
+		else
+			echo PASS > ${1}_${2}.status
 		fi
 		touch .stamp
-		exit 0
+		exit
 	else
+		test -f scripts/$2.ys
 		yosys -ql yosys.log ../../scripts/$2.ys
 		if [ $? != 0 ] ; then
 			echo FAIL > ${1}_${2}.status

architecture/synth_xilinx_mux/assert_area.py

+#!/usr/bin/python3
+
+import glob
+import re
+import os
+
+re_mux = re.compile(r'mux_(index|case|if_bal|if_unbal)_(\d+)_(\d+)\.v')
+
+area = {}
+#             1  2  3  4  5  6 F7 F8
+area[2]   = [ 0, 0, 1, 0, 0, 0, 0, 0 ]
+area[3]   = [ 0, 0, 0, 0, 1, 0, 0, 0 ]
+area[4]   = [ 0, 0, 0, 0, 0, 0, 2, 1 ]
+area[5]   = [ 0, 0, 1, 0, 0, 0, 2, 1 ]
+area[7]   = [ 0, 0, 3, 0, 0, 0, 2, 1 ]
+area[8]   = [ 0, 0, 4, 0, 0, 0, 2, 1 ]
+area[9]   = [ 0, 0, 3, 0, 1, 0, 2, 1 ]
+area[15]  = [ 0, 0, 0, 0, 1, 3, 2, 1 ]
+area[16]  = [ 0, 0, 0, 0, 0, 4, 2, 1 ]
+area[17]  = [ 0, 0, 1, 0, 0, 4, 2, 1 ]
+area[31]  = [ 0, 0, 1, 0, 1, 7, 4, 2 ]
+area[32]  = [ 0, 0, 1, 0, 0, 8, 4, 2 ]
+area[33]  = [ 0, 0, 0, 0, 1, 8, 4, 2 ]
+area[63]  = [ 0, 0, 0, 0, 1,15,10, 5 ]
+area[64]  = [ 0, 0, 0, 0, 0,16,10, 5 ]
+area[65]  = [ 0, 0, 1, 0, 0,16,10, 5 ]
+area[127] = [ 0, 0, 4, 0, 1,31,18, 9 ]
+area[128] = [ 0, 0, 4, 0, 0,32,18, 9 ]
+area[129] = [ 0, 0, 3, 0, 1,32,18, 9 ]
+area[255] = [ 0, 0, 0, 0, 1,67,34,17 ]
+area[256] = [ 0, 0, 0, 0, 0,68,34,17 ]
+area[257] = [ 0, 0, 1, 0, 0,68,34,17 ]
+
+for fn in glob.glob('*.v'):
+    m = re_mux.match(fn)
+    if not m: continue
+
+    N,W = map(int, m.group(2,3))
+    assert N in area
+
+    bn,_ = os.path.splitext(fn)
+
+    with open(fn, 'a') as f:
+        assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
+        print('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd; %s";
+endmodule
+`endif
+''' % '; '.join(assert_area), file=f)

architecture/synth_xilinx_mux/run-test.sh

+#!/bin/bash
+set -e
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/generate.py -O generate_small.py -o /dev/null
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/common.py -O common.py -o /dev/null
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
+python3 generate_small.py
+python3 generate_large.py
+python3 ../assert_area.py
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
+    -p 'design -copy-to __test __test; \
+        synth_xilinx -abc9 -widemux 4; \
+        design -copy-from __test *; \
+        select -assert-any __test; \
+        script -scriptwire __test/w:assert_area'\
+    -l ../../../../../techlibs/xilinx/cells_sim.v"
+
+# Spot tests for -widemux thresholds
+set +e
+../../../../../yosys -qp "synth_xilinx -widemux 1" 2> /dev/null
+if [ $? -eq 0 ]; then
+    echo "Expected error"
+    exit 1
+fi
+set -e
+
+../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 1 t:MUXF7" mux_if_bal_2_1.v
+
+../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-count 6 t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 6 t:MUXF*" mux_case_3_3.v
+
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 9; select -assert-none t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 8; select -assert-none t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 7; select -assert-count 15 t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 6; select -assert-count 15 t:MUXF*" mux_index_7_5.v
+
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 18; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 17; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 16; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 15; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v

backends/Makefile

@@ -19,9 +19,11 @@ endef
 
 #write_aiger
 $(eval $(call template,write_aiger,write_aiger write_aiger_ascii write_aiger_zinit write_aiger_miter write_aiger_symbols write_aiger_map write_aiger_vmap write_aiger_I write_aiger_O write_aiger_B ))
+$(eval $(call template,write_aiger_error, write_aiger_cant_find_top_module write_aiger_cant_open_file write_aiger_miter_and_asserts write_aiger_unsupported_cell_type ))
 
 #write_blif
 $(eval $(call template,write_blif,write_blif write_blif_top write_blif_buf write_blif_unbuf write_blif_true  write_blif_false  write_blif_undef  write_blif_noalias  write_blif_icells  write_blif_gates  write_blif_conn  write_blif_attr  write_blif_param  write_blif_cname  write_blif_iname  write_blif_iattr  write_blif_blackbox  write_blif_impltf))
+$(eval $(call template,write_blif_error, write_blif_unmapped_mem write_blif_cant_find_top_module write_blif_unmapped_proc))
 
 #write_btor
 $(eval $(call template,write_btor,write_btor write_btor_v write_btor_s))
@@ -33,22 +35,21 @@ $(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor
 $(eval $(call template,write_btor_pmux,write_btor_pmux))
 $(eval $(call template,write_btor_and_or,write_btor_and_or))
 $(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
+$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type))
 
 #write_edif
 $(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
+$(eval $(call template,write_edif_error, write_edif_cyclic_dependency write_edif_constant_nodes write_edif_unmapped_mem write_edif_unmapped_proc write_edif_no_module_found ))
 
 #write_firrtl
 $(eval $(call template,write_firrtl,write_firrtl))
-#write_firrtl_mem_wr - issue #938
-#terminate called after throwing an instance of 'std::out_of_range'
-#  what():  dict::at()
-#run.sh: line 11:  9808 Aborted                 (core dumped)
-$(eval $(call template,write_firrtl_mem,write_firrtl_mem ))
+$(eval $(call template,write_firrtl_mem,write_firrtl_mem write_firrtl_mem_wr))
 $(eval $(call template,write_firrtl_logic,write_firrtl ))
 $(eval $(call template,write_firrtl_reduce,write_firrtl ))
 $(eval $(call template,write_firrtl_shift,write_firrtl ))
 $(eval $(call template,write_firrtl_shiftx,write_firrtl ))
 $(eval $(call template,write_firrtl_paramod,write_firrtl))
+$(eval $(call template,write_firrtl_error, write_firrtl_fully_selected write_firrtl_negative_edge_ff write_firrtl_inout_port write_firrtl_unclocked_write_port write_firrtl_complex_write_enable ))
 
 #write_ilang
 $(eval $(call template,write_ilang,write_ilang write_ilang_selected))
@@ -56,26 +57,31 @@ $(eval $(call template,write_ilang_mem,write_ilang_mem))
 $(eval $(call template,write_ilang_mux,write_ilang write_ilang_selected))
 $(eval $(call template,write_ilang_fsm,write_ilang write_ilang_selected))
 $(eval $(call template,write_ilang_tri,write_ilang write_ilang_selected))
+$(eval $(call template,write_ilang_error,write_ilang_error))
 
 #write_intersynth
 $(eval $(call template,write_intersynth,write_intersynth write_intersynth_selected write_intersynth_lib write_intersynth_notypes))
+$(eval $(call template,write_intersynth_error, write_intersynth_cant_export write_intersynth_unprocessed_proc write_intersynth_cant_open_lib_file))
 
 #write_json
 $(eval $(call template,write_json,write_json write_json_aig json json_o json_o_aig json_aig))
+$(eval $(call template,write_json_error,write_json_error))
 
 #write_simplec
 $(eval $(call template,write_simplec,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
 $(eval $(call template,write_simplec_mux,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
 $(eval $(call template,write_simplec_logic,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
+$(eval $(call template,write_simplec_error,write_simplec_no_c_model write_simplec_not_top_module ))
 
 #write_smt2
 $(eval $(call template,write_smt2,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
 $(eval $(call template,write_smt2_logic,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
-$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest))
+$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest))
 $(eval $(call template,write_smt2_fsm,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
 $(eval $(call template,write_smt2_init_assert,write_smt2_init_assert))
 $(eval $(call template,write_smt2_reduce,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
 $(eval $(call template,write_smt2_shiftx,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
+$(eval $(call template,write_smt2_error, write_smt2_cyclic_dependency write_smt2_cant_open_tpl write_smt2_multiple_drivers write_smt2_logic_loop ))
 
 #write_smv
 $(eval $(call template,write_smv,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
@@ -87,9 +93,11 @@ $(eval $(call template,write_smv_logic,write_smv write_smv_synth write_smv_nopro
 $(eval $(call template,write_smv_init_assert,write_smv_init_assert))
 $(eval $(call template,write_smv_cmos4,write_smv_cmos4))
 $(eval $(call template,write_smv_shiftx,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
+$(eval $(call template,write_smv_error,write_smv_cant_open_template write_smv_unsupported_cell))
 
 #write_spice
 $(eval $(call template,write_spice,write_spice write_spice_top write_spice_big_endian write_spice_neg_i write_spice_pos_i write_spice_nc_prefix write_spice_inames ))
+$(eval $(call template,write_spice_error, write_spice_cant_find_top_module write_spice_unmapped_mem write_spice_unmapped_proc))
 
 #write_table
 $(eval $(call template,write_table,write_table ))

backends/run.sh

@@ -10,34 +10,126 @@ cd $1/work_$2
 
 touch .start
 
-yosys -ql yosys.log ../../scripts/$2.ys
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
-sed -i 's/reg =/dummy =/' ./synth.v
+# cases where 'syntax error' or other errors are expected
+if echo "$1" | grep ".*_error"; then
 
-if [ -f "../../../../../techlibs/common/simcells.v" ]; then
-    COMMON_PREFIX=../../../../../techlibs/common
-else
-    COMMON_PREFIX=/usr/local/share/yosys
-fi
+	expected_string=""
+    #Change checked string for check other errors
+	if [ "$2" = "write_aiger_cant_find_top_module" ]; then
+		expected_string="ERROR: Can't find top module in current design!"
+	elif [ "$2" = "write_aiger_cant_open_file" ]; then
+		expected_string="ERROR: Can't open file "
+	elif [ "$2" = "write_aiger_miter_and_asserts" ]; then
+		expected_string="ERROR: Running AIGER back-end in -miter mode, but design contains \$assert, \$assume, \$live and/or \$fair cells!"
+	elif [ "$2" = "write_aiger_unsupported_cell_type" ]; then
+		expected_string="ERROR: Unsupported cell type: "
+	elif [ "$2" = "write_blif_unmapped_mem" ]; then
+		expected_string="ERROR: Found unmapped memories in module "
+	elif [ "$2" = "write_blif_cant_find_top_module" ]; then
+		expected_string="ERROR: Can't find top module "
+	elif [ "$2" = "write_blif_unmapped_proc" ]; then
+		expected_string="ERROR: Found unmapped processes in module "
+	elif [ "$2" = "write_btor_no_top_module" ]; then
+		expected_string="ERROR: No top module found."
+	elif [ "$2" = "write_btor_unsupported_cell_type" ]; then
+		expected_string="ERROR: Unsupported cell type: "
+	elif [ "$2" = "write_edif_cyclic_dependency" ]; then
+		expected_string="ERROR: Cyclic dependency between modules found! Cycle includes module "
+	elif [ "$2" = "write_edif_constant_nodes" ]; then
+		expected_string="ERROR: Design contains constant nodes (map with \"hilomap\" first)."
+	elif [ "$2" = "write_edif_unmapped_mem" ]; then
+		expected_string="ERROR: Found unmapped memories in module "
+	elif [ "$2" = "write_edif_unmapped_proc" ]; then
+		expected_string="ERROR: Found unmapped processes in module "
+	elif [ "$2" = "write_edif_no_module_found" ]; then
+		expected_string="ERROR: No module found in design!"
+	elif [ "$2" = "write_firrtl_fully_selected" ]; then
+		expected_string="ERROR: This command only operates on fully selected designs!"
+	elif [ "$2" = "write_firrtl_negative_edge_ff" ]; then
+		expected_string="ERROR: Negative edge clock on FF "
+	elif [ "$2" = "write_firrtl_inout_port" ]; then
+		expected_string="ERROR: Module port top.q_a is inout!"
+	elif [ "$2" = "write_firrtl_unclocked_write_port" ]; then
+		expected_string="ERROR: Unclocked write port "
+	elif [ "$2" = "write_firrtl_complex_write_enable" ]; then
+		expected_string="ERROR: Complex write enable on port "
+	elif [ "$2" = "write_ilang_error" ]; then
+		expected_string="ERROR: Can't open file \`tt/file1.il' for writing: No such file or directory"
+	elif [ "$2" = "write_intersynth_cant_export" ]; then
+		expected_string="ERROR: Can't export composite or non-word-wide signal "
+	elif [ "$2" = "write_intersynth_unprocessed_proc" ]; then
+		expected_string="ERROR: Can't generate a netlist for a module with unprocessed memories or processes!"
+	elif [ "$2" = "write_intersynth_cant_open_lib_file" ]; then
+		expected_string="ERROR: Can't open lib file "
+	elif [ "$2" = "write_json_error" ]; then
+		expected_string="ERROR: Can't open file "
+	elif [ "$2" = "write_simplec_no_c_model" ]; then
+		expected_string="ERROR: No C model for \$lut available at the moment (FIXME)."
+	elif [ "$2" = "write_simplec_not_top_module" ]; then
+		expected_string="ERROR: Current design has no top module."
+	elif [ "$2" = "write_smt2_cyclic_dependency" ]; then
+		expected_string="ERROR: Cyclic dependency between modules found! Cycle includes module "
+	elif [ "$2" = "write_smt2_cant_open_tpl" ]; then
+		expected_string="ERROR: Can't open template file "
+	elif [ "$2" = "write_smt2_multiple_drivers" ]; then
+		expected_string="ERROR: Found multiple drivers for "
+	elif [ "$2" = "write_smt2_logic_loop" ]; then
+		expected_string="ERROR: Found logic loop in module "
+	elif [ "$2" = "write_smv_cant_open_template" ]; then
+		expected_string="ERROR: Can't open template file "
+	elif [ "$2" = "write_smv_unsupported_cell" ]; then
+		expected_string="ERROR: Found currently unsupported cell type "
+	elif [ "$2" = "write_spice_cant_find_top_module" ]; then
+		expected_string="ERROR: Can't find top module "
+	elif [ "$2" = "write_spice_unmapped_mem" ]; then
+		expected_string="ERROR: Found unmapped memories in module "
+	elif [ "$2" = "write_spice_unmapped_proc" ]; then
+		expected_string="ERROR: Found unmapped processes in module"
+	fi
 
-iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
 
-if ! vvp -N testbench > testbench.log 2>&1; then
-	grep 'ERROR' testbench.log
-	echo FAIL > ${1}_${2}.status
-elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo FAIL > ${1}_${2}.status
+	if yosys -ql yosys.log ../../scripts/$2.ys; then
+		echo FAIL > ${1}_${2}.status
+	else
+		if  grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
+			echo PASS > ${1}_${2}.status
+		else
+			echo FAIL > ${1}_${2}.status
+		fi
+	fi
 else
-	echo PASS > ${1}_${2}.status
+
+
+	yosys -ql yosys.log ../../scripts/$2.ys
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+	sed -i 's/reg =/dummy =/' ./synth.v
+
+	if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+		COMMON_PREFIX=../../../../../techlibs/common
+	else
+		COMMON_PREFIX=/usr/local/share/yosys
+	fi
+
+	iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+
+	if ! vvp -N testbench > testbench.log 2>&1; then
+		grep 'ERROR' testbench.log
+		echo FAIL > ${1}_${2}.status
+	elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+		echo FAIL > ${1}_${2}.status
+	else
+		echo PASS > ${1}_${2}.status
+	fi
+
 fi
 
 touch .stamp

backends/scripts/write_aiger_cant_find_top_module.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
+synth -top top
+write_verilog synth.v

backends/scripts/write_aiger_cant_open_file.ys

+read_verilog -sv ../top2.v
+aigmap
+write_aiger -map tt/tt.map aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
+synth -top top
+write_verilog synth.v

backends/scripts/write_aiger_miter_and_asserts.ys

+read_verilog -sv ../top2.v
+aigmap
+write_aiger -miter aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
+synth -top top
+write_verilog synth.v

backends/scripts/write_aiger_unsupported_cell_type.ys

+read_verilog -sv ../top2.v
+synth
+write_aiger aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
+synth -top top
+write_verilog synth.v

backends/scripts/write_blif_cant_find_top_module.ys

+read_verilog -sv ../top.v
+proc
+write_blif -top u blif1.blif

backends/scripts/write_blif_unmapped_mem.ys

+read_verilog -sv ../top2.v
+proc
+write_blif -top u blif1.blif

backends/scripts/write_blif_unmapped_proc.ys

+read_verilog -sv ../top.v
+write_blif blif1.blif

backends/scripts/write_btor.ys

@@ -8,6 +8,7 @@ synth -top top
 write_btor btor1.btor
 design -reset
 read_verilog -sv ../top.v
+proc_prune
 proc_init
 proc_mux
 proc_dff

backends/scripts/write_btor_no_top_module.ys

+read_verilog ../top3.v
+memory
+proc
+write_btor btor.btor

backends/scripts/write_btor_s.ys

@@ -7,6 +7,7 @@ synth -top top
 write_btor -s btor1.btor
 design -reset
 read_verilog -sv ../top.v
+proc_prune
 proc_init
 proc_mux
 proc_dff

backends/scripts/write_btor_unsupported_cell_type.ys

+read_verilog ../top3.v
+synth_ice40
+write_btor btor.btor

backends/scripts/write_btor_v.ys

@@ -7,6 +7,7 @@ synth -top top
 write_btor -v btor1.btor
 design -reset
 read_verilog -sv ../top.v
+proc_prune
 proc_init
 proc_mux
 proc_dff
@@ -51,4 +52,4 @@ write_btor -v btor10.btor
 design -reset
 read_verilog  -sv ../top_clean.v
 synth -top top
-write_verilog synth.v 
+write_verilog synth.v

backends/scripts/write_edif_constant_nodes.ys

+read_verilog -sv ../top3.v
+proc
+write_edif -nogndvcc blif1.blif

backends/scripts/write_edif_cyclic_dependency.ys

+read_verilog -sv ../top4.v
+proc
+write_edif blif1.blif

backends/scripts/write_edif_no_module_found.ys

+write_edif edif.edif
+write_verilog synth.v

backends/scripts/write_edif_unmapped_mem.ys

+read_verilog ../top2.v
+proc
+write_edif -top top edif.edif
+write_verilog synth.v

backends/scripts/write_edif_unmapped_proc.ys

+read_verilog ../top.v
+write_edif -top top edif.edif
+write_verilog synth.v

backends/scripts/write_firrtl_complex_write_enable.ys

+read_verilog ../top1.v
+proc
+memory
+write_firrtl firrtl.firrtl
+write_verilog synth.v

backends/scripts/write_firrtl_fully_selected.ys

+read_verilog ../top1.v
+proc
+memory_dff -nordff
+memory_collect
+opt_reduce
+clean
+select top22
+write_firrtl firrtl.firrtl
+write_verilog synth.v

backends/scripts/write_firrtl_inout_port.ys

+read_verilog ../top2.v
+proc
+memory_dff -nordff
+memory_collect
+opt_reduce
+clean
+write_firrtl firrtl.firrtl
+write_verilog synth.v

backends/scripts/write_firrtl_mem_wr.ys

 read_verilog ../top.v
 proc
 memory_dff -nordff
+memory_collect
 opt_reduce
 clean
 write_firrtl firrtl.firrtl

backends/scripts/write_firrtl_negative_edge_ff.ys

+read_verilog ../top3.v
+proc
+write_firrtl firrtl.firrtl
+write_verilog synth.v

backends/scripts/write_firrtl_unclocked_write_port.ys

+read_verilog ../top.v
+
+memory
+proc
+write_firrtl firrtl.firrtl
+write_verilog synth.v

backends/scripts/write_ilang_error.ys

+read_verilog ../top.v
+write_ilang ilang.ilang
+proc
+dump -o file.il
+write_ilang ilang.ilang
+dump -n -o tt/file1.il
+synth
+write_verilog synth.v

backends/scripts/write_intersynth_cant_export.ys

+read_verilog ../top.v
+proc
+synth
+abc -lut 4
+write_intersynth intersynth.intersynth
+write_verilog synth.v

backends/scripts/write_intersynth_cant_open_lib_file.ys

+read_verilog ../top.v
+proc
+write_intersynth -lib u intersynth.intersynth
+write_verilog synth.v

backends/scripts/write_intersynth_unprocessed_proc.ys

+read_verilog ../top.v
+write_intersynth intersynth.intersynth
+write_verilog synth.v

backends/scripts/write_json_error.ys

+read_verilog ../top.v
+proc
+json -o tt/json.json
+write_verilog synth.v

backends/scripts/write_simplec_no_c_model.ys

+read_verilog ../top.v
+synth -top top
+abc -lut 4
+write_simplec c.c
+write_verilog synth.v

backends/scripts/write_simplec_not_top_module.ys

+read_verilog ../top.v
+write_simplec c.c
+write_verilog synth.v

backends/scripts/write_smt2_cant_open_tpl.ys

+read_verilog ../top.v
+proc
+memory
+write_smt2 -tpl u smt2.smt2
+write_verilog synth.v

backends/scripts/write_smt2_cyclic_dependency.ys

+read_verilog ../top3.v
+proc
+memory
+write_smt2 smt2.smt2
+write_verilog synth.v

backends/scripts/write_smt2_logic_loop.ys

+read_verilog ../top1.v
+proc
+memory
+write_smt2 smt2.smt2
+write_verilog synth.v

backends/scripts/write_smt2_multiple_drivers.ys

+read_verilog ../top2.v
+proc
+memory
+write_smt2 smt2.smt2
+write_verilog synth.v

backends/scripts/write_smv_cant_open_template.ys

+read_verilog ../top.v
+proc
+memory
+write_smv -tpl t smv.smv
+write_verilog synth.v

backends/scripts/write_smv_unsupported_cell.ys

+read_verilog ../top.v
+proc
+memory
+write_smv smv.smv
+write_verilog synth.v

backends/scripts/write_spice_cant_find_top_module.ys

+read_verilog ../top.v
+proc
+memory
+write_spice -top u sp.sp
+write_verilog synth.v

backends/scripts/write_spice_unmapped_mem.ys

+read_verilog ../top.v
+proc
+write_spice sp.sp
+write_verilog synth.v

backends/scripts/write_spice_unmapped_proc.ys

+read_verilog ../top.v
+write_spice sp.sp
+write_verilog synth.v

backends/write_aiger_error/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out;
+    wire carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_aiger_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module top2
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_aiger_error/top2.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output X
+ );
+
+ reg ASSERT = 1'bX;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 1'bX;
+        cout = 1'bZ;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate)
+        A <= 1'bX;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 1'bZ;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+assign X = 1'bX;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+

backends/write_aiger_error/top_clean.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_blif_error/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	reg patt_out1 = 0;
+	reg patt_carry_out1 = 0;
+	wire out;
+    wire carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    always @(posedge in[0]) begin
+    patt_out1 <=  ~in[1] + &in[2];
+    end
+    always @(negedge in[0]) begin
+        patt_carry_out1 <= in[2] ? |in[1] : patt_out;
+    end
+
+    always @(*) begin
+        if (in[0])
+            patt_out <=  patt_out|in[1]~&in[2];
+    end
+    always @(*) begin
+        if (~in[0])
+            patt_carry_out <=  patt_carry_out1&in[2]~|in[1];
+    end
+	assert_Z out_test(.A(out));
+
+endmodule

backends/write_blif_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg A1,cout1;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(negedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(*) begin
+    if (x)
+        A <=  A1|y~&cin;
+end
+always @(*) begin
+    if (~x)
+        cout <=  cout1&cin~|y;
+end
+`else
+assign {cout,A} =  1'bZ;
+`endif
+
+bb ubb (cin,y,x,A);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+
+ output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+endmodule

backends/write_blif_error/top2.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_btor_error/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk, posedge re_b)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends/write_btor_error/top2.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends/write_btor_error/top3.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule
+
+module top2
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends/write_edif_error/edif.edif

+(edif (rename id00001 "u/u")
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (comment "Generated by Yosys 0.8+553 (git sha1 c9949dba, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)")
+  (external LIB
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell GND
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface (port G (direction OUTPUT)))
+      )
+    )
+    (cell VCC
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface (port P (direction OUTPUT)))
+      )
+    )
+    (cell (rename id00002 "$and")
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface
+          (port A (direction INPUT))
+          (port B (direction INPUT))
+          (port Y (direction OUTPUT))
+        )
+      )
+    )
+    (cell (rename id00003 "$add")
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface
+          (port A (direction INPUT))
+          (port B (direction INPUT))
+          (port Y (direction OUTPUT))
+        )
+      )
+    )
+    (cell (rename id00004 "$dff")
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface
+          (port CLK (direction INPUT))
+          (port Q (direction OUTPUT))
+          (port D (direction INPUT))
+        )
+      )
+    )
+  )
+  (library DESIGN
+    (edifLevel 0)
+    (technology (numberDefinition))
+    (cell bb
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface
+          (port out1 (direction OUTPUT))
+          (port clk (direction INPUT))
+          (port in2 (direction INPUT))
+          (port in1 (direction INPUT))
+        )
+        (contents
+          (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))
+          (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))
+          (instance (rename id00005 "$procdff$8")
+            (viewRef VIEW_NETLIST (cellRef id00004 (libraryRef LIB)))
+            (property CLK_POLARITY (integer 1))
+            (property WIDTH (integer 1)))
+          (instance (rename id00006 "$and$top.v:40$7")
+            (viewRef VIEW_NETLIST (cellRef id00002 (libraryRef LIB)))
+            (property Y_WIDTH (integer 1))
+            (property B_WIDTH (integer 1))
+            (property A_WIDTH (integer 1))
+            (property B_SIGNED (integer 0))
+            (property A_SIGNED (integer 0)))
+          (net out1 (joined
+            (portRef Q (instanceRef id00005))
+            (portRef out1)
+          ))
+          (net clk (joined
+            (portRef CLK (instanceRef id00005))
+            (portRef clk)
+          ))
+          (net (rename id00007 "$and$top.v:40$7_Y") (joined
+            (portRef D (instanceRef id00005))
+            (portRef Y (instanceRef id00006))
+          ))
+          (net in2 (joined
+            (portRef B (instanceRef id00006))
+            (portRef in2)
+          ))
+          (net in1 (joined
+            (portRef A (instanceRef id00006))
+            (portRef in1)
+          ))
+        )
+      )
+    )
+    (cell top
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface
+          (port cout (direction OUTPUT))
+          (port A (direction OUTPUT))
+          (port cin (direction INPUT))
+          (port y (direction INPUT))
+          (port x (direction INPUT))
+        )
+        (contents
+          (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))
+          (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))
+          (instance (rename id00008 "$procdff$10")
+            (viewRef VIEW_NETLIST (cellRef id00004 (libraryRef LIB)))
+            (property CLK_POLARITY (integer 1))
+            (property WIDTH (integer 1)))
+          (instance (rename id00009 "$procdff$9")
+            (viewRef VIEW_NETLIST (cellRef id00004 (libraryRef LIB)))
+            (property CLK_POLARITY (integer 0))
+            (property WIDTH (integer 1)))
+          (instance ubb
+            (viewRef VIEW_NETLIST (cellRef bb)))
+          (instance (rename id00014 "$add$top.v:23$4")
+            (viewRef VIEW_NETLIST (cellRef id00003 (libraryRef LIB)))
+            (property Y_WIDTH (integer 1))
+            (property B_WIDTH (integer 1))
+            (property A_WIDTH (integer 1))
+            (property B_SIGNED (integer 0))
+            (property A_SIGNED (integer 0)))
+          (instance (rename id00015 "$add$top.v:20$2")
+            (viewRef VIEW_NETLIST (cellRef id00003 (libraryRef LIB)))
+            (property Y_WIDTH (integer 1))
+            (property B_WIDTH (integer 1))
+            (property A_WIDTH (integer 1))
+            (property B_SIGNED (integer 0))
+            (property A_SIGNED (integer 0)))
+          (net y (joined
+            (portRef A (instanceRef id00014))
+            (portRef A (instanceRef id00015))
+            (portRef id00012 (instanceRef ubb))
+            (portRef y)
+          ))
+          (net x (joined
+            (portRef CLK (instanceRef id00008))
+            (portRef CLK (instanceRef id00009))
+            (portRef id00011 (instanceRef ubb))
+            (portRef x)
+          ))
+          (net cout (joined
+            (portRef Q (instanceRef id00009))
+            (portRef cout)
+          ))
+          (net cin (joined
+            (portRef B (instanceRef id00015))
+            (portRef cin)
+            (portRef id00013 (instanceRef ubb))
+          ))
+          (net bb_out (joined
+            (portRef id00010 (instanceRef ubb))
+          ))
+          (net (rename id00016 "$add$top.v:20$2_Y") (joined
+            (portRef D (instanceRef id00008))
+            (portRef Y (instanceRef id00015))
+          ))
+          (net (rename id00017 "$add$top.v:23$4_Y") (joined
+            (portRef D (instanceRef id00009))
+            (portRef Y (instanceRef id00014))
+          ))
+          (net A (joined
+            (portRef A)
+            (portRef B (instanceRef id00014))
+            (portRef Q (instanceRef id00008))
+          ))
+        )
+      )
+    )
+  )
+  (design (rename id00001 "u/u")
+    (cellRef id00001 (libraryRef DESIGN))
+  )
+)

backends/write_edif_error/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out;
+    wire carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_edif_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ wire bb_out;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+bb ubb (cin,y,x,bb_out);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+endmodule

backends/write_edif_error/top2.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_edif_error/top3.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output X
+ );
+
+ wire bb_out;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+assign X = 1'bX;
+
+bb ubb (cin,y,x,bb_out);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+endmodule

backends/write_edif_error/top4.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output X
+ );
+
+ wire bb_out;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+assign X = 1'bX;
+
+bb ubb (cin,y,x,bb_out);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+
+	top utop (in1,in2,clk,out1);
+endmodule

backends/write_firrtl_error/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_firrtl_error/top1.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [0:0] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends/write_firrtl_error/top2.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	inout reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[0:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends/write_firrtl_error/top3.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_ilang_error/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

backends/write_ilang_error/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

backends/write_intersynth_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_intersynth_error/top2.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+ 
+
+ 
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate) 
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);    
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate) 
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_json_error/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	reg patt_out = 0;
+	reg patt_carry_out = 0;
+	wire out;
+    wire carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	always @(posedge in[0]) 
+        patt_out <=  in[1] + in[2];
+    always @(negedge in[0])
+        patt_carry_out <=  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_json_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+ 
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_simplec_error/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_equal b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_equal c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_equal cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule

backends/write_simplec_error/top.v

+module tristate (en, i, o);
+    input en;
+    input i;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG  
+    assign	io[0] = i & ~en;
+    assign	io[1] = i ? en : ~en;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_smt2_error/top.v

+module tristate (en, i, o);
+    input en;
+    input i;
+    output [1:0] o;
+
+    wire [1:0] io;
+
+`ifndef BUG
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? en : 1'bZ;
+
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+
+    assign 	io[1] = (i)? ~en : 1'bZ;
+
+    assign o = ~io;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_smt2_error/top1.v

+module tristate (en, i, o);
+    input en;
+    input i;
+    output [1:0] o;
+
+    wire [1:0] io;
+
+`ifndef BUG
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? o[1] : 1'bZ;
+
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+
+    assign 	io[1] = (i)? ~en : 1'bZ;
+
+    assign o = ~io;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_smt2_error/top2.v

+module tristate (en, i, o);
+    input en;
+    input i;
+    output [1:0] o;
+
+    wire [1:0] io;
+
+`ifndef BUG
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? en : 1'bZ;
+
+    assign 	io[0] = (~en)? ~i : 1'bZ;
+
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+
+    assign 	io[1] = (i)? ~en : 1'bZ;
+
+    assign o = ~io;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_smt2_error/top3.v

+module tristate (en, i, o);
+    input en;
+    input i;
+    output [1:0] o;
+
+    wire [1:0] io;
+
+`ifndef BUG
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? en : 1'bZ;
+
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+
+    assign 	io[1] = (i)? ~en : 1'bZ;
+
+    assign o = ~io;
+`endif
+
+top utop (en,i,o,io);
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (c )
+    );
+
+endmodule

backends/write_smv_error/top.tpl

+asdfsfSmodule u
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends/write_smv_error/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

backends/write_smv_error/top1.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;    
+    output [1:0] o;
+    
+    wire [1:0] io;
+`ifndef BUG    
+	assign 	io[0] = (en)? i : 1'bZ;
+		
+    assign 	io[1] = (i)? en : 1'bZ;
+		
+    assign o = io;
+`else
+	assign 	io[0] = (en)? ~i : 1'bZ;
+		
+    assign 	io[1] = (i)? ~en : 1'bZ;
+		
+    assign o = ~io;
+`endif
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

backends/write_spice_error/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

equiv/Makefile

@@ -20,6 +20,8 @@ endef
 #equiv_make
 $(eval $(call template,equiv_make,equiv_make equiv_make_inames equiv_make_blacklist equiv_make_encfile))
 $(eval $(call template,equiv_make_fsm,equiv_make_encfile equiv_make_encfile_fsm))
+$(eval $(call template,equiv_make_error,equiv_make_synth_error equiv_make_cant_open_encfile equiv_make_cant_open_blacklist equiv_make_cant_find_gate_mod equiv_make_cant_find_gold_mod equiv_make_invalid_num_of_args equiv_make_cant_match equiv_make_cant_match_gold_to_gate equiv_make_equiv_mod_already_exists equiv_make_gold_mod_contains_proc equiv_make_gate_mod_contains_proc))
+$(eval $(call template,equiv_make_fsm_error,equiv_make_redefenition_of_signal))
 
 #equiv_simple
 $(eval $(call template,equiv_simple,equiv_simple equiv_simple_v equiv_simple_undef equiv_simple_short equiv_simple_seq equiv_simple_nogroup))
@@ -27,18 +29,22 @@ $(eval $(call template,equiv_simple_fsm,equiv_simple equiv_simple_v equiv_simple
 
 #equiv_status
 $(eval $(call template,equiv_status,equiv_status))
+$(eval $(call template,equiv_status_error,equiv_status_assert))
 
 #equiv_struct
 $(eval $(call template,equiv_struct,equiv_struct equiv_struct_fwd equiv_struct_fwonly equiv_struct_icells equiv_struct_maxiter))
 
 #equiv_remove
 $(eval $(call template,equiv_remove,equiv_remove equiv_remove_gold equiv_remove_gate ))
+$(eval $(call template,equiv_remove_error,equiv_remove_gold_gate ))
 
 #equiv_purge
 $(eval $(call template,equiv_purge,equiv_purge ))
 
 #equiv_miter
+#equiv_miter_invalid_num_of_args - no error
 $(eval $(call template,equiv_miter,equiv_miter equiv_miter_trigger equiv_miter_cmp equiv_miter_assert equiv_miter_undef))
+$(eval $(call template,equiv_miter_error,equiv_miter_miter_module_already_exists equiv_miter_one_module_must_be_selected))
 
 #equiv_mark
 $(eval $(call template,equiv_mark,equiv_mark ))
@@ -48,8 +54,12 @@ $(eval $(call template,equiv_induct,equiv_induct equiv_induct_undef equiv_induct
 
 #equiv_add
 $(eval $(call template,equiv_add,equiv_add equiv_add_try ))
+# ERROR: This command must be executed in module context!
+#equiv_add_cant_find_gold_cell equiv_add_cant_find_gate_cell equiv_add_invalid_number_of_args
+$(eval $(call template,equiv_add_error,equiv_add_module_context ))
 
 #equiv_opt
 $(eval $(call template,equiv_opt,equiv_opt equiv_opt_run equiv_opt_map))
+$(eval $(call template,equiv_opt_error,equiv_opt_unknown_option equiv_opt_no_opt equiv_opt_fully_selected_des))
 
 .PHONY: all clean

equiv/equiv_add_error/logic.v

+
+`timescale 1ns/10ps
+`celldefine
+module NOR2_X0X2 (A, B, Y);
+input  A ;
+input  B ;
+output Y ;
+wire I0_out;
+
+   or  (I0_out, A, B);
+   not (Y, I0_out);
+
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module DFFARAS_X2X2(Q,QN,D,CLK,SN,RN);
+
+input D,CLK,SN,RN;
+output Q,QN;
+reg Q,QN;
+
+
+always @ (posedge CLK or negedge RN or negedge SN)
+
+begin
+if (!RN) begin
+Q<=1'b0; 
+QN<=1'b1;
+end
+else if (!SN) begin
+Q<=1'b1;
+QN<=1'b0;
+end
+else begin 
+Q<=D;
+QN<=!D;
+end
+end
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module TIEHL (tiehi, tielo);
+output  tiehi ;
+output  tielo ;
+
+assign tiehi = 1'b1;
+assign tielo = 1'b0;
+endmodule
+`endcelldefine
+
+`timescale 1ns/10ps
+`celldefine
+
+module INV_X2X2 (A, Y);
+input  A ;
+output Y ;
+
+   not (Y, A);
+/*
+   specify
+     // delay parameters
+     specparam
+       tplhl$A$Y = 0.23:0.23:0.23,
+       tphlh$A$Y = 0.33:0.33:0.33;
+
+     // path delays
+     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
+
+   endspecify
+*/
+endmodule
+`endcelldefine

equiv/equiv_add_error/synth_top.v

+/* Generated by Yosys 0.7 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os) */
+
+(* src = "top.v:1" *)
+module top(clk, rst, count);
+  (* src = "top.v:3" *)
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  (* src = "top.v:1" *)
+  input clk;
+  (* src = "top.v:1" *)
+  output count;
+  (* src = "top.v:1" *)
+  input rst;
+  INV_X2X2 _3_ (
+    .A(rst),
+    .Y(_1_)
+  );
+  TIEHL _4_ (
+    .tiehi(_2_)
+  );
+  DFFARAS_X2X2 _5_ (
+    .CLK(clk),
+    .D(_0_),
+    .Q(count),
+    .QN(_0_),
+    .RN(_1_),
+    .SN(_2_)
+  );
+endmodule

equiv/equiv_add_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire f;
+
+    top uut ( .clk(clk),
+              .rst(rst),
+              .count(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

equiv/equiv_add_error/top.v

+module top(input wire clk,rst,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_make_error/blacklist.txt

+NOR2_X0X2

equiv/equiv_make_error/encfile_redef.fsm

+.fsm FSM st
+.map 0000 -------------1
+.map 1000 ------------1-
+.map 1010 ------------1-
+.map 1010 -------------1
+.map 0100 -----------1--
+.map 1100 ----------1---
+.map 0010 ---------1----
+.map 1010 --------1-----
+.map 0110 -------1------
+.map 0001 ------1-------
+.map 1001 -----1--------
+.map 0101 ----1---------
+.map 1101 ---1----------
+.map 0011 --1-----------
+.map 1011 -1------------
+.map 0111 1-------------
+.map 1000 1-----1-------

equiv/equiv_make_error/encfile_synth_error.fsm

+.fsm FSM st
+.map 0000 -------------1
+.map 1000 ------------1-
+.maap 0100 -----------1--
+.map 1100 ----------1---
+.map 0010 ---------1----
+.map 1010 --------1-----
+.map 0110 -------1------
+.map 0001 ------1-------
+.map 1001 -----1--------
+.map 0101 ----1---------
+.map 1101 ---1----------
+.map 0011 --1-----------
+.map 1011 -1------------
+.map 0111 1-------------

equiv/equiv_make_error/logic.v

+
+`timescale 1ns/10ps
+`celldefine
+module NOR2_X0X2 (A, B, Y);
+input  A ;
+input  B ;
+output Y ;
+wire I0_out;
+
+   or  (I0_out, A, B);
+   not (Y, I0_out);
+
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module DFFARAS_X2X2(Q,QN,D,CLK,SN,RN);
+
+input D,CLK,SN,RN;
+output Q,QN;
+reg Q,QN;
+
+
+always @ (posedge CLK or negedge RN or negedge SN)
+
+begin
+if (!RN) begin
+Q<=1'b0; 
+QN<=1'b1;
+end
+else if (!SN) begin
+Q<=1'b1;
+QN<=1'b0;
+end
+else begin 
+Q<=D;
+QN<=!D;
+end
+end
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module TIEHL (tiehi, tielo);
+output  tiehi ;
+output  tielo ;
+
+assign tiehi = 1'b1;
+assign tielo = 1'b0;
+endmodule
+`endcelldefine
+
+`timescale 1ns/10ps
+`celldefine
+
+module INV_X2X2 (A, Y);
+input  A ;
+output Y ;
+
+   not (Y, A);
+/*
+   specify
+     // delay parameters
+     specparam
+       tplhl$A$Y = 0.23:0.23:0.23,
+       tphlh$A$Y = 0.33:0.33:0.33;
+
+     // path delays
+     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
+
+   endspecify
+*/
+endmodule
+`endcelldefine

equiv/equiv_make_error/synth_top.v

+/* Generated by Yosys 0.7 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os) */
+
+(* src = "top.v:1" *)
+module top(clk, rst, count);
+  (* src = "top.v:3" *)
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  (* src = "top.v:1" *)
+  input clk;
+  (* src = "top.v:1" *)
+  output count;
+  (* src = "top.v:1" *)
+  input rst;
+  INV_X2X2 _3_ (
+    .A(rst),
+    .Y(_1_)
+  );
+  TIEHL _4_ (
+    .tiehi(_2_)
+  );
+  DFFARAS_X2X2 _5_ (
+    .CLK(clk),
+    .D(_0_),
+    .Q(count),
+    .QN(_0_),
+    .RN(_1_),
+    .SN(_2_)
+  );
+endmodule

equiv/equiv_make_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire f;
+
+    top uut ( .clk(clk),
+              .rst(rst),
+              .count(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

equiv/equiv_make_error/top.v

+module top(input wire clk,rst,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_make_error/top1.v

+module top(input wire clk,output reg count);
+
+always @(posedge clk)begin
+	count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_make_error/top2.v

+module top(input wire clk,rst,set,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_make_fsm_error/blacklist.txt

+NOR2_X0X2

equiv/equiv_make_fsm_error/encfile.fsm

+.fsm FSM st
+.map 0000 -------------1
+.map 1000 ------------1-
+.map 1010 ------------1-
+.map 1010 -------------1
+.map 0100 -----------1--
+.map 1100 ----------1---
+.map 0010 ---------1----
+.map 1010 --------1-----
+.map 0110 -------1------
+.map 0001 ------1-------
+.map 1001 -----1--------
+.map 0101 ----1---------
+.map 1101 ---1----------
+.map 0011 --1-----------
+.map 1011 -1------------
+.map 0111 1-------------
+.map 1000 1-----1-------

equiv/equiv_make_fsm_error/encfile_redef.fsm

+.fsm FSM st
+.map 0000 -------------1
+.map 1000 ------------1-
+.map 1010 ------------1-
+.map 1010 -------------1
+.map 0100 -----------1--
+.map 1100 ----------1---
+.map 0010 ---------1----
+.map 1010 --------1-----
+.map 0110 -------1------
+.map 0001 ------1-------
+.map 1001 -----1--------
+.map 0101 ----1---------
+.map 1101 ---1----------
+.map 0011 --1-----------
+.map 1011 -1------------
+.map 0111 1-------------
+.map 1000 1-----1-------

equiv/equiv_make_fsm_error/logic.v

+module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
+
+parameter NAME = "";
+
+parameter CLK_POLARITY = 1'b1;
+parameter ARST_POLARITY = 1'b1;
+
+parameter CTRL_IN_WIDTH = 1;
+parameter CTRL_OUT_WIDTH = 1;
+
+parameter STATE_BITS = 1;
+parameter STATE_NUM = 1;
+parameter STATE_NUM_LOG2 = 1;
+parameter STATE_RST = 0;
+parameter STATE_TABLE = 1'b0;
+
+parameter TRANS_NUM = 1;
+parameter TRANS_TABLE = 4'b0x0x;
+
+input CLK, ARST;
+input [CTRL_IN_WIDTH-1:0] CTRL_IN;
+output reg [CTRL_OUT_WIDTH-1:0] CTRL_OUT;
+
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_arst = ARST == ARST_POLARITY;
+
+reg [STATE_BITS-1:0] state;
+reg [STATE_BITS-1:0] state_tmp;
+reg [STATE_BITS-1:0] next_state;
+
+reg [STATE_BITS-1:0] tr_state_in;
+reg [STATE_BITS-1:0] tr_state_out;
+reg [CTRL_IN_WIDTH-1:0] tr_ctrl_in;
+reg [CTRL_OUT_WIDTH-1:0] tr_ctrl_out;
+
+integer i;
+
+task tr_fetch;
+	input [31:0] tr_num;
+	reg [31:0] tr_pos;
+	reg [STATE_NUM_LOG2-1:0] state_num;
+	begin
+		tr_pos = (2*STATE_NUM_LOG2+CTRL_IN_WIDTH+CTRL_OUT_WIDTH)*tr_num;
+		tr_ctrl_out = TRANS_TABLE >> tr_pos;
+		tr_pos = tr_pos + CTRL_OUT_WIDTH;
+		state_num = TRANS_TABLE >> tr_pos;
+		tr_state_out = STATE_TABLE >> (STATE_BITS*state_num);
+		tr_pos = tr_pos + STATE_NUM_LOG2;
+		tr_ctrl_in = TRANS_TABLE >> tr_pos;
+		tr_pos = tr_pos + CTRL_IN_WIDTH;
+		state_num = TRANS_TABLE >> tr_pos;
+		tr_state_in = STATE_TABLE >> (STATE_BITS*state_num);
+		tr_pos = tr_pos + STATE_NUM_LOG2;
+	end
+endtask
+/*
+
+always @(posedge pos_clk, posedge pos_arst) begin
+	if (pos_arst) begin
+		state_tmp = STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
+		for (i = 0; i < STATE_BITS; i = i+1)
+			if (state_tmp[i] === 1'bz)
+				state_tmp[i] = 0;
+		state <= state_tmp;
+	end else begin
+		state_tmp = next_state;
+		for (i = 0; i < STATE_BITS; i = i+1)
+			if (state_tmp[i] === 1'bz)
+				state_tmp[i] = 0;
+		state <= state_tmp;
+	end
+end
+
+always @(state, CTRL_IN) begin
+	next_state <= STATE_TABLE[STATE_BITS*(STATE_RST+1)-1:STATE_BITS*STATE_RST];
+	CTRL_OUT <= 'bx;
+	// $display("---");
+	// $display("Q: %b %b", state, CTRL_IN);
+	for (i = 0; i < TRANS_NUM; i = i+1) begin
+		tr_fetch(i);
+		// $display("T: %b %b -> %b %b [%d]", tr_state_in, tr_ctrl_in, tr_state_out, tr_ctrl_out, i);
+		casez ({state, CTRL_IN})
+			{tr_state_in, tr_ctrl_in}: begin
+				// $display("-> %b %b <-   MATCH", state, CTRL_IN);
+				{next_state, CTRL_OUT} <= {tr_state_out, tr_ctrl_out};
+			end
+		endcase
+	end
+end
+*/
+endmodule

equiv/equiv_make_fsm_error/synth_top.v

+/* Generated by Yosys 0.8+96 (git sha1 2d73e1b6, gcc 8.2.0-7ubuntu1 -Og -fPIC) */
+
+(* cells_not_processed =  1  *)
+(* src = "top.v:1" *)
+module FSM(clk, rst, en, ls, rs, stop, busy, finish);
+  (* src = "top.v:71" *)
+  wire [2:0] _00_;
+  (* src = "top.v:19" *)
+  (* unused_bits = "0 1 2 3" *)
+  wire [3:0] _01_;
+  (* src = "top.v:80" *)
+  wire [31:0] _02_;
+  (* src = "top.v:43" *)
+  wire _03_;
+  (* src = "top.v:76" *)
+  wire _04_;
+  (* src = "top.v:85" *)
+  wire _05_;
+  (* src = "top.v:85" *)
+  wire _06_;
+  (* src = "top.v:87" *)
+  wire _07_;
+  (* src = "top.v:89" *)
+  wire _08_;
+  (* src = "top.v:89" *)
+  wire _09_;
+  (* src = "top.v:39" *)
+  wire _10_;
+  (* src = "top.v:53" *)
+  wire _11_;
+  (* src = "top.v:60" *)
+  wire _12_;
+  (* src = "top.v:85" *)
+  wire _13_;
+  (* src = "top.v:89" *)
+  wire _14_;
+  wire [2:0] _15_;
+  wire [2:0] _16_;
+  (* unused_bits = "0" *)
+  wire _17_;
+  (* unused_bits = "0" *)
+  wire _18_;
+  (* unused_bits = "0" *)
+  wire _19_;
+  (* unused_bits = "0" *)
+  wire _20_;
+  (* unused_bits = "0" *)
+  wire _21_;
+  (* unused_bits = "0" *)
+  wire _22_;
+  (* unused_bits = "0" *)
+  wire _23_;
+  (* unused_bits = "0" *)
+  wire _24_;
+  (* unused_bits = "0" *)
+  wire _25_;
+  (* unused_bits = "0" *)
+  wire _26_;
+  (* unused_bits = "0" *)
+  wire _27_;
+  (* unused_bits = "0" *)
+  wire _28_;
+  (* unused_bits = "0" *)
+  wire _29_;
+  (* unused_bits = "0" *)
+  wire _30_;
+  (* unused_bits = "0" *)
+  wire _31_;
+  (* unused_bits = "0" *)
+  wire _32_;
+  (* unused_bits = "0" *)
+  wire _33_;
+  (* unused_bits = "0" *)
+  wire _34_;
+  (* unused_bits = "0" *)
+  wire _35_;
+  (* unused_bits = "0" *)
+  wire _36_;
+  (* src = "top.v:9" *)
+  output busy;
+  (* src = "top.v:2" *)
+  input clk;
+  (* src = "top.v:16" *)
+  reg [2:0] count;
+  (* src = "top.v:4" *)
+  input en;
+  (* src = "top.v:10" *)
+  output finish;
+  (* src = "top.v:5" *)
+  input ls;
+  (* src = "top.v:6" *)
+  input rs;
+  (* src = "top.v:3" *)
+  input rst;
+  (* src = "top.v:8" *)
+  output stop;
+  assign _02_ = count + (* src = "top.v:80" *) 32'd1;
+  assign _03_ = ~ (* src = "top.v:43" *) ls;
+  (* fsm_encoding = "auto" *)
+  (* src = "top.v:14" *)
+  \$fsm  #(
+    .ARST_POLARITY(1'h1),
+    .CLK_POLARITY(1'h1),
+    .CTRL_IN_WIDTH(32'd7),
+    .CTRL_OUT_WIDTH(32'd6),
+    .NAME("\\st"),
+    .STATE_BITS(32'd14),
+    .STATE_NUM(32'd14),
+    .STATE_NUM_LOG2(32'd4),
+    .STATE_RST(32'd0),
+    .STATE_TABLE(196'b1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1zzzzzzzzzzzzzz1),
+    .TRANS_NUM(32'd34),
+    .TRANS_TABLE(714'b1101zzz0z0z10100000001101zzz1z0z10010000001101zzzzz1z00000000001100zzzzz0z00110000001100zzzzz1z00000000001011zzzzz0z01110000011011zzzzz1z00000000011010zzzzz0z10101000001010zzzzz1z000010000010010zzzz0z101100000010011zzzz0z01100000001001zzzzz1z00000000001000zzzzz0z00010010001000zzzzz1z00000010000111zzzzz0z01000000000111zzzzz1z00000000000110zzzz10z11010000000110zzzz00z00010000000110zzzzz1z00000000000101zzzzz0111000000000101zzzzz0000100000000101zzzzz1z00000000000100zz1zz0z10110000000100zz0zz0z00100000000100zzzzz1z00000000000011zzzzz0z01010000100011zzzzz1z00000000100010z0zzz0z10010100000010z1zzz0z01010100000010zzzzz1z00000100000001zzzzz0z10000001000001zzzzz1z00000001000000zzzzz0z01110000000000zzzzz1z0000000000)
+  ) _39_ (
+    .ARST(1'h0),
+    .CLK(clk),
+    .CTRL_IN({ _03_, _10_, rs, _11_, ls, rst, _12_ }),
+    .CTRL_OUT({ _07_, _04_, _09_, _08_, _06_, _05_ })
+  );
+  assign _10_ = count > (* src = "top.v:39" *) 32'd7;
+  assign _11_ = ls && (* src = "top.v:53" *) rs;
+  assign _12_ = ls || (* src = "top.v:60" *) rs;
+  assign _13_ = _05_ || (* src = "top.v:85" *) _06_;
+  assign _14_ = _08_ || (* src = "top.v:89" *) _09_;
+  always @(posedge clk)
+      count <= _00_;
+  assign _15_ = _10_ ? (* src = "top.v:77" *) 3'h0 : _02_[2:0];
+  assign _16_ = _04_ ? (* src = "top.v:76" *) _15_ : count;
+  assign _00_ = rst ? (* src = "top.v:72" *) _16_ : 3'h0;
+  assign stop = _13_ ? (* src = "top.v:85" *) 1'h1 : 1'h0;
+  assign finish = _07_ ? (* src = "top.v:87" *) 1'h1 : 1'h0;
+  assign busy = _14_ ? (* src = "top.v:89" *) 1'h1 : 1'h0;
+endmodule
+
+(* cells_not_processed =  1  *)
+(* src = "top.v:94" *)
+module top(clk, rst, en, a, b, s, bs, f);
+  (* src = "top.v:98" *)
+  input a;
+  (* src = "top.v:99" *)
+  input b;
+  (* src = "top.v:101" *)
+  output bs;
+  (* src = "top.v:95" *)
+  input clk;
+  (* src = "top.v:97" *)
+  input en;
+  (* src = "top.v:102" *)
+  output f;
+  (* src = "top.v:96" *)
+  input rst;
+  (* src = "top.v:100" *)
+  output s;
+  (* module_not_derived = 32'd1 *)
+  (* src = "top.v:105" *)
+  FSM u_FSM (
+    .busy(bs),
+    .clk(clk),
+    .en(en),
+    .finish(f),
+    .ls(a),
+    .rs(b),
+    .rst(rst),
+    .stop(s)
+  );
+endmodule

equiv/equiv_make_fsm_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg a = 0;
+    reg b = 0;
+    reg rst;    
+    reg en;
+    wire s;
+    wire bs;
+    wire f;
+    
+    top uut ( .clk(clk),
+              .rst(rst), 
+              .en(en), 
+              .a(a), 
+              .b(b), 
+              .s(s), 
+              .bs(bs), 
+              .f(f));
+              
+    always @(posedge clk)
+    begin
+        #2
+        a <= ~a;
+    end
+    
+    always @(posedge clk)
+    begin
+        #4
+        b <= ~b;
+    end
+    
+    initial begin
+        en <= 1;
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+    
+    
+    assert_expr s_test(.clk(clk), .A(s));
+	assert_expr bs_test(.clk(clk), .A(bs));
+	assert_expr f_test(.clk(clk), .A(f));
+  
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

equiv/equiv_make_fsm_error/top.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

equiv/equiv_miter_error/logic.v

+
+`timescale 1ns/10ps
+`celldefine
+module NOR2_X0X2 (A, B, Y);
+input  A ;
+input  B ;
+output Y ;
+wire I0_out;
+
+   or  (I0_out, A, B);
+   not (Y, I0_out);
+
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module DFFARAS_X2X2(Q,QN,D,CLK,SN,RN);
+
+input D,CLK,SN,RN;
+output Q,QN;
+reg Q,QN;
+
+
+always @ (posedge CLK or negedge RN or negedge SN)
+
+begin
+if (!RN) begin
+Q<=1'b0; 
+QN<=1'b1;
+end
+else if (!SN) begin
+Q<=1'b1;
+QN<=1'b0;
+end
+else begin 
+Q<=D;
+QN<=!D;
+end
+end
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module TIEHL (tiehi, tielo);
+output  tiehi ;
+output  tielo ;
+
+assign tiehi = 1'b1;
+assign tielo = 1'b0;
+endmodule
+`endcelldefine
+
+`timescale 1ns/10ps
+`celldefine
+
+module INV_X2X2 (A, Y);
+input  A ;
+output Y ;
+
+   not (Y, A);
+/*
+   specify
+     // delay parameters
+     specparam
+       tplhl$A$Y = 0.23:0.23:0.23,
+       tphlh$A$Y = 0.33:0.33:0.33;
+
+     // path delays
+     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
+
+   endspecify
+*/
+endmodule
+`endcelldefine

equiv/equiv_miter_error/synth_top.v

+/* Generated by Yosys 0.7 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os) */
+
+(* src = "top.v:1" *)
+module top(clk, rst, count);
+  (* src = "top.v:3" *)
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  (* src = "top.v:1" *)
+  input clk;
+  (* src = "top.v:1" *)
+  output count;
+  (* src = "top.v:1" *)
+  input rst;
+  INV_X2X2 _3_ (
+    .A(rst),
+    .Y(_1_)
+  );
+  TIEHL _4_ (
+    .tiehi(_2_)
+  );
+  DFFARAS_X2X2 _5_ (
+    .CLK(clk),
+    .D(_0_),
+    .Q(count),
+    .QN(_0_),
+    .RN(_1_),
+    .SN(_2_)
+  );
+endmodule

equiv/equiv_miter_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire f;
+
+    top uut ( .clk(clk),
+              .rst(rst),
+              .count(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

equiv/equiv_miter_error/top.v

+module top(input wire clk,rst,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_opt_error/logic.v

+
+`timescale 1ns/10ps
+`celldefine
+module NOR2_X0X2 (A, B, Y);
+input  A ;
+input  B ;
+output Y ;
+wire I0_out;
+
+   or  (I0_out, A, B);
+   not (Y, I0_out);
+
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module DFFARAS_X2X2(Q,QN,D,CLK,SN,RN);
+
+input D,CLK,SN,RN;
+output Q,QN;
+reg Q,QN;
+
+
+always @ (posedge CLK or negedge RN or negedge SN)
+
+begin
+if (!RN) begin
+Q<=1'b0; 
+QN<=1'b1;
+end
+else if (!SN) begin
+Q<=1'b1;
+QN<=1'b0;
+end
+else begin 
+Q<=D;
+QN<=!D;
+end
+end
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module TIEHL (tiehi, tielo);
+output  tiehi ;
+output  tielo ;
+
+assign tiehi = 1'b1;
+assign tielo = 1'b0;
+endmodule
+`endcelldefine
+
+`timescale 1ns/10ps
+`celldefine
+
+module INV_X2X2 (A, Y);
+input  A ;
+output Y ;
+
+   not (Y, A);
+/*
+   specify
+     // delay parameters
+     specparam
+       tplhl$A$Y = 0.23:0.23:0.23,
+       tphlh$A$Y = 0.33:0.33:0.33;
+
+     // path delays
+     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
+
+   endspecify
+*/
+endmodule
+`endcelldefine

equiv/equiv_opt_error/map.map

+module top(input wire clk,rst,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_opt_error/synth_top.v

+/* Generated by Yosys 0.7 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os) */
+
+(* src = "top.v:1" *)
+module top(clk, rst, count);
+  (* src = "top.v:3" *)
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  (* src = "top.v:1" *)
+  input clk;
+  (* src = "top.v:1" *)
+  output count;
+  (* src = "top.v:1" *)
+  input rst;
+  INV_X2X2 _3_ (
+    .A(rst),
+    .Y(_1_)
+  );
+  TIEHL _4_ (
+    .tiehi(_2_)
+  );
+  DFFARAS_X2X2 _5_ (
+    .CLK(clk),
+    .D(_0_),
+    .Q(count),
+    .QN(_0_),
+    .RN(_1_),
+    .SN(_2_)
+  );
+endmodule

equiv/equiv_opt_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire f;
+
+    top uut ( .clk(clk),
+              .rst(rst),
+              .count(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

equiv/equiv_opt_error/top.v

+module top(input wire clk,rst,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_remove_error/logic.v

+
+`timescale 1ns/10ps
+`celldefine
+module NOR2_X0X2 (A, B, Y);
+input  A ;
+input  B ;
+output Y ;
+wire I0_out;
+
+   or  (I0_out, A, B);
+   not (Y, I0_out);
+
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module DFFARAS_X2X2(Q,QN,D,CLK,SN,RN);
+
+input D,CLK,SN,RN;
+output Q,QN;
+reg Q,QN;
+
+
+always @ (posedge CLK or negedge RN or negedge SN)
+
+begin
+if (!RN) begin
+Q<=1'b0; 
+QN<=1'b1;
+end
+else if (!SN) begin
+Q<=1'b1;
+QN<=1'b0;
+end
+else begin 
+Q<=D;
+QN<=!D;
+end
+end
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module TIEHL (tiehi, tielo);
+output  tiehi ;
+output  tielo ;
+
+assign tiehi = 1'b1;
+assign tielo = 1'b0;
+endmodule
+`endcelldefine
+
+`timescale 1ns/10ps
+`celldefine
+
+module INV_X2X2 (A, Y);
+input  A ;
+output Y ;
+
+   not (Y, A);
+/*
+   specify
+     // delay parameters
+     specparam
+       tplhl$A$Y = 0.23:0.23:0.23,
+       tphlh$A$Y = 0.33:0.33:0.33;
+
+     // path delays
+     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
+
+   endspecify
+*/
+endmodule
+`endcelldefine

equiv/equiv_remove_error/synth_top.v

+/* Generated by Yosys 0.7 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os) */
+
+(* src = "top.v:1" *)
+module top(clk, rst, count);
+  (* src = "top.v:3" *)
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  (* src = "top.v:1" *)
+  input clk;
+  (* src = "top.v:1" *)
+  output count;
+  (* src = "top.v:1" *)
+  input rst;
+  INV_X2X2 _3_ (
+    .A(rst),
+    .Y(_1_)
+  );
+  TIEHL _4_ (
+    .tiehi(_2_)
+  );
+  DFFARAS_X2X2 _5_ (
+    .CLK(clk),
+    .D(_0_),
+    .Q(count),
+    .QN(_0_),
+    .RN(_1_),
+    .SN(_2_)
+  );
+endmodule

equiv/equiv_remove_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire f;
+
+    top uut ( .clk(clk),
+              .rst(rst),
+              .count(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

equiv/equiv_remove_error/top.v

+module top(input wire clk,rst,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/equiv_status_error/logic.v

+
+`timescale 1ns/10ps
+`celldefine
+module NOR2_X0X2 (A, B, Y);
+input  A ;
+input  B ;
+output Y ;
+wire I0_out;
+
+   or  (I0_out, A, B);
+   not (Y, I0_out);
+
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module DFFARAS_X2X2(Q,QN,D,CLK,SN,RN);
+
+input D,CLK,SN,RN;
+output Q,QN;
+reg Q,QN;
+
+
+always @ (posedge CLK or negedge RN or negedge SN)
+
+begin
+if (!RN) begin
+Q<=1'b0; 
+QN<=1'b1;
+end
+else if (!SN) begin
+Q<=1'b1;
+QN<=1'b0;
+end
+else begin 
+Q<=D;
+QN<=!D;
+end
+end
+endmodule
+`endcelldefine
+
+
+`timescale 1ns/10ps
+`celldefine
+module TIEHL (tiehi, tielo);
+output  tiehi ;
+output  tielo ;
+
+assign tiehi = 1'b1;
+assign tielo = 1'b0;
+endmodule
+`endcelldefine
+
+`timescale 1ns/10ps
+`celldefine
+
+module INV_X2X2 (A, Y);
+input  A ;
+output Y ;
+
+   not (Y, A);
+/*
+   specify
+     // delay parameters
+     specparam
+       tplhl$A$Y = 0.23:0.23:0.23,
+       tphlh$A$Y = 0.33:0.33:0.33;
+
+     // path delays
+     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
+
+   endspecify
+*/
+endmodule
+`endcelldefine

equiv/equiv_status_error/synth_top.v

+/* Generated by Yosys 0.7 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os) */
+
+(* src = "top.v:1" *)
+module top(clk, rst, count);
+  (* src = "top.v:3" *)
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  (* src = "top.v:1" *)
+  input clk;
+  (* src = "top.v:1" *)
+  output count;
+  (* src = "top.v:1" *)
+  input rst;
+  INV_X2X2 _3_ (
+    .A(rst),
+    .Y(_1_)
+  );
+  TIEHL _4_ (
+    .tiehi(_2_)
+  );
+  DFFARAS_X2X2 _5_ (
+    .CLK(clk),
+    .D(_0_),
+    .Q(count),
+    .QN(_0_),
+    .RN(_1_),
+    .SN(_2_)
+  );
+endmodule

equiv/equiv_status_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg rst;
+    wire f;
+
+    top uut ( .clk(clk),
+              .rst(rst),
+              .count(f));
+
+    initial begin
+        rst <= 1;
+        #5
+        rst <= 0;
+    end
+
+
+	assert_expr f_test(.clk(clk), .A(f));
+
+endmodule
+
+
+module assert_expr(input clk, input A);
+    always @(posedge clk)
+    begin
+        //#1;
+        if (A == 1'bZ)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

equiv/equiv_status_error/top.v

+module top(input wire clk,rst,output reg count);
+
+always @(posedge clk or posedge rst)begin
+	if(rst)
+		count <= 0;
+	else
+		count <= count + 1'b1;
+end
+
+endmodule

equiv/run.sh

@@ -10,34 +10,106 @@ cd $1/work_$2
 
 touch .start
 
-yosys -ql yosys.log ../../scripts/$2.ys
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
-sed -i 's/reg =/dummy =/' ./synth.v
+# cases where 'syntax error' or other errors are expected
+if echo "$1" | grep ".*_error"; then
 
-if [ -f "../../../../../techlibs/common/simcells.v" ]; then
-    COMMON_PREFIX=../../../../../techlibs/common
-else
-    COMMON_PREFIX=/usr/local/share/yosys
-fi
+	expected_string=""
+    #Change checked string for check other errors
+	if [ "$2" = "equiv_add_module_context" ]; then
+		expected_string="ERROR: This command must be executed in module context!"
+	elif [ "$2" = "equiv_add_cant_find_gold_cell" ]; then
+		expected_string="ERROR: Can't find gold cell"
+	elif [ "$2" = "equiv_add_cant_find_gate_cell" ]; then
+		expected_string="ERROR: Can't find gate cell"
+	elif [ "$2" = "equiv_add_invalid_number_of_args" ]; then
+		expected_string="ERROR: Invalid number of arguments."
+	elif [ "$2" = "equiv_make_synth_error" ]; then
+		expected_string="ERROR: Syntax error in encfile '../encfile_synth_error.fsm'!"
+	elif [ "$2" = "equiv_make_redefenition_of_signal" ]; then
+		expected_string="ERROR: Re-definition of signal"
+	elif [ "$2" = "equiv_make_cant_open_encfile" ]; then
+		expected_string="ERROR: Can't open encfile 'encfile111.fsm'!"
+	elif [ "$2" = "equiv_make_cant_open_blacklist" ]; then
+		expected_string="ERROR: Can't open blacklist file '../black.txt'!"
+	elif [ "$2" = "equiv_make_cant_find_gate_mod" ]; then
+		expected_string="ERROR: Can't find gate module"
+	elif [ "$2" = "equiv_make_cant_find_gold_mod" ]; then
+		expected_string="ERROR: Can't find gold module"
+	elif [ "$2" = "equiv_make_invalid_num_of_args" ]; then
+		expected_string="ERROR: Invalid number of arguments"
+	elif [ "$2" = "equiv_make_cant_match" ]; then
+		expected_string="ERROR: Can't match gate port \`rst_gate' to a gold port"
+	elif [ "$2" = "equiv_make_cant_match_gold_to_gate" ]; then
+		expected_string="ERROR: Can't match gold port \`set_gold' to a gate port"
+	elif [ "$2" = "equiv_make_equiv_mod_already_exists" ]; then
+		expected_string="ERROR: Equiv module equiv already exists."
+	elif [ "$2" = "equiv_make_gold_mod_contains_proc" ]; then
+		expected_string="ERROR: Gold module contains memories or procresses. Run 'memory' or 'proc' respectively."
+	elif [ "$2" = "equiv_make_gate_mod_contains_proc" ]; then
+		expected_string="ERROR: Gate module contains memories or procresses. Run 'memory' or 'proc' respectively."
+	elif [ "$2" = "equiv_miter_invalid_num_of_args" ]; then
+		expected_string="ERROR: Invalid number of arguments."
+	elif [ "$2" = "equiv_miter_miter_module_already_exists" ]; then
+		expected_string="ERROR: Miter module equiv already exists"
+	elif [ "$2" = "equiv_miter_one_module_must_be_selected" ]; then
+		expected_string="ERROR: Exactly one module must be selected for 'equiv_miter'!"
+	elif [ "$2" = "equiv_opt_unknown_option" ]; then
+		expected_string="ERROR: Command syntax error: Unknown option."
+	elif [ "$2" = "equiv_opt_no_opt" ]; then
+		expected_string="ERROR: No optimization pass specified!"
+	elif [ "$2" = "equiv_opt_fully_selected_des" ]; then
+		expected_string="ERROR: This command only operates on fully selected designs!"
+	elif [ "$2" = "equiv_remove_gold_gate" ]; then
+		expected_string="ERROR: Options -gold and -gate are exclusive."
+	elif [ "$2" = "equiv_status_assert" ]; then
+		expected_string="ERROR: Found 1 unproven \$equiv cells in 'equiv_status -assert'."
+
+
+	fi
 
-iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
 
-if ! vvp -N testbench > testbench.log 2>&1; then
-	grep 'ERROR' testbench.log
-	echo FAIL > ${1}_${2}.status
-elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo FAIL > ${1}_${2}.status
+	if yosys -ql yosys.log ../../scripts/$2.ys; then
+		echo FAIL > ${1}_${2}.status
+	else
+		if  grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
+			echo PASS > ${1}_${2}.status
+		else
+			echo FAIL > ${1}_${2}.status
+		fi
+	fi
 else
-	echo PASS > ${1}_${2}.status
+
+
+	yosys -ql yosys.log ../../scripts/$2.ys
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+	sed -i 's/reg =/dummy =/' ./synth.v
+
+	if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+		COMMON_PREFIX=../../../../../techlibs/common
+	else
+		COMMON_PREFIX=/usr/local/share/yosys
+	fi
+
+	iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+
+	if ! vvp -N testbench > testbench.log 2>&1; then
+		grep 'ERROR' testbench.log
+		echo FAIL > ${1}_${2}.status
+	elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+		echo FAIL > ${1}_${2}.status
+	else
+		echo PASS > ${1}_${2}.status
+	fi
+
 fi
 
 touch .stamp

equiv/scripts/equiv_add_cant_find_gate_cell.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -save something
+design -push
+equiv_add gold gateeee
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_add_cant_find_gold_cell.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -save something
+design -push
+equiv_add golddd gate
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_add_invalid_number_of_args.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -save something
+design -push
+equiv_add gold gate gate gate gate
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_add_module_context.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -save something
+design -push
+equiv_add gold gate
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_make_cant_find_gate_mod.ys

+read_verilog ../top.v
+proc
+fsm_detect
+fsm_extract
+fsm_recode -encfile encfile.fsm
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gat equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_cant_find_gold_mod.ys

+read_verilog ../top.v
+proc
+fsm_detect
+fsm_extract
+fsm_recode -encfile encfile.fsm
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gol gat equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_cant_match.ys

+read_verilog ../top1.v
+proc
+fsm_detect
+fsm_extract
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_cant_match_gold_to_gate.ys

+read_verilog ../top2.v
+proc
+fsm_detect
+fsm_extract
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_cant_open_blacklist.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make -blacklist ../black.txt gold gate equiv
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_make_cant_open_encfile.ys

+read_verilog ../top.v
+proc
+fsm_detect
+fsm_extract
+fsm_recode -encfile encfile.fsm
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make -encfile encfile111.fsm gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_equiv_mod_already_exists.ys

+read_verilog ../top.v
+proc
+fsm_detect
+fsm_extract
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+equiv_make gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_gate_mod_contains_proc.ys

+read_verilog ../top.v
+fsm_detect
+fsm_extract
+design -stash gate
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gold
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_gold_mod_contains_proc.ys

+read_verilog ../top.v
+fsm_detect
+fsm_extract
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_invalid_num_of_args.ys

+read_verilog ../top.v
+proc
+fsm_detect
+fsm_extract
+fsm_recode -encfile encfile.fsm
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_redefenition_of_signal.ys

+read_verilog ../top.v
+proc
+fsm_detect
+fsm_extract
+fsm_recode -encfile encfile.fsm
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make -encfile ../encfile_redef.fsm -encfile ../encfile.fsm gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_make_synth_error.ys

+read_verilog ../top.v
+proc
+fsm_detect
+fsm_extract
+fsm_recode -encfile encfile.fsm
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+proc
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make -encfile ../encfile_synth_error.fsm gold gate equiv
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

equiv/scripts/equiv_miter_invalid_num_of_args.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+equiv_miter miter_module equiv sss uuu ggg
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_miter_miter_module_already_exists.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+equiv_miter equiv
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_miter_one_module_must_be_selected.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top top1
+equiv_make gold gate equiv
+equiv_make gold gate equiv1
+equiv_miter miter_module equiv equiv1
+equiv_miter miter_module equiv1 equiv
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_opt_fully_selected_des.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+select equiv
+equiv_opt -run a:b equiv_purge
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_opt_no_opt.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+equiv_opt
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_opt_unknown_option.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+equiv_opt -
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_remove_gold_gate.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+equiv_remove -gate -gold equiv
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

equiv/scripts/equiv_status_assert.ys

+read_verilog ../top.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gold
+read_verilog ../synth_top.v
+read_verilog ../logic.v
+prep -flatten -top top
+splitnets -ports;;
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_status -assert
+equiv_make gold gate equiv
+equiv_status -assert
+design -reset
+read_verilog ../top.v
+write_verilog synth.v

frontends/Makefile

@@ -27,6 +27,7 @@ $(eval $(call template,read_blif_mux,read_blif read_blif_attr read_blif_buf read
 $(eval $(call template,read_blif_pmux,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
 $(eval $(call template,read_blif_tri,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
 $(eval $(call template,read_blif_eblif,read_blif_eblif))
+$(eval $(call template,read_blif_error, read_blif_syntax_error read_blif_duplicate_defenition ))
 
 #read_ilang
 $(eval $(call template,read_ilang,read_ilang read_ilang_selected))
@@ -34,6 +35,7 @@ $(eval $(call template,read_ilang_fsm,read_ilang read_ilang_selected))
 $(eval $(call template,read_ilang_mem,read_ilang read_ilang_selected))
 $(eval $(call template,read_ilang_mux,read_ilang read_ilang_selected))
 $(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected))
+$(eval $(call template,read_ilang_error,read_ilang_parse_error))
 
 #read_json
 $(eval $(call template,read_json,read_json))
@@ -42,6 +44,7 @@ $(eval $(call template,read_json_logic,read_json))
 $(eval $(call template,read_json_mem,read_json_mem))
 $(eval $(call template,read_json_mux,read_json))
 $(eval $(call template,read_json_tri,read_json))
+$(eval $(call template,read_json_error, read_json_nonstring_key read_json_nonarray_bits_attr read_json_unexpected_eof read_json_invalid_direction read_json_no_bits read_json_no_direction read_json_unexpected_char ))
 
 #read_liberty  read_liberty_lib
 $(eval $(call template,read_liberty,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
@@ -55,6 +58,7 @@ $(eval $(call template,read_liberty_latch,read_liberty read_liberty_nooverwrite
 $(eval $(call template,read_liberty_latch_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
 $(eval $(call template,read_liberty_diff_inv,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
 $(eval $(call template,read_liberty_tri,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
+$(eval $(call template,read_liberty_error, read_liberty_invalid_bus_type read_liberty_unsupp_type_for_bus read_liberty_bus_interface_only_in_lib_mode read_liberty_latch_has_no_data_in read_liberty_miss_func_on_output read_liberty_ff_has_no_next_stage_attr read_liberty_parse_error_in_function read_liberty_cant_resolve_wire_name read_liberty_missing_direction read_liberty_cant_open_input_file read_liberty_redefenition_of_module ))
 
 #read_aiger
 $(eval $(call template,read_aiger,read_aiger read_aiger_proc read_aiger_ascii read_aiger_module read_aiger_clk read_aiger_clk_module ))
@@ -62,6 +66,7 @@ $(eval $(call template,read_aiger_latch,read_aiger_aig))
 $(eval $(call template,read_aiger_logic,read_aiger_aig))
 $(eval $(call template,read_aiger_ff,read_aiger_aig))
 $(eval $(call template,read_aiger_mult,read_aiger_aig))
+$(eval $(call template,read_aiger_error, read_aiger_cant_interpret_first_char read_aiger_unsup_aiger_file read_aiger_invalid_aiger_header read_aiger_cant_interpret_as_input read_aiger_cant_interpret_as_and read_aiger_bad_state_property read_aiger_invalid_reset_literal read_aiger_duplicate_definition ))
 
 #read
 # read_vhdl87 read_vhdl93 read_vhdl2k read_vhdl2008 read_vhdl - ERROR: This version of Yosys is built without Verific support.
@@ -72,9 +77,11 @@ $(eval $(call template,read_verilog,read_verilog read_verilog_assert_assumes rea
 
 #verilog_defaults
 $(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push verilog_defaults_pop verilog_defaults_clear))
+$(eval $(call template,verilog_defaults_error,verilog_defaults_missing_arg verilog_defaults_extra_arg))
 
 #verilog_defines
 $(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
+$(eval $(call template,verilog_defines_error,verilog_defines_extra_arg))
 
 #verilog_lexer
 $(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))

frontends/read_aiger_error/aiger_ff1.aiger

+aaga 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_ff2.aiger

+aag 7 2 1 2 4 a
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_ff3.aiger

+aag 7 2 1 2 4
+2 s
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_ff4.aiger

+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7f
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends/read_aiger_error/aiger_latch1.aiger

+aag 1 0 1 2 0 2
+2 3
+2
+3

frontends/read_aiger_error/aiger_latch2.aiger

+aag 1 0 1 2 0
+2 3 3
+2
+3

frontends/read_aiger_error/aiger_latch3.aiger

+aag 1 0 1 2 0
+2 3
+21
+3

frontends/read_blif_error/blif_e1.blif

+# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+
+.modell top
+.inputs C S[0] S[1]
+.outputs Y[0] Y[1] Y[2] Y[3]
+.names $false
+.names $true
+1
+.names $undef
+.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
+.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
+.names $false $1\Y[3:0][0]
+1 1
+.names $false $1\Y[3:0][1]
+1 1
+.names $false $1\Y[3:0][2]
+1 1
+.names $false $1\Y[3:0][3]
+1 1
+.names $procmux$3_Y[0] $0\Y[3:0][0]
+1 1
+.names $procmux$3_Y[1] $0\Y[3:0][1]
+1 1
+.names $procmux$3_Y[2] $0\Y[3:0][2]
+1 1
+.names $procmux$3_Y[3] $0\Y[3:0][3]
+1 1
+.end

frontends/read_blif_error/blif_seg_fault.blif

+# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+
+.model top
+.inputs C S[0] S[1]
+.outputs Y[0] Y[1] Y[2] Y[3]
+.names $false
+.names $true
+1
+.names $undef
+.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
+.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
+.names $false $1\Y[3:0][0]
+1 1
+.names
+1 1
+.names $false $1\Y[3:0][2]
+1 1
+.names $false $1\Y[3:0][3]
+1 1
+.names $procmux$3_Y[0] $0\Y[3:0][0]
+1 1
+.names $procmux$3_Y[1] $0\Y[3:0][1]
+1 1
+.names $procmux$3_Y[2] $0\Y[3:0][2]
+1 1
+.names $procmux$3_Y[3] $0\Y[3:0][3]
+1 1
+.end

frontends/read_blif_error/eblif_seg_fault.eblif

+
+.model top
+.names a b
+.inputs a
+.outputs b
+.conn a b
+.names a b c
+11 1
+.cname $my_and_gate
+.latch a_and_b dff_q re clk 0
+.attr my_design.v:42
+.end

frontends/read_blif_error/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

frontends/read_ilang_error/file.il

+
+autoidx 15
+
+attribute \cells_not_processed 1
+attribute \src "top.v:1"
+module \top
+
+  attribute \src "top.v:17"
+  wire $0\B[0:0]
+
+  attribute \src "top.v:19"
+  attribute \unused_bits "1"
+  wire width 2 $and$top.v:19$4_Y
+
+  attribute \src "top.v:18"
+  wire $logic_and$top.v:18$2_Y
+
+  attribute \src "top.v:20"
+  wire $logic_and$top.v:20$6_Y
+
+  attribute \src "top.v:20"
+  wire $logic_not$top.v:20$5_Y
+
+  attribute \src "top.v:18"
+  wire $logic_or$top.v:18$3_Y
+
+  attribute \src "top.v:20"
+  wire $logic_or$top.v:20$7_Y
+
+  attribute \src "top.v:21"
+  attribute \unused_bits "1"
+  wire width 2 $or$top.v:21$8_Y
+
+  wire $procmux$10_Y
+
+  attribute \src "top.v:8"
+  wire input 5 \A
+
+  attribute \init 1'0
+  attribute \src "top.v:9"
+  wire output 6 \B
+
+  attribute \src "top.v:6"
+  wire input 4 \clk
+
+  attribute \src "top.v:3"
+  wire width 2 input 1 \x
+
+  attribute \src "top.v:4"
+  wire width 2 input 2 \y
+
+  attribute \src "top.v:5"
+  wire width 2 input 3 \z
+
+  attribute \src "top.v:19"
+  cell $and $and$top.v:19$4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \z
+    connect \Y $and$top.v:19$4_Y
+  end
+
+  attribute \src "top.v:18"
+  cell $logic_and $logic_and$top.v:18$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B \z
+    connect \Y $logic_and$top.v:18$2_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_and $logic_and$top.v:20$6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B $logic_not$top.v:20$5_Y
+    connect \Y $logic_and$top.v:20$6_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_not $logic_not$top.v:20$5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \z
+    connect \Y $logic_not$top.v:20$5_Y
+  end
+
+  attribute \src "top.v:18"
+  cell $logic_or $logic_or$top.v:18$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:18$2_Y
+    connect \Y $logic_or$top.v:18$3_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_or $logic_or$top.v:20$7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:20$6_Y
+    connect \Y $logic_or$top.v:20$7_Y
+  end
+
+  attribute \src "top.v:21"
+  cell $or $or$top.v:21$8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \x
+    connect \Y $or$top.v:21$8_Y
+  end
+
+  attribute \src "top.v:17"
+  cell $dff $procdff$14
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D $0\B[0:0]
+    connect \Q \B
+  end
+
+  attribute \src "top.v:18"
+  cell $mux $procmux$10
+    parameter \WIDTH 1
+    connect \A \B
+    connect \B $and$top.v:19$4_Y [0]
+    connect \S $logic_or$top.v:18$3_Y
+    connect \Y $procmux$10_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $mux $procmux$12
+    parameter \WIDTH 1
+    connect \A $procmux$10_Y
+    connect \B $or$top.v:21$8_Y [0]
+    connect \S $logic_or$top.v:20$7_Y
+    connect \Y $0\B[0:0]
+  end
+end

frontends/read_ilang_error/ilang.ilang

+# Generated by Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+autoidx 15
+attribute \cells_not_processed 1
+attribute \src "top.v:1"
+module \top
+  attribute \src "top.v:17"
+  wire $0\B[0:0]
+  attribute \src "top.v:19"
+  attribute \unused_bits "1"
+  wire width 2 $and$top.v:19$4_Y
+  attribute \src "top.v:18"
+  wire $logic_and$top.v:18$2_Y
+  attribute \src "top.v:20"
+  wire $logic_and$top.v:20$6_Y
+  attribute \src "top.v:20"
+  wire $logic_not$top.v:20$5_Y
+  attribute \src "top.v:18"
+  wire $logic_or$top.v:18$3_Y
+  attribute \src "top.v:20"
+  wire $logic_or$top.v:20$7_Y
+  attribute \src "top.v:21"
+  attribute \unused_bits "1"
+  wire width 2 $asdfasdfasfor$top.v:21$8_Y
+  wire $procmux$10_Y
+  attribute \src "top.v:8"
+  wire input 5 \A
+  attribute \init 1'0
+  attribute \src "top.v:9"
+  wire output 6 \B
+  attribute \src "top.v:6"
+  wire input 4 \clk
+  attribute \src "top.v:3"
+  wire width 2 input 1 \x
+  attribute \src "top.v:4"
+  wire width 2 input 2 \y
+  attribute \src "top.v:5"
+  wire width 2 input 3 \z
+  attribute \src "top.v:19"
+  cell $and $and$top.v:19$4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \z
+    connect \Y $and$top.v:19$4_Y
+  end
+  attribute \src "top.v:18"
+  cell $logic_and $logic_and$top.v:18$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B \z
+    connect \Y $logic_and$top.v:18$2_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_and $logic_and$top.v:20$6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B $logic_not$top.v:20$5_Y
+    connect \Y $logic_and$top.v:20$6_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_not $logic_not$top.v:20$5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \z
+    connect \Y $logic_not$top.v:20$5_Y
+  end
+  attribute \src "top.v:18"
+  cell $logic_or $logic_or$top.v:18$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:18$2_Y
+    connect \Y $logic_or$top.v:18$3_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_or $logic_or$top.v:20$7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:20$6_Y
+    connect \Y $logic_or$top.v:20$7_Y
+  end
+  attribute \src "top.v:21"
+  cell $or $or$top.v:21$8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \x
+    connect \Y $or$top.v:21$8_Y
+  end
+  attribute \src "top.v:17"
+  cell $dff $procdff$14
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D $0\B[0:0]
+    connect \Q \B
+  end
+  attribute \src "top.v:18"
+  cell $mux $procmux$10
+    parameter \WIDTH 1
+    connect \A \B
+    connect \B $and$top.v:19$4_Y [0]
+    connect \S $logic_or$top.v:18$3_Y
+    connect \Y $procmux$10_Y
+  end
+  attribute \src "top.v:20"
+  cell $mux $procmux$12
+    parameter \WIDTH 1
+    connect \A $procmux$10_Y
+    connect \B $or$top.v:21$8_Y [0]
+    connect \S $logic_or$top.v:20$7_Y
+    connect \Y $0\B[0:0]
+  end
+end

frontends/read_ilang_error/testbench.v

+module testbench;
+    reg [0:7] in;
+
+	reg patt_B = 0;
+	wire B;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[1:2]),
+	.y(in[3:4]),
+	.z(in[5:6]),
+	.clk(in[0]),
+	.A(in[7]),
+	.B(B)
+	);
+	
+	always @(negedge in[0]) begin
+    if (in[1:2] || in[3:4] && in[5:6])
+        patt_B <=  in[7] & in[5:6];
+    if (in[1:2] || in[3:4] && !in[5:6])
+        patt_B <=  in[7] | in[1:2];
+end
+	
+	assert_comb out_test(.A(patt_B), .B(B));
+
+endmodule

frontends/read_ilang_error/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+ 
+ initial begin
+    B = 0;
+ end
+
+`ifndef BUG
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+`else
+always @(posedge clk) begin
+    B =  z - y + x;
+end
+`endif
+
+endmodule

frontends/read_json_error/json1.json

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+          }
+        },
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+          }
+        }
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+    }
+  }
+}

frontends/read_json_error/json2.json

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+          }
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+    }
+  }
+}

frontends/read_json_error/json3.json

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+        },
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+        },
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+        }
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+          }
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+          }
+        }
+      }
+    }
+  }
+}

frontends/read_json_error/json4.json

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frontends/read_json_error/json5.json

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frontends/read_json_error/json6.json

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frontends/read_json_error/json7.json

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frontends/read_json_error/json8.json

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frontends/read_liberty_error/lib.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,pf);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib1.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : 2 ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib2.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!s)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib3.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+function : "(!A*)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/lib4.lib

+library (Cell_EX2) {
+technology (cmos);
+delay_model : table_lookup;
+capacitive_load_unit (1,f);
+pulling_resistance_unit : "1kohm";
+time_unit : "1ns";
+voltage_unit : "1V";
+current_unit : "1A";
+default_fanout_load : 0.0;
+default_inout_pin_cap : 0.0;
+default_input_pin_cap : 0.0;
+default_output_pin_cap : 0.0;
+input_threshold_pct_rise : 50.0;
+input_threshold_pct_fall : 50.0;
+output_threshold_pct_rise : 50.0;
+output_threshold_pct_fall : 50.0;
+slew_lower_threshold_pct_fall : 10.0;
+slew_lower_threshold_pct_rise : 10.0;
+slew_upper_threshold_pct_fall : 90.0;
+slew_upper_threshold_pct_rise : 90.0;
+
+lu_table_template (delay_template4x4) {
+variable_1 : input_net_transition;
+variable_2 : total_output_net_capacitance;
+index_1 ("1,2,3,4");
+index_2 ("1,2,3,4");
+}
+
+
+cell (top) {
+area : 2;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00376;
+rise_capacitance : 0.00376;
+fall_capacitance : 0.00377;
+rise_capacitance_range (0.00376 , 0.00376) ;
+fall_capacitance_range (0.00377 , 0.00377) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.08000;
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+cell (INVX2) {
+area : 3;
+cell_footprint : inv;
+pin (A) {
+direction : input ;
+capacitance : 0.00676;
+rise_capacitance : 0.00676;
+fall_capacitance : 0.00677;
+rise_capacitance_range (0.00676 , 0.00676) ;
+fall_capacitance_range (0.00677 , 0.00677) ;
+clock : false;
+max_transition : 1.0;
+}
+pin (Y) {
+direction : output;
+max_capacitance : 0.16000;
+function : "(!A)";
+timing () {
+related_pin : "A";
+timing_sense : negative_unate;
+cell_rise (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.05545, 0.08432, 0.13771, 0.24632", \
+"0.07093, 0.10601, 0.16334, 0.26969", \
+"0.09321, 0.13663, 0.20648, 0.32107", \
+"0.12336, 0.18027, 0.26781, 0.40737");
+}
+rise_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.09501, 0.14667, 0.25660, 0.48700", \
+"0.13380, 0.18147, 0.28263, 0.50271", \
+"0.19812, 0.25305, 0.35174, 0.55511", \
+"0.32615, 0.38683, 0.49515, 0.69333");
+}
+cell_fall (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.04962, 0.07644, 0.12297, 0.21732", \
+"0.06032, 0.09421, 0.14752, 0.24018", \
+"0.07225, 0.11581, 0.18296, 0.28919", \
+"0.08114, 0.13786, 0.22567, 0.36035");
+}
+fall_transition (delay_template4x4) {
+index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
+index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
+values ("0.08067, 0.12114, 0.20638, 0.38782", \
+"0.11950, 0.15830, 0.23419, 0.40548", \
+"0.19046, 0.23320, 0.31117, 0.46523", \
+"0.32214, 0.37613, 0.46164, 0.61834");
+}
+}
+}
+}
+
+}

frontends/read_liberty_error/libff.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "dff";
+ff("IQ", "IQN") {
+clocked_on : " CLK ";
+clear : " CLR ";
+}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_error/liblat.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "latch";
+latch(IQ, IQN) {
+enable : "CLK" ;
+clear : "CLR" ;}
+pin(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_error/liblat1.lib

+library(top) {
+
+ /* unit attributes */
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1uA";
+  pulling_resistance_unit : "1kohm";
+  leakage_power_unit : "1nW";
+  capacitive_load_unit(1,pf);
+
+/* positive edge triggered D flip-flop with active low reset */
+cell(top) {
+area : 972;
+cell_footprint : "latch";
+latch(IQ, IQN) {
+enable : "CLK" ;
+data_in : "D" ;
+clear : "CLR" ;}
+type ( BUS4 ) {
+ base_type : arraysss ;
+ data_type : bit ;
+ bit_width : 4 ;
+ bit_from : 0 ;
+ bit_to : 3 ;
+ downto :false ;
+}
+bus(D) {
+direction : input;
+capacitance : 0.0225;
+timing() { /* hold time constraint for a rising transition on G */
+timing_type : hold_rising;
+rise_constraint(scalar) { values("-0.298"); }
+fall_constraint(scalar) { values("-0.298"); }
+related_pin : "CLK";
+}
+timing() { /* setup time constraint for a rising transition on G */
+timing_type : setup_rising;
+rise_constraint(scalar) { values("0.018"); }
+fall_constraint(scalar) { values("0.018"); }
+related_pin : "CLK";
+}
+} /* end of pin D */
+pin ( CLK ) {
+direction : input;
+capacitance : 0.0585;
+clock : true;
+} /* end of pin CLK */
+pin ( CLR ) {
+direction : input;
+capacitance : 0.0135;
+} /* end of pin CLR */
+pin ( Q ) {
+direction : output;
+function : "IQ";
+timing () { /* propagation delay from rising edge of CLK to Q */
+timing_type : rising_edge;
+cell_rise(lu5x5) { values( "0.018" );}
+rise_transition(lu5x5) { values( "0.018" );}
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLK";
+} /* end of Q timing related to CLK */
+timing () { /* propagation delay from falling edge of clear to Q=0 */
+timing_type : clear;
+timing_sense : positive_unate;
+cell_fall(lu5x5) { values( "0.018" );}
+fall_transition(lu5x5) { values( "0.018" );}
+related_pin : "CLR";
+} /* end of Q timing related to CLR */
+} /* end of pin Q */
+} /* end of cell dff */
+
+}

frontends/read_liberty_error/liblat2.lib

+library (ExamBus) {
+date : "May 14, 2002";
+ revision : 2002.05;
+ bus_naming_style :"%s[%d]";/* Optional; this is the
+ default */
+type (bus4) {
+base_type : array;/* Required */
+data_type : bit;/* Required if base_type is array */
+bit_width : 4;/* Optional; default is 1 */
+bit_from : 0;/* Optional MSB; defaults to 0 */
+bit_to : 3;/* Optional LSB; defaults to 0 */
+downto : false;/* Optional; defaults to false */
+}
+cell (bused_cell) {
+area : 10;
+bus (A) {
+bus_type : bus4;
+direction : input;
+capacitance : 3;
+pin (A[0:2]) {
+capacitance : 2;
+}
+pin (A[3]) {
+ capacitance : 2.5;
+}
+}
+bus (B) {
+bus_type : bus4;
+capacitance : 2;
+}
+pin (E) {
+direction : input ;
+capacitance : 2 ;
+}
+bus(X) {
+bus_type : bus4;
+direction : output;
+capacitance : 1;
+pin (X[0:3]) {
+function : "A & B’";
+timing() {
+related_pin : "A B";
+/* A[0] and B[0] are related to X[0],
+A[1] and B[1] are related to X[1], etc. */
+}
+}
+}
+bus (Y) {
+bus_type : bus4;
+direction : output;
+capacitance : 1;
+pin (Y[0:3]) {
+function : "B";
+three_state : "!E";
+timing () {
+related_pin : "A[0:3] B E";
+}
+internal_power() {
+when: "E" ;
+related_pin : B ;
+power() {
+}
+}
+internal_power() {
+related_pin : B ;
+power() {
+}
+}
+}
+}
+bus (Z) {
+bus_type : bus4;
+direction : output;
+pin (Z[0:1]) {
+function : "!A[0:1]";
+timing () {
+related_pin : "A[0:1]";
+}
+internal_power() {
+related_pin  : "A[0:1]";
+power() {
+}
+}
+}
+pin (Z[2]) {
+function : "A[2]";
+timing () {
+related_pin : "A[2]";
+}
+internal_power() {
+related_pin : "A[0:1]";
+power() {
+}
+}
+}
+pin (Z[3]) {
+function : "!A[3]";
+timing () {
+related_pin : "A[3]";
+}
+internal_power() {
+related_pin : "A[0:1]";
+power() {
+}
+}
+}
+}
+pin_opposite("Y[0:1]","Z[0:1]");
+/* Y[0] is opposite to Z[0], etc. */
+pin_equal("Y[2:3] Z[2:3]");
+ /* Y[2], Y[3], Z[2], and Z[3] are equal */
+cell (bused_cell2) {
+area : 20;
+bus (A) {
+bus_type : bus41;
+direction : input;
+capacitance : 1;
+pin (A[0:3]) {
+capacitance : 2;
+}
+pin (A[3]) {
+capacitance : 2.5;
+}
+}
+bus (B) {
+bus_type : bus4;
+direction : input;
+capacitance : 2;
+}
+pin (E) {
+direction : input ;
+capacitance : 2 ;
+bus(X) {
+bus_type : bus4;
+direction : output;
+capacitance : 1;
+pin (X[0:3]) {
+function : "A & B’";
+timing() {
+related_pin : "A B";
+/* A[0] and B[0] are related to X[0],
+A[1] and B[1] are related to X[1], etc. */
+}
+}
+}
+}

regression/issue_00449/testbench.v → frontends/read_liberty_error/testbench.v

 module testbench;
-    reg clk;
+    reg a;
+
+	wire b;
 
     initial begin
-       // $dumpfile("testbench.vcd");
-       // $dumpvars(0, testbench);
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
 
-        #0 clk = 0;
+        #5 a = 0;
         repeat (10000) begin
-            #5 clk = 1;
-            #5 clk = 0;
+            #5 a = ~a;
         end
 
         $display("OKAY");
     end
 
-	wire b;
-
-	top uut (clk,b);
+    top uut (
+	.A(a),
+	.Y(b)
+	);
 
-	assert_X b_test(.clk(clk), .A(b));
+	assert_comb b_test(.A(~a),.B(b));
 
 endmodule

frontends/run.sh

@@ -10,34 +10,120 @@ cd $1/work_$2
 
 touch .start
 
-yosys -ql yosys.log ../../scripts/$2.ys
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
-sed -i 's/reg =/dummy =/' ./synth.v
+# cases where 'syntax error' or other errors are expected
+if echo "$1" | grep ".*_error"; then
 
-if [ -f "../../../../../techlibs/common/simcells.v" ]; then
-    COMMON_PREFIX=../../../../../techlibs/common
-else
-    COMMON_PREFIX=/usr/local/share/yosys
-fi
+	expected_string=""
+    #Change checked string for check other errors
+	if [ "$2" = "read_aiger_cant_interpret_first_char" ]; then
+		expected_string="ERROR: Line 80: cannot interpret first character"
+	elif [ "$2" = "read_aiger_unsup_aiger_file" ]; then
+		expected_string="ERROR: Unsupported AIGER file!"
+	elif [ "$2" = "read_aiger_invalid_aiger_header" ]; then
+		expected_string="ERROR: Invalid AIGER header"
+	elif [ "$2" = "read_aiger_cant_interpret_as_input" ]; then
+		expected_string="ERROR: Line 2 cannot be interpreted as an input!"
+	elif [ "$2" = "read_aiger_cant_interpret_as_and" ]; then
+		expected_string="ERROR: Line 6 cannot be interpreted as an AND!"
+	elif [ "$2" = "read_aiger_bad_state_property" ]; then
+		expected_string="ERROR: Line 4 cannot be interpreted as a bad state property!"
+	elif [ "$2" = "read_aiger_invalid_reset_literal" ]; then
+		expected_string="ERROR: Line 1 has invalid reset literal for latch!"
+	elif [ "$2" = "read_aiger_duplicate_definition" ]; then
+		expected_string="ERROR: Duplicate definition of module top!"
+	elif [ "$2" = "read_blif_syntax_error" ]; then
+		expected_string="ERROR: Syntax error in line"
+	elif [ "$2" = "read_blif_duplicate_defenition" ]; then
+		expected_string="ERROR: Duplicate definition of module "
+	elif [ "$2" = "read_ilang_parse_error" ]; then
+		expected_string="ERROR: Parser error in line "
+	elif [ "$2" = "read_json_nonstring_key" ]; then
+		expected_string="ERROR: Unexpected non-string key in JSON dict."
+	elif [ "$2" = "read_json_nonarray_bits_attr" ]; then
+		expected_string=" has non-array bits attribute."
+	elif [ "$2" = "read_json_unexpected_eof" ]; then
+		expected_string="ERROR: Unexpected EOF in JSON file."
+	elif [ "$2" = "read_json_invalid_direction" ]; then
+		expected_string="ERROR: JSON port node 'x' has invalid 'insdfasdfput' direction attribute."
+	elif [ "$2" = "read_json_no_bits" ]; then
+		expected_string=" has no bits attribute."
+	elif [ "$2" = "read_json_no_direction" ]; then
+		expected_string=" has no direction attribute."
+	elif [ "$2" = "read_json_unexpected_char" ]; then
+		expected_string="ERROR: Unexpected character in JSON file: "
+	elif [ "$2" = "verilog_defaults_missing_arg" ]; then
+		expected_string="ERROR: Command syntax error: Missing argument."
+	elif [ "$2" = "verilog_defaults_extra_arg" ]; then
+		expected_string="ERROR: Command syntax error: Extra argument."
+	elif [ "$2" = "verilog_defines_extra_arg" ]; then
+		expected_string="ERROR: Command syntax error: Extra argument."
+	elif [ "$2" = "read_liberty_invalid_bus_type" ]; then
+		expected_string="ERROR: Missing or invalid direction for bus B on cell bused_cell."
+	elif [ "$2" = "read_liberty_unsupp_type_for_bus" ]; then
+		expected_string="ERROR: Unknown or unsupported type for bus interface D on cell top."
+	elif [ "$2" = "read_liberty_bus_interface_only_in_lib_mode" ]; then
+		expected_string="ERROR: Error in cell top: bus interfaces are only supported in -lib mode."
+	elif [ "$2" = "read_liberty_latch_has_no_data_in" ]; then
+		expected_string="ERROR: Latch cell top has no data_in and/or enable attribute."
+	elif [ "$2" = "read_liberty_miss_func_on_output" ]; then
+		expected_string="ERROR: Missing function on output Y of cell top."
+	elif [ "$2" = "read_liberty_ff_has_no_next_stage_attr" ]; then
+		expected_string="ERROR: FF cell top has no next_state and/or clocked_on attribute."
+	elif [ "$2" = "read_liberty_parse_error_in_function" ]; then
+		expected_string="ERROR: Parser error in function expr "
+	elif [ "$2" = "read_liberty_cant_resolve_wire_name" ]; then
+		expected_string="ERROR: Can't resolve wire name s."
+	elif [ "$2" = "read_liberty_missing_direction" ]; then
+		expected_string="ERROR: Missing or invalid direction for pin A on cell top."
+	elif [ "$2" = "read_liberty_cant_open_input_file" ]; then
+		expected_string="ERROR: Can't open input file \`../libbbb.lib' for reading: No such file or directory"
+	elif [ "$2" = "read_liberty_redefenition_of_module" ]; then
+		expected_string="ERROR: Re-definition of cell/module top!"
+	fi
 
-iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
-if [ $? != 0 ] ; then
-    echo FAIL > ${1}_${2}.status
-    touch .stamp
-    exit 0
-fi
 
-if ! vvp -N testbench > testbench.log 2>&1; then
-	grep 'ERROR' testbench.log
-	echo FAIL > ${1}_${2}.status
-elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo FAIL > ${1}_${2}.status
+	if yosys -ql yosys.log ../../scripts/$2.ys; then
+		echo FAIL > ${1}_${2}.status
+	else
+		if  grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
+			echo PASS > ${1}_${2}.status
+		else
+			echo FAIL > ${1}_${2}.status
+		fi
+	fi
 else
-	echo PASS > ${1}_${2}.status
+
+
+	yosys -ql yosys.log ../../scripts/$2.ys
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+	sed -i 's/reg =/dummy =/' ./synth.v
+
+	if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+		COMMON_PREFIX=../../../../../techlibs/common
+	else
+		COMMON_PREFIX=/usr/local/share/yosys
+	fi
+
+	iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
+	fi
+
+	if ! vvp -N testbench > testbench.log 2>&1; then
+		grep 'ERROR' testbench.log
+		echo FAIL > ${1}_${2}.status
+	elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+		echo FAIL > ${1}_${2}.status
+	else
+		echo PASS > ${1}_${2}.status
+	fi
+
 fi
 
 touch .stamp

frontends/scripts/read_aiger_bad_state_property.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch1.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_cant_interpret_as_and.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff4.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_cant_interpret_as_input.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff3.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_cant_interpret_first_char.ys

+read_aiger -clk_name clk -module_name top ../aiger1.aiger
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_duplicate_definition.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
+read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_invalid_aiger_header.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff2.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_invalid_reset_literal.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch2.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_aiger_unsup_aiger_file.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff1.aiger
+
+synth -top top
+write_verilog synth.v

frontends/scripts/read_blif_duplicate_defenition.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+read_blif blif1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_blif_syntax_error.ys

+read_blif ../blif_e1.blif
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_blif blif5.blif
+write_verilog synth.v

frontends/scripts/read_ilang_parse_error.ys

+read_ilang ../ilang.ilang
+dump -n -o file1.il
+write_verilog synth.v

frontends/scripts/read_json_invalid_direction.ys

+read_json ../json4.json
+write_verilog synth.v

frontends/scripts/read_json_no_bits.ys

+read_json ../json3.json
+write_verilog synth.v

frontends/scripts/read_json_no_direction.ys

+read_json ../json2.json
+write_verilog synth.v

frontends/scripts/read_json_nonarray_bits_attr.ys

+read_json ../json7.json
+write_verilog synth.v

frontends/scripts/read_json_nonstring_key.ys

+read_json ../json8.json
+write_verilog synth.v

frontends/scripts/read_json_unexpected_char.ys

+read_json ../json1.json
+write_verilog synth.v

frontends/scripts/read_json_unexpected_eof.ys

+read_json ../json5.json
+write_verilog synth.v

frontends/scripts/read_liberty_bus_interface_only_in_lib_mode.ys

+read_liberty ../liblat1.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_cant_open_input_file.ys

+read_liberty ../libbbb.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_cant_resolve_wire_name.ys

+read_liberty ../lib2.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_ff_has_no_next_stage_attr.ys

+read_liberty ../libff.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_invalid_bus_type.ys

+read_liberty -lib ../liblat2.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_latch_has_no_data_in.ys

+read_liberty ../liblat.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_miss_func_on_output.ys

+read_liberty ../lib4.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_missing_direction.ys

+read_liberty ../lib1.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_parse_error_in_function.ys

+read_liberty ../lib3.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_redefenition_of_module.ys

+read_liberty ../lib.lib
+read_liberty ../lib.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/read_liberty_unsupp_type_for_bus.ys

+read_liberty -lib ../liblat1.lib
+synth -top top
+write_verilog synth.v

frontends/scripts/verilog_defaults_extra_arg.ys

+verilog_defaults -push -pop
+read_verilog
+proc
+write_verilog synth.v

frontends/scripts/verilog_defaults_missing_arg.ys

+verilog_defaults
+read_verilog
+proc
+write_verilog synth.v

frontends/scripts/verilog_defines_extra_arg.ys

+verilog_defines -aa
+read_verilog
+proc
+write_verilog synth.v

frontends/verilog_defaults_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_defaults_error/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG 
+    
+    always @(*)
+		Y = (S)? B : A;
+`else
+	
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG 
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG 
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y); 
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+	
+assign Y = D[S];
+ 
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+    
+    
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+    
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+    
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_defaults_error/top1.v

+module top1 (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+endmodule

frontends/verilog_defines_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_defines_error/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG 
+    
+    always @(*)
+		Y = (S)? B : A;
+`else
+	
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG 
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG 
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y); 
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+	
+assign Y = D[S];
+ 
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+    
+    
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+    
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+    
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

regression/Makefile

@@ -355,8 +355,8 @@ $(eval $(call template,issue_00873,issue_00873))
 #issue_00888
 $(eval $(call template,issue_00888,issue_00888))
 
-#pr_00896
-$(eval $(call template,pr_00896,pr_00896))
+#issue_00896
+$(eval $(call template,issue_00896,issue_00896))
 
 #issue_00922
 $(eval $(call template,issue_00922,issue_00922))
@@ -406,6 +406,70 @@ $(eval $(call template,issue_00993,issue_00993))
 #issue_00997
 $(eval $(call template,issue_00997,issue_00997))
 
+#issue_01002
+$(eval $(call template,issue_01002,issue_01002))
+
+#issue_01016
+$(eval $(call template,issue_01016,issue_01016))
+
+#issue_01022
+$(eval $(call template,issue_01022,issue_01022))
+
+#issue_01023
+$(eval $(call template,issue_01023,issue_01023))
+
+#issue_01033
+$(eval $(call template,issue_01033,issue_01033))
+
+#issue_01034
+$(eval $(call template,issue_01034,issue_01034))
+
+#issue_01040
+$(eval $(call template,issue_01040,issue_01040))
+
+#issue_01047
+$(eval $(call template,issue_01047,issue_01047))
+
+#issue_01063
+$(eval $(call template,issue_01063,issue_01063))
+
+#issue_01065
+$(eval $(call template,issue_01065,issue_01065))
+
+#issue_01070
+$(eval $(call template,issue_01070,issue_01070))
+
+#issue_01084
+$(eval $(call template,issue_01084,issue_01084))
+
+#issue_01091
+$(eval $(call template,issue_01091,issue_01091))
+
+#issue_01093
+$(eval $(call template,issue_01093,issue_01093))
+
+#issue_01115
+$(eval $(call template,issue_01115,issue_01115))
+
+#issue_01118
+$(eval $(call template,issue_01118,issue_01118))
+
+#issue_01128
+$(eval $(call template,issue_01128,issue_01128))
+
+#issue_01131
+$(eval $(call template,issue_01131,issue_01131))
+
+#issue_01132
+$(eval $(call template,issue_01132,issue_01132))
+
+#issue_01135
+$(eval $(call template,issue_01135,issue_01135))
+
+#issue_01144
+$(eval $(call template,issue_01144,issue_01144))
+
+
 
 
 .PHONY: all clean

regression/issue_01002/top.v

+module onehot(i_in, o_out);
+	parameter	LG = 7;
+	localparam	WID = (1<<LG);
+	//
+	input	wire	[WID-1:0]	i_in;
+	output	reg	[LG-1:0]	o_out;
+
+	//
+	integer	N;
+
+	always @(*)
+	begin
+		o_out = 0;
+		for(N=0; N<WID; N=N+1)
+		begin
+			if (i_in[N])
+				o_out = o_out | N[LG-1:0];
+		end
+	end
+endmodule

regression/issue_01016/top.v

+module mux_x(clk, in, en, out);
+   input clk, in, en;
+   output out;
+
+   assign out = en ? in : 1'bx;
+
+endmodule // latchx

regression/issue_01022/top.v

+module test(
+  output logic [31:0] b
+);
+
+  assign b = '1;
+
+endmodule

regression/issue_01023/top.v

+module mux_case_5_1(i, s, o);
+  input [4:0] i;
+  output o;
+  input [2:0] s;
+  \$shiftx  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd1),
+    .B_SIGNED(32'd0),
+    .B_WIDTH(32'sd0),
+    .Y_WIDTH(32'd1)
+  ) _34_ (
+    .A(i[4]),
+    .B(),
+    .Y(o)
+  );
+endmodule

regression/issue_01033/top.v

+module dram(input [3:0] i, output [4:0] o);
+`ifdef UNPACKED
+reg val [0:0];
+`else
+reg [0:0] val;
+`endif
+initial val[0] = 1'h1;
+assign o = i + val[0];
+endmodule

regression/issue_01034/top.v

+module dram(input [3:0] i, output [4:0] o);
+`ifdef UNPACKED
+reg val [0:0];
+`else
+reg [0:0] val;
+`endif
+initial val[0] = 1'h1;
+assign o = i + val[0];
+endmodule

regression/issue_01040/top.v

+module dut_sub(input clk, input [32:2] a, output [32:2] a_l);
+
+always @(posedge clk) a_l <= a;
+
+endmodule // dut_sub
+
+
+module dut(input clk, input[32:2] a, output [32:2] a_l);
+
+dut_sub sub(.clk(clk), .a(a), .a_l(a_l));
+
+endmodule // dut

regression/issue_01047/top.v

+module top (y, w);
+   output y;
+   input [2:0] w;
+   assign y = 1'b1 >> (w * (3'b110));
+endmodule

regression/issue_01063/top.v

+module top
+(
+input x,
+input y,
+input cin,
+
+output reg A,
+output cout
+);
+parameter X = 1;
+wire o;
+
+always @(posedge cin)
+A <= o;
+
+assign cout = cin? y : x;
+
+middle u_mid1 (.x(x),.o(o),.y(1'b0));
+middle u_mid2 (.x(x),.o(o),.y(1'b1));
+middle u_mid3 (.x(x),.o(o),.y(1'bX));
+middle u_mid4 (.x(x),.o(o),.y(1'bX));
+
+endmodule
+
+module middle
+(
+input x,
+input y,
+output o
+);
+
+urtl u_urtl (.x(x),.o(o),.y(y));
+endmodule
+
+module urtl
+(
+input x,
+input y,
+output o
+);
+
+assign o = x + y;
+endmodule

regression/issue_01065/top.v

+module top(input clk);
+wire ce = 1'b1;
+reg q = 1'b0;
+always @(posedge clk)
+    if (ce) q <= 1'b0;
+
+(* keep *)
+unknown_module u(.i(q));
+endmodule

regression/issue_01070/top.v

+module top(input clk, d, output reg q);
+wire ce = 1'b1;
+always @(negedge clk)
+    if (ce) q <= d;
+endmodule

regression/issue_01084/top.v

+module top;
+initial
+   if (0) $error("ASDF");
+endmodule

regression/issue_01091/top.v

+module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      o <= i[0*W+:W];
+     else
+      o <= i[1*W+:W];
+    else
+     if (s[1] == 1'b0)
+      o <= i[2*W+:W];
+end
+endmodule

regression/issue_01093/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+//assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

regression/issue_01115/top.v

+module top(input clk, output [32:0] o);
+assign o = 'bx;
+endmodule

regression/issue_01118/top.v

+module top(output [3:0] o);
+generate
+    genvar i;
+    for (i = 3; i >= 0; i = i-1) begin
+        assign o[i] = 1'b0;
+    end
+endgenerate
+endmodule

regression/issue_01128/top.v

+module test (
+    input i,
+    output o
+);
+    wire w1;
+    wire w2;
+
+    assign w1 = ~i;
+    assign w2 = w1;
+    assign o = ~w2;
+endmodule

regression/issue_01131/top.v

+module minimal;
+reg [7:0] q;
+initial begin
+q <= '81;
+end
+endmodule

regression/issue_01132/top.v

+module mux_if_bal_3_1 #(parameter N=3, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
+always @* begin
+    o <= {{W{{1'bx}}}};
+    if (s[0] == 1'b0)
+     if (s[1] == 1'b0)
+      o <= i[0*W+:W];
+     else
+      o <= i[1*W+:W];
+    else
+     if (s[1] == 1'b0)
+      o <= i[2*W+:W];
+end
+endmodule

regression/issue_01135/top.v

+module top(input [7:0] i, output o);
+always @*
+case (i[6:3])
+    4: o <= i[0];
+    3: o <= i[2];
+    7: o <= i[3];
+    default: o <= 1'b0;
+endcase
+endmodule

regression/issue_01144/top.v

+module top(input clk, d, output q);
+specify
+  // Fails:
+  (posedge clk => (q +: d)) = (3,1);
+  (/*posedge*/ clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+  (/*posedge*/ clk *> (q +: d)) = (3,1);
+
+  // Works:
+  (/*posedge*/ clk => q) = (3,1);
+  (/*posedge*/ clk *> q) = (3,1);
+endspecify
+endmodule

regression/run.sh

@@ -22,7 +22,11 @@ if [ "$1" = "issue_00089" ] ||\
    [ "$1" = "issue_00603" ] ||\
    [ "$1" = "issue_00635" ] ||\
    [ "$1" = "issue_00763" ] ||\
-   [ "$1" = "issue_00814" ]; then
+   [ "$1" = "issue_00814" ] ||\
+   [ "$1" = "issue_01063" ] ||\
+   [ "$1" = "issue_01093" ] ||\
+   [ "$1" = "issue_01131" ] ||\
+   [ "$1" = "issue_01144" ]; then
 
 	expected_string="syntax error"
     #Change checked string for check other errors
@@ -38,6 +42,12 @@ if [ "$1" = "issue_00089" ] ||\
 		expected_string="Invalid nesting"
 	elif [ "$1" = "issue_00814" ]; then
 		expected_string="is implicitly declared"
+	elif [ "$1" = "issue_01063" ]; then
+		expected_string="Gate cell u_mid8 not found in module top."
+	elif [ "$1" = "issue_01093" ]; then
+		expected_string="ERROR: Design has no top module, use the 'hierarchy' command to specify one."
+	elif [ "$1" = "issue_01131" ]; then
+		expected_string="ERROR: Value conversion failed"
 	fi
 
 	if yosys -ql yosys.log ../../scripts/$2.ys; then
@@ -94,7 +104,24 @@ elif [ "$1" = "issue_00502" ] ||\
 	 [ "$1" = "issue_00982" ] ||\
 	 [ "$1" = "issue_00987" ] ||\
 	 [ "$1" = "issue_00993" ] ||\
-	 [ "$1" = "issue_00997" ]; then
+	 [ "$1" = "issue_00997" ] ||\
+	 [ "$1" = "issue_01002" ] ||\
+	 [ "$1" = "issue_01016" ] ||\
+	 [ "$1" = "issue_01022" ] ||\
+	 [ "$1" = "issue_01023" ] ||\
+	 [ "$1" = "issue_01033" ] ||\
+	 [ "$1" = "issue_01034" ] ||\
+	 [ "$1" = "issue_01040" ] ||\
+	 [ "$1" = "issue_01047" ] ||\
+	 [ "$1" = "issue_01065" ] ||\
+	 [ "$1" = "issue_01070" ] ||\
+	 [ "$1" = "issue_01084" ] ||\
+	 [ "$1" = "issue_01091" ] ||\
+	 [ "$1" = "issue_01115" ] ||\
+	 [ "$1" = "issue_01118" ] ||\
+	 [ "$1" = "issue_01128" ] ||\
+	 [ "$1" = "issue_01132" ] ||\
+	 [ "$1" = "issue_01135" ]; then
 
 	expected_string=""
 	expected="1"
@@ -182,6 +209,43 @@ elif [ "$1" = "issue_00502" ] ||\
 		expected_string="_DFF_P_                        1"
 	elif [ "$1" = "issue_00997" ]; then
 		expected_string="h0"
+	elif [ "$1" = "issue_01002" ]; then
+		expected_string="Estimated number of LCs:         95"
+	elif [ "$1" = "issue_01016" ]; then
+		expected_string="cell \$mux \$ternary\$../top.v:5"
+	elif [ "$1" = "issue_01022" ]; then
+		expected_string="connect \\\b 32'11111111111111111111111111111111"
+	elif [ "$1" = "issue_01023" ]; then
+		expected_string="Continuing TECHMAP pass"
+	elif [ "$1" = "issue_01033" ]; then
+		expected_string="RAM64X1D         "
+		expected="0"
+	elif [ "$1" = "issue_01034" ]; then
+		expected_string="FDRE         "
+		expected="0"
+	elif [ "$1" = "issue_01040" ]; then
+		expected_string=".subckt dut_sub a\[2\]=a\[2\] a\[3\]=a\[3\] a\[4\]=a\[4\] a\[5\]=a\[5\] a\[6\]=a\[6\]"
+	elif [ "$1" = "issue_01047" ]; then
+		expected_string="assign y = ~(w\[0\] | w\[1\]);"
+	elif [ "$1" = "issue_01065" ]; then
+		expected_string="Driver-driver conflict for"
+		expected="0"
+	elif [ "$1" = "issue_01070" ]; then
+		expected_string="cell \$_DFF_N_"
+	elif [ "$1" = "issue_01084" ]; then
+		expected_string="Successfully finished Verilog frontend"
+	elif [ "$1" = "issue_01091" ]; then
+		expected_string="\$_MUX4_                         1"
+	elif [ "$1" = "issue_01115" ]; then
+		expected_string="connect \\\o 33'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
+	elif [ "$1" = "issue_01118" ]; then
+		expected_string="connect \\\o \[0\] 1'0"
+	elif [ "$1" = "issue_01128" ]; then
+		expected_string="\$_BUF_                          1"
+	elif [ "$1" = "issue_01132" ]; then
+		expected_string="\$_MUX4_                         1"
+	elif [ "$1" = "issue_01135" ]; then
+		expected_string="\$pmux                           1"
 	fi
 
 	yosys -ql yosys.log ../../scripts/$2.ys;
@@ -227,7 +291,7 @@ else
 		 [ "$1" = "issue_00589" ] ||\
 		 [ "$1" = "issue_00628" ]; then
 		iverilog_adds="$TECHLIBS_PREFIX/ice40/cells_sim.v"
-	elif [ "$1" = "pr_00896" ]; then
+	elif [ "$1" = "issue_00896" ]; then
 		iverilog_adds="$TECHLIBS_PREFIX/ecp5/cells_sim.v"
 	fi
 
@@ -237,6 +301,13 @@ else
     	touch .stamp
     	exit 0
 	fi
+	# cases where we do not run iverilog
+	if [ "$1" = "issue_00449" ]; then
+		echo PASS > ${1}_${2}.status
+    	touch .stamp
+    	exit 0
+	fi
+
 
 	iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
 	if [ $? != 0 ] ; then

regression/scripts/issue_00444.ys

 read_verilog -formal ../top.v
 hierarchy
+proc_prune
 proc_init
 proc_mux
 proc_dff

regression/scripts/issue_01002.ys

+read -sv ../top.v
+hierarchy -top onehot -chparam LG 7
+tee -a result.log synth_xilinx
+

regression/scripts/issue_01016.ys

+read_verilog -sv ../top.v
+proc
+wreduce -keepdc
+tee -a result.log dump
+

regression/scripts/issue_01022.ys

+read_verilog -sv ../top.v
+tee -a result.log dump
+

regression/scripts/issue_01023.ys

+read_verilog -icells ../top.v
+tee -a result.log techmap
+

regression/scripts/issue_01033.ys

+read_verilog ../top.v
+tee -a result.log synth_xilinx
+

regression/scripts/issue_01034.ys

+read_verilog ../top.v
+tee -a result.log synth_xilinx -nodram
+

regression/scripts/issue_01040.ys

+read_verilog ../top.v
+synth
+write_blif result.log

regression/scripts/issue_01047.ys

+read -formal ../top.v
+synth
+write_verilog -noattr result.log

regression/scripts/issue_01063.ys

+read -formal ../top.v
+proc
+fmcombine top u_mid1 u_mid8

regression/scripts/issue_01065.ys

+read_verilog ../top.v
+proc
+tee -o result.log opt -fast

regression/scripts/issue_01070.ys

+read_verilog ../top.v
+proc
+dff2dffe
+simplemap
+opt
+opt_rmdff
+stat
+tee -o result.log dump

regression/scripts/issue_01084.ys

+tee -o result.log read_verilog ../top.v

regression/scripts/issue_01091.ys

+read_verilog ../top.v
+proc
+opt
+techmap
+muxcover -nopartial
+tee -o result.log stat

regression/scripts/issue_01093.ys

+read_verilog ../top.v
+proc
+tee -o result.log sim

regression/scripts/issue_01115.ys

+read_verilog ../top.v
+proc
+tee -o result.log dump

regression/scripts/issue_01118.ys

+read_verilog ../top.v
+proc
+tee -o result.log dump

regression/scripts/issue_01128.ys

+read_verilog ../top.v
+insbuf
+# select just the $_BUF_ from w1 to w2 as @buf
+select -set buf w:w1 %coe1 w:w1 %d
+# set the keep attribute for the $_BUF_ from w1 to w2
+setattr -set keep 1 @buf
+opt_clean
+tee -o result.log stat

regression/scripts/issue_01131.ys

+tee -o result.log read_verilog ../top.v

regression/scripts/issue_01132.ys

+read_verilog ../top.v
+proc; opt; wreduce; simplemap; muxcover -mux4=150
+tee -o result.log stat

regression/scripts/issue_01135.ys

+read_verilog ../top.v
+proc; pmux2shiftx -norange; opt -full
+tee -o result.log stat

regression/scripts/issue_01144.ys

+read_verilog ../top.v
+tee -o result.log stat

simple/scripts/opt_merge_share_all.ys

 read_verilog -formal ../top.v
 hierarchy
+proc_prune
 proc_init
 proc_mux
 proc_dff