Merge pull request #42 from YosysHQ/xc7mux

Supporting tests for Xilinx MUXFx -- YosysHQ/yosys#1148

architecture/Makefile

@@ -71,6 +71,7 @@ $(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_b
 $(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
 ifeq ($(ENABLE_HEAVY_TESTS),1)
 $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
+$(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
 endif
 
 #greenpak4

architecture/run.sh

@@ -2,7 +2,6 @@
 
 set -x
 test -d $1
-test -f scripts/$2.ys
 
 rm -rf $1/work_$2
 mkdir $1/work_$2
@@ -25,7 +24,6 @@ if echo "$1" | grep ".*_error"; then
 		expected_string="ERROR: Invalid Xilinx -family setting: "
 	fi
 
-
 	if yosys -ql yosys.log ../../scripts/$2.ys; then
 		echo FAIL > ${1}_${2}.status
 	else
@@ -39,9 +37,15 @@ else
 
 	if [ -f ../run-test.sh ]; then
 		../run-test.sh
+		if [ $? != 0 ] ; then
+			echo FAIL > ${1}_${2}.status
+		else
+			echo PASS > ${1}_${2}.status
+		fi
 		touch .stamp
-		exit 0
+		exit
 	else
+		test -f scripts/$2.ys
 		yosys -ql yosys.log ../../scripts/$2.ys
 		if [ $? != 0 ] ; then
 			echo FAIL > ${1}_${2}.status

architecture/synth_xilinx_mux/assert_area.py

+#!/usr/bin/python3
+
+import glob
+import re
+import os
+
+re_mux = re.compile(r'mux_(index|case|if_bal|if_unbal)_(\d+)_(\d+)\.v')
+
+area = {}
+#             1  2  3  4  5  6 F7 F8
+area[2]   = [ 0, 0, 1, 0, 0, 0, 0, 0 ]
+area[3]   = [ 0, 0, 0, 0, 1, 0, 0, 0 ]
+area[4]   = [ 0, 0, 0, 0, 0, 0, 2, 1 ]
+area[5]   = [ 0, 0, 1, 0, 0, 0, 2, 1 ]
+area[7]   = [ 0, 0, 3, 0, 0, 0, 2, 1 ]
+area[8]   = [ 0, 0, 4, 0, 0, 0, 2, 1 ]
+area[9]   = [ 0, 0, 3, 0, 1, 0, 2, 1 ]
+area[15]  = [ 0, 0, 0, 0, 1, 3, 2, 1 ]
+area[16]  = [ 0, 0, 0, 0, 0, 4, 2, 1 ]
+area[17]  = [ 0, 0, 1, 0, 0, 4, 2, 1 ]
+area[31]  = [ 0, 0, 1, 0, 1, 7, 4, 2 ]
+area[32]  = [ 0, 0, 1, 0, 0, 8, 4, 2 ]
+area[33]  = [ 0, 0, 0, 0, 1, 8, 4, 2 ]
+area[63]  = [ 0, 0, 0, 0, 1,15,10, 5 ]
+area[64]  = [ 0, 0, 0, 0, 0,16,10, 5 ]
+area[65]  = [ 0, 0, 1, 0, 0,16,10, 5 ]
+area[127] = [ 0, 0, 4, 0, 1,31,18, 9 ]
+area[128] = [ 0, 0, 4, 0, 0,32,18, 9 ]
+area[129] = [ 0, 0, 3, 0, 1,32,18, 9 ]
+area[255] = [ 0, 0, 0, 0, 1,67,34,17 ]
+area[256] = [ 0, 0, 0, 0, 0,68,34,17 ]
+area[257] = [ 0, 0, 1, 0, 0,68,34,17 ]
+
+for fn in glob.glob('*.v'):
+    m = re_mux.match(fn)
+    if not m: continue
+
+    N,W = map(int, m.group(2,3))
+    assert N in area
+
+    bn,_ = os.path.splitext(fn)
+
+    with open(fn, 'a') as f:
+        assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
+        print('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd; %s";
+endmodule
+`endif
+''' % '; '.join(assert_area), file=f)

architecture/synth_xilinx_mux/run-test.sh

+#!/bin/bash
+set -e
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/generate.py -O generate_small.py -o /dev/null
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mux/common.py -O common.py -o /dev/null
+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
+python3 generate_small.py
+python3 generate_large.py
+python3 ../assert_area.py
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
+    -p 'design -copy-to __test __test; \
+        synth_xilinx -abc9 -widemux 4; \
+        design -copy-from __test *; \
+        select -assert-any __test; \
+        script -scriptwire __test/w:assert_area'\
+    -l ../../../../../techlibs/xilinx/cells_sim.v"
+
+# Spot tests for -widemux thresholds
+set +e
+../../../../../yosys -qp "synth_xilinx -widemux 1" 2> /dev/null
+if [ $? -eq 0 ]; then
+    echo "Expected error"
+    exit 1
+fi
+set -e
+
+../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-none t:MUXF*" mux_if_bal_2_1.v
+../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 1 t:MUXF7" mux_if_bal_2_1.v
+
+../../../../../yosys -qp "synth_xilinx -widemux 5; select -assert-none t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 4; select -assert-none t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 3; select -assert-count 6 t:MUXF*" mux_case_3_3.v
+../../../../../yosys -qp "synth_xilinx -widemux 2; select -assert-count 6 t:MUXF*" mux_case_3_3.v
+
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 9; select -assert-none t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 8; select -assert-none t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 7; select -assert-count 15 t:MUXF*" mux_index_7_5.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 6; select -assert-count 15 t:MUXF*" mux_index_7_5.v
+
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 18; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 17; select -assert-none t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 16; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v
+../../../../../yosys -qp "synth_xilinx -nowidelut -widemux 15; select -assert-count 24 t:MUXF*" mux_if_unbal_16_8.v