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lvzhengyang
yosys-tests
Commits
68d81606
Commit
68d81606
authored
Jun 29, 2020
by
Miodrag Milanovic
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Fixed pmgen generate scripts
parent
6af741f6
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11 deletions
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simple/test_pmgen/test_pmgen_generate_eqpmux.ys
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-2
simple/test_pmgen/test_pmgen_generate_ice40_dsp.ys
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-3
simple/test_pmgen/test_pmgen_generate_reduce.ys
+0
-2
simple/test_pmgen/test_pmgen_generate_xilinx_srl_fixed.ys
+1
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simple/test_pmgen/test_pmgen_generate_xilinx_srl_variable.ys
+0
-2
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simple/test_pmgen/test_pmgen_generate_eqpmux.ys
View file @
68d81606
read_verilog ../top.v
proc
test_pmgen -generate eqpmux
test_pmgen -generate eqpmux
simple/test_pmgen/test_pmgen_generate_ice40_dsp.ys
View file @
68d81606
read_verilog ../top.v
proc
test_pmgen -generate ice40_dsp
test_pmgen -generate ice40_dsp
simple/test_pmgen/test_pmgen_generate_reduce.ys
View file @
68d81606
read_verilog ../top.v
proc
test_pmgen -generate reduce
test_pmgen -generate reduce
simple/test_pmgen/test_pmgen_generate_xilinx_srl_fixed.ys
View file @
68d81606
read_verilog ../top.v
read_verilog -lib +/xilinx/cells_sim.v
proc
test_pmgen -generate xilinx_srl.fixed
test_pmgen -generate xilinx_srl.fixed
simple/test_pmgen/test_pmgen_generate_xilinx_srl_variable.ys
View file @
68d81606
read_verilog ../top.v
proc
test_pmgen -generate xilinx_srl.variable
test_pmgen -generate xilinx_srl.variable
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