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yosys-tests
Unverified Commit 64ab84a7 by Miodrag Milanović Committed by GitHub
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Merge pull request #81 from SergeyDegtyar/review_frontends_group 

Review frontends group
parents cfd1c5c9 45df44f0
Showing with 1565 additions and 6877 deletions
frontends/.gitignore
*/work_*/
/.stamp
/run-test.mk
frontends/Makefile
all: work
touch .stamp
PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
clean::
rm -f .stamp
all::
define template
$(foreach design,$(1),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
run-test.mk: ../generate.py
@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
$(design)/work_$(script)/.stamp:
bash run.sh $(design) $(script)
clean::
rm -rf $(design)/work_$(script)
))
endef
#read_blif
$(eval $(call template,read_blif,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_and_or,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_fsm,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_logic,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_mem,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_mux,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_pmux,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_tri,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_eblif,read_blif_eblif))
$(eval $(call template,read_blif_error, read_blif_syntax_error read_blif_duplicate_defenition ))
#read_ilang
$(eval $(call template,read_ilang,read_ilang read_ilang_selected read_ilang_overwrite read_ilang_nooverwrite read_ilang_lib))
$(eval $(call template,read_ilang_fsm,read_ilang read_ilang_selected read_ilang_overwrite read_ilang_nooverwrite read_ilang_lib))
$(eval $(call template,read_ilang_mem,read_ilang read_ilang_selected read_ilang_overwrite read_ilang_nooverwrite read_ilang_lib))
$(eval $(call template,read_ilang_mux,read_ilang read_ilang_selected read_ilang_overwrite read_ilang_nooverwrite read_ilang_lib))
$(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected read_ilang_overwrite read_ilang_nooverwrite read_ilang_lib))
$(eval $(call template,read_ilang_error,read_ilang_parse_error))
#read_json
$(eval $(call template,read_json,read_json))
$(eval $(call template,read_json_fsm,read_json))
$(eval $(call template,read_json_logic,read_json))
$(eval $(call template,read_json_mem,read_json_mem))
$(eval $(call template,read_json_mux,read_json))
$(eval $(call template,read_json_tri,read_json))
$(eval $(call template,read_json_error, read_json_nonstring_key read_json_nonarray_bits_attr read_json_unexpected_eof read_json_invalid_direction read_json_no_bits read_json_no_direction read_json_unexpected_char ))
#read_liberty read_liberty_lib
$(eval $(call template,read_liberty,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_arith,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_np,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_pn,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_ff_pp,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_latch,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_latch_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_diff_inv,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_tri,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_tech,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_error, read_liberty_invalid_bus_type read_liberty_unsupp_type_for_bus read_liberty_bus_interface_only_in_lib_mode read_liberty_latch_has_no_data_in read_liberty_miss_func_on_output read_liberty_ff_has_no_next_stage_attr read_liberty_parse_error_in_function read_liberty_cant_resolve_wire_name read_liberty_missing_direction read_liberty_cant_open_input_file read_liberty_redefenition_of_module ))
#read_aiger
$(eval $(call template,read_aiger,read_aiger read_aiger_proc read_aiger_ascii read_aiger_module read_aiger_map read_aiger_clk read_aiger_clk_module ))
$(eval $(call template,read_aiger_latch,read_aiger_aig))
$(eval $(call template,read_aiger_logic,read_aiger_aig))
$(eval $(call template,read_aiger_ff,read_aiger_aig))
$(eval $(call template,read_aiger_mult,read_aiger_aig))
$(eval $(call template,read_aiger_error, read_aiger_cant_interpret_first_char read_aiger_unsup_aiger_file read_aiger_invalid_aiger_header read_aiger_cant_interpret_as_input read_aiger_cant_interpret_as_and read_aiger_bad_state_property read_aiger_invalid_reset_literal read_aiger_duplicate_definition ))
#read
# read_vhdl87 read_vhdl93 read_vhdl2k read_vhdl2008 read_vhdl - ERROR: This version of Yosys is built without Verific support.
$(eval $(call template,read,read_vlog95 read_vlog2k read_sv2005 read_sv2009 read_sv2012 read_sv read_formal read_define read_define_value read_undef read_incdir read_noverific))
#read_verilog
$(eval $(call template,read_verilog,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_noautowire read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_nopp read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify ))
$(eval $(call template,read_verilog_string,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_noautowire read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_nopp read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_mem,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_noassert read_verilog_noassume read_verilog_noautowire read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_fsm,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_noautowire read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_logic,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_noautowire read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_ff_edge,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_noautowire read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_task_func,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_dpi,read_verilog_sv read_verilog_sv_ast1 read_verilog_sv_ast2))
$(eval $(call template,read_verilog_param_defparam,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_assert,read_verilog_assert read_verilog_assert_ast1 read_verilog_assert_ast2))
$(eval $(call template,read_verilog_real_value_shift_concat,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_comparison,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_div_mod,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_for_while,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_generate,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
$(eval $(call template,read_verilog_attributes,read_verilog read_verilog_assert_assumes read_verilog_assume_asserts read_verilog_debug read_verilog_defer read_verilog_dname read_verilog_dname_value read_verilog_dump_ast1 read_verilog_dump_ast2 read_verilog_dump_rtlil read_verilog_dump_vlog1 read_verilog_dump_vlog2 read_verilog_formal read_verilog_icells read_verilog_idir read_verilog_i_dir read_verilog_lib read_verilog_mem2reg read_verilog_noassert read_verilog_noassume read_verilog_nodpi read_verilog_no_dump_ptr read_verilog_nolatches read_verilog_nomem2reg read_verilog_nomeminit read_verilog_noopt read_verilog_nooverwrite read_verilog_norestrict read_verilog_overwrite read_verilog_ppdump read_verilog_setattr read_verilog_sv read_verilog_yydebug read_verilog_specify))
#verilog_defaults
$(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push verilog_defaults_pop verilog_defaults_clear))
$(eval $(call template,verilog_defaults_error,verilog_defaults_missing_arg verilog_defaults_extra_arg))
#verilog_defines
$(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
$(eval $(call template,verilog_defines_error,verilog_defines_extra_arg))
#verilog_lexer
$(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))
$(eval $(call template,verilog_lexer_package,verilog_lexer))
$(eval $(call template,verilog_lexer_interface_logic,verilog_lexer))
$(eval $(call template,verilog_lexer_casez,verilog_lexer))
$(eval $(call template,verilog_lexer_automatic_task,verilog_lexer))
$(eval $(call template,verilog_lexer_unique_priority,verilog_lexer))
$(eval $(call template,verilog_lexer_always_ff_latch,verilog_lexer))
$(eval $(call template,verilog_lexer_assert_assume_restrict,verilog_lexer_assert))
#../top.v:88: ERROR: syntax error, unexpected TOK_TYPEDEF
#$(eval $(call template,verilog_lexer_enum_typedef,verilog_lexer))
#../top.v:90: ERROR: syntax error, unexpected TOK_SUPPLY1
#$(eval $(call template,verilog_lexer_supply,verilog_lexer))
include run-test.mk
.PHONY: all clean
frontends/common.v deleted 100644 → 0
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
frontends/read/read_define.ys 0 → 100644
read -formal ../top.v
read -define MACRO
frontends/read/read_define_value.ys 0 → 100644
read -formal ../top.v
read -define MACRO=1
frontends/read/read_formal.ys 0 → 100644
read -formal ../top.v
frontends/read/read_incdir.ys 0 → 100644
read -formal ../top.v
read -incdir ../include_dir
frontends/read/read_sv2005.ys 0 → 100644
read -sv2005 ../top.v
frontends/read/read_sv2009.ys 0 → 100644
read -sv2009 ../top.v
frontends/read/read_sv2012.ys 0 → 100644
read -sv2012 ../top.v
frontends/read/read_undef.ys 0 → 100644
read -formal ../top.v
read -define MACRO
read -undef MACRO
frontends/scripts/read_formal.ys → frontends/read/read_vhdl.disable
read -formal ../top.v
read -vhdl ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
......
frontends/read/read_vhdl.ys 0 → 100644
read -vhdl ../top.vhd
frontends/scripts/read_define.ys → frontends/read/read_vhdl2k.disable
read -formal ../top.v
read -define MACRO
read -vhdl2k ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
......
frontends/read/read_vhdl2k.ys 0 → 100644
read -vhdl2k ../top.vhd
frontends/scripts/read_define_value.ys → frontends/read/read_vhdl87.disable
read -formal ../top.v
read -define MACRO=1
read -vhdl87 ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
......
frontends/read/read_vhdl87.ys 0 → 100644
read -vhdl87 ../top.vhd
frontends/scripts/read_incdir.ys → frontends/read/read_vhdl93.disable
read -formal ../top.v
read -incdir ../include_dir
read -vhdl93 ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
......
frontends/read/read_vhdl93.ys 0 → 100644
read -vhdl93 ../top.vhd
frontends/read/read_vlog2k.ys 0 → 100644
read -vlog2k ../top.v
frontends/read/read_vlog95.ys 0 → 100644
read -vlog95 ../top.v
frontends/read/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out;
wire patt_carry_out;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign patt_out = in[1] + in[2];
assign patt_carry_out = in[0] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
frontends/read/top.v
......@@ -9,12 +9,7 @@ module top
output cout
);
`ifndef BUG
assign A = y + cin;
assign cout = x + A;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/scripts/read_aiger.ys → frontends/read_aiger/read_aiger.ys
......@@ -3,7 +3,8 @@ aigmap
write_aiger aiger.aiger
design -reset
read_aiger aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends/read_aiger/read_aiger_aig.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_ff.aig
select -assert-count 4 t:$_AND_
select -assert-count 1 t:$_DFF_P_
select -assert-count 4 t:$_NOT_
select -assert-none t:$_AND_ t:$_DFF_P_ t:$_NOT_ %% t:* %D
frontends/scripts/read_aiger_ascii.ys → frontends/read_aiger/read_aiger_ascii.ys
......@@ -3,7 +3,8 @@ aigmap
write_aiger -ascii aiger.aiger
design -reset
read_aiger aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends/read_aiger/read_aiger_bad_state_property_fail.pat 0 → 100644
ERROR: Line 4 cannot be interpreted as a bad state property!
frontends/read_aiger/read_aiger_cant_interpret_as_and_fail.pat 0 → 100644
ERROR: Line 6 cannot be interpreted as an AND!
frontends/read_aiger/read_aiger_cant_interpret_as_input_fail.pat 0 → 100644
ERROR: Line 2 cannot be interpreted as an input!
frontends/read_aiger/read_aiger_clk.ys 0 → 100644
read_aiger -clk_name clk ../aiger_ff.aig
select -assert-count 4 t:$_AND_
select -assert-count 1 t:$_DFF_P_
select -assert-count 4 t:$_NOT_
select -assert-none t:$_AND_ t:$_DFF_P_ t:$_NOT_ %% t:* %D
frontends/scripts/read_aiger_clk_module.ys → frontends/read_aiger/read_aiger_clk_module.ys
......@@ -3,7 +3,8 @@ aigmap
write_aiger aiger.aiger
design -reset
read_aiger -clk_name clk -module_name top aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends/read_aiger/read_aiger_duplicate_definition_fail.pat 0 → 100644
ERROR: Duplicate definition of module top!
frontends/read_aiger/read_aiger_invalid_reset_literal_fail.pat 0 → 100644
ERROR: Line 1 has invalid reset literal for latch!
frontends/read_aiger/read_aiger_latch.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_latch.aig
stat
select -assert-count 1 t:$_DFF_P_
select -assert-count 1 t:$_NOT_
select -assert-none t:$_DFF_P_ t:$_NOT_ %% t:* %D
frontends/read_aiger/read_aiger_logic.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_logic.aig
select -assert-count 3 t:$_AND_
select -assert-count 4 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends/scripts/read_aiger_map.ys → frontends/read_aiger/read_aiger_map.ys
......@@ -3,7 +3,8 @@ aigmap
write_aiger aiger.aiger
design -reset
read_aiger -map aig.map aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends/scripts/read_aiger_module.ys → frontends/read_aiger/read_aiger_module.ys
......@@ -3,7 +3,8 @@ aigmap
write_aiger aiger.aiger
design -reset
read_aiger -module_name top aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends/read_aiger/read_aiger_mult.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_mult.aig
stat
select -assert-count 8 t:$_AND_
select -assert-count 2 t:$dff
select -assert-count 9 t:$_NOT_
select -assert-none t:$_AND_ t:$dff t:$_NOT_ %% t:* %D
frontends/scripts/read_aiger_proc.ys → frontends/read_aiger/read_aiger_proc.ys
......@@ -4,7 +4,8 @@ aigmap
write_aiger aiger.aiger
design -reset
read_aiger aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends/read_aiger/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out;
wire patt_carry_out;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign patt_out = in[1] + in[2];
assign patt_carry_out = in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
frontends/read_aiger/top.v
......@@ -9,12 +9,7 @@ module top
output cout
);
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_aiger_ff/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg n1,n2 = 0;
wire n3,n3_inv;
reg n3p;
wire n3ip;
top uut (
.clk (clk ),
.__1__ (n1 ),
.__2__ (n2 ),
.__3__ (n3 ),
.__3b__ (n3_inv )
);
always @(posedge clk) begin
#3;
n1 <= n1 + 1;
#1;
n2 <= n2 + 1;
end
wire _0_;
wire n4p;
assign _0_ = ~(n3p ^ n1);
assign n4p = n2 & ~(_0_);
assign n3ip = ~n3p;
always @(posedge clk)
n3p <= n4p;
assert_dff dff_test(.clk(clk), .test(n3), .pat(n3p));
endmodule
frontends/read_aiger_latch/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
reg lat = 0;
top uut (
.clk (en ),
//.__1__ (dinA ),
.__1b__ (doutB )
);
always @(posedge en) begin
#3;
dinA <= dinA + 1;
end
always @(* )
if ( en )
lat <= dinA;
assert_dff lat_test(.clk(en), .test(doutB), .pat(lat));
endmodule
frontends/read_aiger_logic/testbench.v deleted 100644 → 0
module testbench;
reg [0:1] in;
wire pat,pat1;
wire c,s;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.c(c),
.s(s),
.x(in[0]),
.y(in[1])
);
assign pat = in[1] ^ in[0];
assign pat1 = in[1] & in[0];
assert_comb out_test(.A(pat), .B(s));
assert_comb out1_test(.A(pat1), .B(c));
endmodule
frontends/read_aiger_mult/testbench.v deleted 100644 → 0
module testbench;
reg [0:1] in;
wire pat,pat1;
wire c,s;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
endmodule
frontends/read_aiger_s2c/testbench.v deleted 100644 → 0
module testbench;
reg [0:1] in;
wire pat,pat1;
wire c,s;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
endmodule
frontends/scripts/read_blif.ys → frontends/read_blif/read_blif.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_and_or.ys 0 → 100644
read_verilog ../top_and_or.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 1 t:$dff
select -assert-count 11 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/scripts/read_blif_attr.ys → frontends/read_blif/read_blif_attr.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_attr_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_attr_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends/scripts/read_blif_buf.ys → frontends/read_blif/read_blif_buf.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
stat
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_buf_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_buf_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends/scripts/read_blif_cname.ys → frontends/read_blif/read_blif_cname.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_cname_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_cname_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends/scripts/read_blif_conn.ys → frontends/read_blif/read_blif_conn.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_conn_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_conn_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends/read_blif/read_blif_duplicate_defenition_fail.pat 0 → 100644
ERROR: Duplicate definition of module top in line 3!
frontends/scripts/read_blif_duplicate_defenition.ys → frontends/read_blif/read_blif_duplicate_defenition_fail.ys
......@@ -2,8 +2,3 @@ read_verilog ../top.v
synth -top top
write_blif blif1.blif
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/read_blif/read_blif_eblif.ys 0 → 100644
read_blif -wideports ../eblif.eblif
stat
select -assert-count 1 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 17 t:$dff
select -assert-count 58 t:$lut
#select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_logic.ys 0 → 100644
read_verilog ../top_logic.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 4 t:$dff
select -assert-count 6 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends/scripts/read_blif_param.ys → frontends/read_blif/read_blif_param.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_param_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_param_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends/read_blif/read_blif_pmux.ys 0 → 100644
read_verilog ../top_pmux.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 4 t:$dff
select -assert-count 4 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/scripts/read_blif_sop.ys → frontends/read_blif/read_blif_sop.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$sop
select -assert-none t:$dff t:$sop %% t:* %D
frontends/read_blif/read_blif_sop_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$sop
select -assert-none t:$dff t:$sop %% t:* %D
frontends/read_blif/read_blif_sop_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
stat
select -assert-count 58 t:$sop
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$sop t:$paramod\mux4\dw?4 %% t:* %D
frontends/read_blif/read_blif_tri.ys 0 → 100644
read_verilog ../top_tri.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
frontends/scripts/read_blif_wideports.ys → frontends/read_blif/read_blif_wideports.ys
......@@ -3,8 +3,8 @@ synth -top top
write_blif blif1.blif
design -reset
read_blif -wideports blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_wideports_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -wideports blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends/read_blif/read_blif_wideports_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -wideports blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends/read_blif/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
frontends/read_blif/top.v
......@@ -7,21 +7,17 @@ module top
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_blif_and_or/top.v → frontends/read_blif/top_and_or.v
......@@ -8,22 +8,16 @@ module top
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_blif_logic/top.v → frontends/read_blif/top_logic.v
......@@ -7,15 +7,14 @@ module top
output reg A,
output reg cout
);
reg A1,cout1;
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A1 <= ~y + &cin;
end
......@@ -29,8 +28,5 @@ end
always @(posedge x) begin
cout <= cout1&cin~|y;
end
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
frontends/read_blif_mem/top.v → frontends/read_blif/top_mem.v
......@@ -17,11 +17,7 @@ module top
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
......@@ -35,11 +31,7 @@ module top
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......
frontends/read_blif_mux/top.v → frontends/read_blif/top_mux.v
......@@ -2,15 +2,9 @@ module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
......@@ -30,11 +24,7 @@ begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
......@@ -58,11 +48,7 @@ begin
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
......
frontends/read_blif_tri/top.v → frontends/read_blif/top_tri.v
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
......
frontends/read_blif_and_or/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
frontends/read_blif_eblif/testbench.v deleted 100644 → 0
module testbench;
reg a;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.a(a),
.b(b)
);
assert_comb b_test(.A(1'bx),.B(b));
endmodule
frontends/read_blif_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_blif_logic/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
frontends/read_blif_logic/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_blif_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_blif_mux/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_blif_pmux/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] S = 0;
wire [3:0] Y;
top uut (
.C (clk),
.S (S ),
.Y (Y )
);
always @(posedge clk) begin
//#3;
S <= S + 1;
end
assert_tri m16_test(.en(clk), .A(1'b1), .B(Y[0]|Y[1]|Y[2]|Y[3]));
endmodule
frontends/read_blif_pmux/top.v deleted 100644 → 0
module top(C, S, Y);
input C;
input [1:0] S;
output reg [3:0] Y;
initial Y = 0;
always @(posedge C) begin
case (S)
2'b00: Y <= 4'b0001;
2'b01: Y <= 4'b0010;
2'b10: Y <= 4'b0100;
2'b11: Y <= 4'b1000;
endcase
end
endmodule
frontends/read_blif_tri/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
frontends/read_ilang/read_ilang.ys 0 → 100644
read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
select -assert-count 1 t:$and
select -assert-count 1 t:$dff
select -assert-count 2 t:$logic_and
select -assert-count 1 t:$logic_not
select -assert-count 2 t:$logic_or
select -assert-count 2 t:$mux
select -assert-count 1 t:$or
select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D
frontends/read_ilang/read_ilang_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
stat
select -assert-count 1 t:$add
select -assert-count 2 t:$dff
select -assert-count 33 t:$eq
select -assert-count 2 t:$gt
select -assert-count 1 t:$logic_and
select -assert-count 3 t:$logic_or
select -assert-count 19 t:$mux
select -assert-count 1 t:$not
select -assert-count 1 t:$pmux
#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D
frontends/scripts/read_ilang_lib.ys → frontends/read_ilang/read_ilang_lib.ys
......@@ -5,6 +5,4 @@ dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -lib ilang.ilang
read_ilang ilang.ilang
dump -n -o file1.il
write_verilog synth.v
frontends/scripts/read_ilang_nooverwrite.ys → frontends/read_ilang/read_ilang_lib_fsm.ys
read_verilog ../top.v
read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -nooverwrite ilang.ilang
read_ilang -lib ilang.ilang
dump -n -o file1.il
write_verilog synth.v
frontends/scripts/read_ilang.ys → frontends/read_ilang/read_ilang_lib_tri.ys
read_verilog ../top.v
read_verilog ../top_tri.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -lib ilang.ilang
read_ilang ilang.ilang
dump -n -o file1.il
write_verilog synth.v
frontends/read_ilang/read_ilang_mem.ys 0 → 100644
read_verilog ../top_mem.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
stat
select -assert-count 2 t:$dff
select -assert-count 1 t:$mem
select -assert-count 10 t:$mux
select -assert-none t:$dff t:$mem t:$mux %% t:* %D
frontends/read_ilang/read_ilang_mux.ys 0 → 100644
read_verilog ../top_mux.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
stat
select -assert-count 1 t:$shiftx
select -assert-count 1 t:$mux
select -assert-count 12 t:$eq
select -assert-count 2 t:$pmux
frontends/read_ilang/read_ilang_nooverwrite.ys 0 → 100644
read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -nooverwrite ilang.ilang
dump -n -o file1.il
select -assert-count 1 t:$and
select -assert-count 1 t:$dff
select -assert-count 2 t:$logic_and
select -assert-count 1 t:$logic_not
select -assert-count 2 t:$logic_or
select -assert-count 2 t:$mux
select -assert-count 1 t:$or
select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D
frontends/read_ilang/read_ilang_nooverwrite_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -nooverwrite ilang.ilang
dump -n -o file1.il
stat
select -assert-count 1 t:$add
select -assert-count 2 t:$dff
select -assert-count 33 t:$eq
select -assert-count 2 t:$gt
select -assert-count 1 t:$logic_and
select -assert-count 3 t:$logic_or
select -assert-count 19 t:$mux
select -assert-count 1 t:$not
select -assert-count 1 t:$pmux
#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D
frontends/read_ilang/read_ilang_overwrite.ys 0 → 100644
read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -overwrite ilang.ilang
dump -n -o file1.il
select -assert-count 1 t:$and
select -assert-count 1 t:$dff
select -assert-count 2 t:$logic_and
select -assert-count 1 t:$logic_not
select -assert-count 2 t:$logic_or
select -assert-count 2 t:$mux
select -assert-count 1 t:$or
select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D
frontends/read_ilang/read_ilang_overwrite_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -overwrite ilang.ilang
dump -n -o file1.il
stat
select -assert-count 1 t:$add
select -assert-count 2 t:$dff
select -assert-count 33 t:$eq
select -assert-count 2 t:$gt
select -assert-count 1 t:$logic_and
select -assert-count 3 t:$logic_or
select -assert-count 19 t:$mux
select -assert-count 1 t:$not
select -assert-count 1 t:$pmux
#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D
frontends/read_ilang/read_ilang_parse_error_fail.pat 0 → 100644
ERROR: Parser error in line 110: ilang error: wire $or$top.v:21$8_Y not found
frontends/scripts/read_ilang_selected.ys → frontends/read_ilang/read_ilang_selected.ys
......@@ -6,4 +6,13 @@ write_ilang -selected ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
write_verilog synth.v
select -assert-count 1 t:$and
select -assert-count 1 t:$dff
select -assert-count 2 t:$logic_and
select -assert-count 1 t:$logic_not
select -assert-count 2 t:$logic_or
select -assert-count 2 t:$mux
select -assert-count 1 t:$or
select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D
frontends/read_ilang/read_ilang_selected_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
memory
dump -o file.il
write_ilang -selected ilang.ilang
design -reset
read_ilang ilang.ilang
dump -n -o file1.il
stat
select -assert-count 1 t:$add
select -assert-count 2 t:$dff
select -assert-count 33 t:$eq
select -assert-count 2 t:$gt
select -assert-count 1 t:$logic_and
select -assert-count 3 t:$logic_or
select -assert-count 19 t:$mux
select -assert-count 1 t:$not
select -assert-count 1 t:$pmux
#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D
frontends/scripts/read_ilang_overwrite.ys → frontends/read_ilang/read_ilang_tri.ys
read_verilog ../top.v
read_verilog ../top_tri.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
read_ilang -overwrite ilang.ilang
read_ilang ilang.ilang
dump -n -o file1.il
write_verilog synth.v
stat
select -assert-count 2 t:$mux
frontends/read_ilang/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
frontends/read_ilang/top.v
......@@ -8,22 +8,16 @@ module top
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_json_mem/top.v → frontends/read_ilang/top_mem.v
......@@ -7,38 +7,32 @@ module top
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......@@ -48,5 +42,5 @@ module top
q_b <= ram[addr_b];
end
end
endmodule
endmodule
frontends/read_verilog_real_value_shift_concat/top1.v → frontends/read_ilang/top_mux.v
......@@ -2,6 +2,7 @@ module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
......
frontends/read_ilang_tri/top.v → frontends/read_ilang/top_tri.v
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
......
frontends/read_ilang_error/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
frontends/read_ilang_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_ilang_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_ilang_mux/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_ilang_tri/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
frontends/scripts/read_json_mem.ys → frontends/read_json/read_json.ys
read_verilog ../top.v
proc
write_json json.json
design -reset
read_json json.json
design -reset
read_verilog ../top.v
proc
memory
write_verilog synth.v
select -assert-count 2 t:$dff
select -assert-count 2 t:$add
select -assert-none t:$dff t:$add %% t:* %D
frontends/scripts/read_json.ys → frontends/read_json/read_json_fsm.ys
read_verilog ../top.v
read_verilog ../top_fsm.v
proc
write_json json.json
design -reset
read_json json.json
write_verilog synth.v
frontends/read_json/read_json_invalid_direction_fail.pat 0 → 100644
ERROR: JSON port node 'x' has invalid 'insdfasdfput' direction attribute.
frontends/read_json/read_json_logic.ys 0 → 100644
read_verilog ../top_logic.v
proc
write_json json.json
design -reset
read_json json.json
select -assert-count 1 t:$and
select -assert-count 1 t:$dff
select -assert-count 2 t:$logic_and
select -assert-count 1 t:$logic_not
select -assert-count 2 t:$logic_or
select -assert-count 2 t:$mux
select -assert-count 1 t:$or
select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D
frontends/read_json/read_json_mem.ys 0 → 100644
read_verilog ../top_mem.v
proc
memory
write_json json.json
design -reset
read_json json.json
stat
select -assert-count 2 t:$dff
select -assert-count 1 t:$mem
select -assert-count 10 t:$mux
select -assert-none t:$dff t:$mem t:$mux %% t:* %D
frontends/read_json/read_json_mem_noproc.ys 0 → 100644
read_verilog ../top_mem.v
write_json json.json
design -reset
read_json json.json
stat
select -assert-count 2 t:$memrd
select -assert-count 2 t:$memwr
select -assert-none t:$memrd t:$memwr %% t:* %D
frontends/read_json/read_json_mux.ys 0 → 100644
read_verilog ../top_mux.v
proc
write_json json.json
design -reset
read_json json.json
stat
select -assert-count 1 t:$shiftx
select -assert-count 1 t:$mux
select -assert-count 12 t:$eq
select -assert-count 2 t:$pmux
frontends/read_json/read_json_no_bits_fail.pat 0 → 100644
ERROR: JSON port node 'x' has no bits attribute.
frontends/read_json/read_json_no_direction_fail.pat 0 → 100644
ERROR: JSON port node 'x' has no direction attribute.
frontends/read_json/read_json_nonarray_bits_attr_fail.pat 0 → 100644
ERROR: JSON netname node '$add$top.v:21$4_Y' has non-array bits attribute.
frontends/read_json/read_json_nonstring_key_fail.pat 0 → 100644
ERROR: Unexpected non-string key in JSON dict.
frontends/read_json/read_json_tri.ys 0 → 100644
read_verilog ../top_tri.v
proc
write_json json.json
design -reset
read_json json.json
stat
select -assert-count 2 t:$mux
frontends/read_json/read_json_unexpected_char_fail.pat 0 → 100644
ERROR: Unexpected character in JSON file: 'a'
frontends/read_json/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
frontends/read_json/top.v
......@@ -7,21 +7,17 @@ module top
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_ilang_error/top.v → frontends/read_json/top_logic.v
......@@ -8,22 +8,16 @@ module top
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_ilang_mem/top.v → frontends/read_json/top_mem.v
......@@ -7,38 +7,30 @@ module top
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......@@ -48,5 +40,5 @@ module top
q_b <= ram[addr_b];
end
end
endmodule
endmodule
frontends/read_verilog_string/top1.v → frontends/read_json/top_mux.v
......@@ -2,6 +2,7 @@ module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
......
frontends/read_json_tri/top.v → frontends/read_json/top_tri.v
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
......
frontends/read_json_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_json_logic/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
frontends/read_json_logic/top.v deleted 100644 → 0
module top
(
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_json_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_json_mux/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_json_mux/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_json_tri/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
frontends/read_liberty/lib_latch_nn.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
data_in : "D" ;
clear : "CLR" ;
preset : "PRE" ;}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_falling;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_falling;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( PRE ) {
direction : input;
capacitance : 0.0135;
} /* end of pin PRE */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : falling_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : negative_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
timing () { /* propagation delay from falling edge of preset to Q=1 */
timing_type : preset;
timing_sense : negative_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "PRE";
} /* end of Q timing related to PRE */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty/lib_latch_pp.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
data_in : "D" ;
clear : "CLR" ;
preset : "PRE" ;}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( PRE ) {
direction : input;
capacitance : 0.0135;
} /* end of pin PRE */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
timing () { /* propagation delay from falling edge of preset to Q=1 */
timing_type : preset;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "PRE";
} /* end of Q timing related to PRE */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty/lib_rom.lib 0 → 100644
library (read_only_memory) {
type(bus4) {
base_type : array;
data_type : bit;
bit_width : 4;
bit_from : 0;
bit_to : 3;
downto : false;
}
cell (rom) {
memory() {
type : rom;
address_width : 4;
word_width : 4;
}
bus (ADDR) {
bus_type : "bus4";
direction : input;
capacitance : 1.46;
timing () {
timing_type : setup_falling;
intrinsic_rise : 3.20;
intrinsic_fall : 3.20;
related_pin : "CLK";
}
}
pin (CLK) {
direction : input;
capacitance : 1.13;
clock : true;
}
bus(QO){
bus_type : "bus4";
direction : output;
memory_read() {
address : ADDR;
}
timing () {
timing_sense : non_unate;
intrinsic_rise : 5.25;
rise_resistance : 0.020;
intrinsic_fall : 5.50;
fall_resistance : 0.017;
related_bus_pins : "ADDR";
}
}
}
}
frontends/read_liberty_error/lib.lib → frontends/read_liberty/lib_type.lib
......@@ -25,7 +25,14 @@ variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
type (bus4) {
base_type : array;/* Required */
data_type : bit;/* Required if base_type is array */
bit_width : 4;/* Optional; default is 1 */
bit_from : 0;/* Optional MSB; defaults to 0 */
bit_to : 3;/* Optional LSB; defaults to 0 */
downto : false;/* Optional; defaults to false */
}
cell (top) {
area : 2;
......
frontends/read_liberty/read_liberty.ys 0 → 100644
read_liberty ../lib.lib
select -assert-count 2 t:$_NOT_
select -assert-none t:$_NOT_ %% t:* %D
frontends/read_liberty/read_liberty_arith.ys 0 → 100644
read_liberty ../lib_arith.lib
stat
select -assert-count 2 t:$_AND_
select -assert-count 2 t:$_OR_
select -assert-count 1 t:$_XOR_
select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ %% t:* %D
frontends/read_liberty/read_liberty_bus_interface_only_in_lib_mode_fail.pat 0 → 100644
ERROR: Error in cell top: bus interfaces are only supported in -lib mode.
frontends/read_liberty/read_liberty_cant_open_input_file_fail.pat 0 → 100644
ERROR: Can't open input file `../libbbb.lib' for reading: No such file or directory
frontends/read_liberty/read_liberty_diff_inv.ys 0 → 100644
read_liberty ../lib_diff_inv.lib
stat
select -assert-count 2 t:$_NOT_
select -assert-none t:$_NOT_ %% t:* %D
frontends/read_liberty/read_liberty_ff.ys 0 → 100644
read_liberty ../lib_ff.lib
stat
select -assert-count 1 t:$_DFF_PP0_
select -assert-count 1 t:$_NOT_
select -assert-none t:$_DFF_PP0_ t:$_NOT_ %% t:* %D
frontends/read_liberty/read_liberty_ff_has_no_next_stage_attr_fail.pat 0 → 100644
ERROR: FF cell top has no next_state and/or clocked_on attribute.
frontends/read_liberty/read_liberty_ff_n.ys 0 → 100644
read_liberty ../lib_ff_n.lib
stat
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:$_NOT_
select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% t:* %D
frontends/read_liberty/read_liberty_ff_np.ys 0 → 100644
read_liberty ../lib_ff_np.lib
stat
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:$_NOT_
select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% t:* %D
frontends/read_liberty/read_liberty_ff_pn.ys 0 → 100644
read_liberty ../lib_ff_pn.lib
stat
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:$_NOT_
select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% t:* %D
frontends/read_liberty/read_liberty_ff_pp.ys 0 → 100644
read_liberty ../lib_ff_pp.lib
stat
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:$_NOT_
select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% t:* %D
frontends/read_liberty/read_liberty_ignoring_cell.pat 0 → 100644
Ignoring cell top with missing or invalid direction for pin A.
frontends/read_liberty/read_liberty_ignoring_cell.ys 0 → 100644
tee -o result.out read_liberty -ignore_miss_dir ../lib1.lib
frontends/read_liberty/read_liberty_ignoring_latch_cell.pat 0 → 100644
Ignored latch cell top with no data_in and/or enable attribute.
frontends/read_liberty/read_liberty_ignoring_latch_cell.ys 0 → 100644
tee -o result.out read_liberty -ignore_miss_data_latch ../liblat.lib
frontends/read_liberty/read_liberty_ignoring_miss_func.pat 0 → 100644
Ignoring cell top with missing function on output Y.
frontends/read_liberty/read_liberty_ignoring_miss_func.ys 0 → 100644
tee -o result.out read_liberty -ignore_miss_func ../lib4.lib
frontends/read_liberty/read_liberty_invalid_bus_type_fail.pat 0 → 100644
ERROR: Missing or invalid direction for bus B on cell bused_cell.
frontends/read_liberty/read_liberty_latch.ys 0 → 100644
read_liberty ../lib_latch.lib
stat
select -assert-count 1 t:$_AND_
select -assert-count 1 t:$_DLATCH_P_
select -assert-count 2 t:$_NOT_
select -assert-count 1 t:$_OR_
select -assert-none t:$_AND_ t:$_DLATCH_P_ t:$_NOT_ t:$_OR_ %% t:* %D
frontends/read_liberty/read_liberty_latch_has_no_data_in_fail.pat 0 → 100644
ERROR: Latch cell top has no data_in and/or enable attribute.
frontends/read_liberty/read_liberty_latch_n.ys 0 → 100644
read_liberty ../lib_latch_n.lib
stat
select -assert-count 1 t:$_DLATCH_P_
select -assert-count 1 t:$_NOT_
select -assert-count 2 t:$_OR_
select -assert-none t:$_DLATCH_P_ t:$_NOT_ t:$_OR_ %% t:* %D
frontends/read_liberty/read_liberty_latch_nn.ys 0 → 100644
read_liberty ../lib_latch_nn.lib
stat
select -assert-count 1 t:$_AND_
select -assert-count 1 t:$_DLATCH_P_
select -assert-count 2 t:$_NOT_
select -assert-count 3 t:$_OR_
select -assert-none t:$_AND_ t:$_DLATCH_P_ t:$_NOT_ t:$_OR_ %% t:* %D
frontends/read_liberty/read_liberty_latch_pp.ys 0 → 100644
read_liberty ../lib_latch_pp.lib
stat
select -assert-count 1 t:$_AND_
select -assert-count 1 t:$_DLATCH_P_
select -assert-count 2 t:$_NOT_
select -assert-count 3 t:$_OR_
select -assert-none t:$_AND_ t:$_DLATCH_P_ t:$_NOT_ t:$_OR_ %% t:* %D
frontends/read_liberty/read_liberty_miss_func_on_output_fail.pat 0 → 100644
ERROR: Missing function on output Y of cell top.
frontends/read_liberty/read_liberty_missing_direction_fail.pat 0 → 100644
ERROR: Missing or invalid direction for pin A on cell top.
frontends/read_liberty/read_liberty_nooverwrite.ys 0 → 100644
read_liberty -nooverwrite ../lib.lib
frontends/read_liberty/read_liberty_redefenition_nooverwrite.pat 0 → 100644
Ignoring re-definition of module top.
Ignoring re-definition of module INVX2.
frontends/read_liberty/read_liberty_redefenition_nooverwrite.ys 0 → 100644
read_liberty ../lib.lib
tee -o result.out read_liberty -nooverwrite ../lib.lib
frontends/read_liberty/read_liberty_redefenition_of_module_fail.ys 0 → 100644
read_liberty ../lib.lib
read_liberty ../lib.lib
frontends/read_liberty/read_liberty_redefenition_overwrite.pat 0 → 100644
Replacing existing module top.
Replacing existing module INVX2.
frontends/read_liberty/read_liberty_redefenition_overwrite.ys 0 → 100644
read_liberty ../lib.lib
tee -o result.out read_liberty -overwrite ../lib.lib
frontends/read_liberty/read_liberty_rom.ys 0 → 100644
read_liberty -lib ../lib_rom.lib
frontends/read_liberty/read_liberty_setattr.ys 0 → 100644
read_liberty -setattr a ../lib.lib
frontends/read_liberty/read_liberty_tri.ys 0 → 100644
read_liberty -lib ../lib_tri.lib
frontends/read_liberty/read_liberty_type.ys 0 → 100644
tee -o result.out read_liberty -lib ../lib_type.lib
frontends/read_liberty/read_liberty_unsupp_type_for_bus_fail.pat 0 → 100644
ERROR: Unknown or unsupported type for bus interface D on cell top.
frontends/scripts/read_aiger_aig.ys → frontends/read_liberty/read_liberty_unsupp_type_for_bus_fail.ys
read_aiger -clk_name clk -module_name top ../aiger.aiger
read_liberty -lib ../liblat1.lib
synth -top top
write_verilog synth.v
frontends/read_liberty/testbench.v deleted 100644 → 0
module testbench;
reg a;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.Y(b)
);
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/read_liberty_arith/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.regA(out),
.regcout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
frontends/read_liberty_diff_inv/testbench.v deleted 100644 → 0
module testbench;
reg a;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.Y(b)
);
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/read_liberty_error/testbench.v deleted 100644 → 0
module testbench;
reg a;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.Y(b)
);
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/read_liberty_ff/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_n/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_np/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_pn/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_ff_pp/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_latch/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_latch_n/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
wire out = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.CLK(in[0]),
.D(in[1]),
.CLR(in[2]),
.Q(out)
);
always @(posedge in[0] or posedge in[2])
if (in[2])
patt_out <= 0;
else
patt_out <= in[1];
assert_dff dff_test(.clk(in[0]),.test(out),.pat(patt_out));
endmodule
frontends/read_liberty_tech/testbench.v deleted 100644 → 0
module testbench;
reg a;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.Y(b)
);
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/read_liberty_tri/testbench.v deleted 100644 → 0
module testbench;
reg a;
reg En = 1'b1;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.En(En),
.Y(b)
);
assert_comb b_test(.A(a),.B(b));
endmodule
frontends/read_verilog/read_verilog.ys 0 → 100644
read_verilog ../top.v
select -assert-count 1 t:$shiftx
select -assert-count 1 t:$mux
frontends/read_verilog/read_verilog_assert.ys 0 → 100644
read_verilog -sv ../top_assert_assume.v
select -assert-count 4 t:$add
select -assert-count 1 t:$allconst
select -assert-count 1 t:$allseq
select -assert-count 1 t:$assert
select -assert-count 1 t:$assume
select -assert-count 1 t:$fair
select -assert-count 2 t:$initstate
select -assert-count 1 t:$live
frontends/read_verilog/read_verilog_assert_assumes.ys 0 → 100644
read_verilog -assert-assumes ../top.v
frontends/read_verilog/read_verilog_assert_ast1.ys 0 → 100644
read_verilog -sv -dump_ast1 ../top_assert_assume.v
frontends/read_verilog/read_verilog_assert_ast2.ys 0 → 100644
read_verilog -sv -dump_ast2 ../top_assert_assume.v
frontends/read_verilog/read_verilog_assume_asserts.ys 0 → 100644
read_verilog -assume-asserts ../top.v
frontends/read_verilog/read_verilog_comparison.ys 0 → 100644
read_verilog ../top_comparison.v
select -assert-count 1 t:$eqx
select -assert-count 1 t:$ge
select -assert-count 1 t:$le
select -assert-count 1 t:$lt
select -assert-count 1 t:$ne
select -assert-count 1 t:$nex
frontends/read_verilog/read_verilog_div_mod.ys 0 → 100644
read_verilog ../top_div_mod.v
select -assert-count 1 t:$div
select -assert-count 1 t:$mod
select -assert-count 1 t:$neg
select -assert-count 1 t:$pos
select -assert-count 1 t:$pow
frontends/read_verilog/read_verilog_dname.ys 0 → 100644
read_verilog -Dname ../top.v
synth -top top
frontends/read_verilog/read_verilog_logic.ys 0 → 100644
read_verilog ../top_logic.v
select -assert-count 1 t:$add
select -assert-count 2 t:$and
select -assert-count 2 t:$mux
select -assert-count 4 t:$not
select -assert-count 2 t:$or
select -assert-count 1 t:$reduce_and
select -assert-count 2 t:$reduce_or
select -assert-count 1 t:$reduce_xnor
select -assert-count 1 t:$reduce_xor
select -assert-count 1 t:$xnor
select -assert-count 1 t:$xor
frontends/read_verilog/read_verilog_mem.ys 0 → 100644
read_verilog ../top_mem.v
select -assert-count 2 t:$memrd
select -assert-count 2 t:$memwr
frontends/read_verilog/read_verilog_mem2reg.ys 0 → 100644
read_verilog -mem2reg ../top_mem.v
select -assert-none t:$memrd
select -assert-none t:$memwr
frontends/read_verilog/read_verilog_nolatches.ys 0 → 100644
read_verilog -nolatches ../top_latch.v
frontends/read_verilog/read_verilog_nooverwrite.ys 0 → 100644
read_verilog ../top.v
tee -o result.out read_verilog -nooverwrite ../top.v
frontends/read_verilog/read_verilog_overwrite.ys 0 → 100644
read_verilog ../top.v
tee -o result.out read_verilog -overwrite ../top.v
frontends/read_verilog/read_verilog_setattr.ys 0 → 100644
read_verilog -setattr attr ../top.v
frontends/read_verilog/read_verilog_sv_ast1.ys 0 → 100644
read_verilog -sv -dump_ast1 ../top.v
frontends/read_verilog/read_verilog_sv_ast2.ys 0 → 100644
read_verilog -sv -dump_ast2 ../top.v
frontends/read_verilog/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog/top.v
......@@ -2,15 +2,8 @@ module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
......@@ -28,11 +21,7 @@ begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
......@@ -56,11 +45,7 @@ begin
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
......@@ -69,13 +54,13 @@ end
endmodule
module mux16 (D, S, Y);
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
......@@ -91,20 +76,20 @@ mux2 u_mux2 (
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
......
frontends/read_verilog/top1.v
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
......@@ -45,55 +15,18 @@ begin
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
`ifdef NBUG
`elsif BUG
`endif
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_verilog_assert/top.v → frontends/read_verilog/top_assert_assume.v
......@@ -21,7 +21,6 @@ module top
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
......@@ -36,8 +35,5 @@ always @(negedge x) begin
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_verilog/top_attributes.v 0 → 100644
(* black_box *) module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
(* white_box *) module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
frontends/read_verilog_real_value_shift_concat/top.v → frontends/read_verilog/top_concat_replication_shift.v
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
reg b,c = 1.01;
wire a;
reg b,c = 1.01;
wire a;
endmodule
......
frontends/read_verilog/top_directives.v 0 → 100644
`include "../top.v"
`resetall
`define NBUG
`timescale 10ns/1ns
module mux ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
`ifdef NBUG
`elsif BUG
`endif
end
endmodule
`undef NBUG
frontends/read_verilog_div_mod/top.v → frontends/read_verilog/top_div_mod.v
......@@ -10,15 +10,11 @@ module top
wire pow,p,n;
`ifndef BUG
assign {cout,A} = cin % y / x;
assign pow = y ** x;
assign p = +x;
assign n = -x;
`else
assign {cout,A} = 2'bZZ;
`endif
endmodule
frontends/read_verilog/top_dpi.v 0 → 100644
package my_pkg;
localparam u = 0;
endpackage
module tb_dpi;
import "DPI-C" function int add();
wire logic w;
endmodule
module hello();
import "DPI-C" function void print_hello();
endmodule
frontends/read_verilog_ff_edge/top.v → frontends/read_verilog/top_ff_edge.v
......@@ -5,11 +5,7 @@ module adff
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -21,11 +17,7 @@ module adffn
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -37,11 +29,7 @@ module dffe
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
......@@ -51,11 +39,7 @@ module dffsr
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
......@@ -69,11 +53,7 @@ module ndffnsnr
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
......@@ -95,7 +75,7 @@ dffsr u_dffsr (
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
......@@ -103,21 +83,21 @@ ndffnsnr u_ndffnsnr (
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
......
frontends/read_verilog/top_for_while.v 0 → 100644
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
reg i;
function integer log2;
input integer value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
while (1)
value = value>>1;
repeat(10)
begin
end
end
endfunction
endmodule
frontends/read_verilog/top_generate.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
parameter u = 0;
genvar index;
generate
for (index=0; index < 8; index=index+1)
begin: gen_code_label
end
endgenerate
genvar index;
generate
case( u )
0 : begin end
1 : begin end
2 : begin end
3 : begin end
endcase
endgenerate
// reg angle;
// case (index)
// //Create the case statement
// 1 :
// begin
// generate
// genvar caseIndex;
// for (caseIndex = 0; caseIndex < 1024; caseIndex=caseIndex+1)
// begin
// caseIndex: angle = 2*pi*caseIndex/1024;
// end
// endgenerate
// end
// endcase
endmodule
frontends/read_verilog/top_latch.v 0 → 100644
module latch
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @ (clk or clr)
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
frontends/read_verilog_logic/top.v → frontends/read_verilog/top_logic.v
......@@ -15,7 +15,6 @@ module top
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A1 <= ~y + &cin;
end
......@@ -36,8 +35,5 @@ end
always @(posedge x) begin
cout <= cout1&cin~|y;
end
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
frontends/read_verilog_mem/top.v → frontends/read_verilog/top_mem.v
......@@ -17,11 +17,7 @@ module top
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
......@@ -35,11 +31,7 @@ module top
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......
frontends/read_verilog/top_param_defparam.v 0 → 100644
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
parameter D_WIDTH = 8;
parameter S_WIDTH = 3;
localparam L = 6;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
defparam u_mux16.D_WIDTH = 16;
defparam u_mux16.S_DEPTH = 4;
endmodule
frontends/read_verilog/top_string.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
parameter FILE_OUT= "\"file1.txt\"";
reg [8*10:1] stringvar;
reg [7:0] q;
initial begin
stringvar="Starting";
q <= '1;
end
endmodule
frontends/read_verilog/top_task_func.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire [7:0] temp_a,temp_b;
wire e;
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9/5) *( temp_in + 32);
end
endtask
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
always @ (temp_a)
begin
convert (temp_a, temp_b);
end
assign e = myfunction (a,b,c,d);
endmodule
frontends/read_verilog_assert/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
frontends/read_verilog_assert/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_verilog_attributes/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_attributes/top.v deleted 100644 → 0
(* black_box *) module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
(* white_box *)module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_verilog_comparison/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] I0 = 1;
reg [15:0] I1 = 0;
wire A,B,C,D,E,F;
reg Ap,Bp,Cp,Dp,Ep,Fp;
top uut (
.clk (clk),
.I0 (I0 ),
.I1 (I1 ),
.A (A ),
.B (B ),
.C (C ),
.D (D ),
.E (E ),
.F (F )
);
always @(posedge clk)
begin
if (I0 < I1)
Ap <= 1'b1;
else
Ap <= 1'b0;
if (I0 <= I1)
Bp <= 1'b1;
else
Bp <= 1'b0;
if (I0 != I1)
Cp <= 1'b1;
else
Cp <= 1'b0;
if (I0 === I1)
Dp <= 1'b1;
else
Dp <= 1'b0;
if (I0 !== I1)
Ep <= 1'b1;
else
Ep <= 1'b0;
if (I0 >= I1)
Fp <= 1'b1;
else
Fp <= 1'b0;
end
always @(posedge clk) begin
//#3;
I0 <= {I0[14:0],I0[15]};
//D <= D <<< 1;
I1 <= I1 + 1;
end
assert_tri A_test(.en(clk), .A(A), .B(Ap));
assert_tri B_test(.en(clk), .A(B), .B(Bp));
assert_tri C_test(.en(clk), .A(C), .B(Cp));
//assert_tri D_test(.en(clk), .A(D), .B(Dp));
assert_tri E_test(.en(clk), .A(E), .B(Ep));
assert_tri F_test(.en(clk), .A(F), .B(Fp));
endmodule
frontends/read_verilog_div_mod/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] % in[1] / in[0];
assert_Z out_test(in[0], out);
assert_Z carry_test(in[0], carryout);
endmodule
frontends/read_verilog_dpi/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_dpi/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
package my_pkg;
localparam u = 0;
endpackage
module tb_dpi;
import "DPI-C" function int add();
wire logic w;
endmodule
module hello();
import "DPI-C" function void print_hello();
endmodule
frontends/read_verilog_ff_edge/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
frontends/read_verilog_for_while/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_for_while/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
reg i;
function integer log2;
input integer value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
while (1)
value = value>>1;
repeat(10)
begin
end
end
endfunction
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_verilog_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_verilog_generate/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_generate/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
casez( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
inout[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
casex( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
parameter u = 0;
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
genvar index;
generate
for (index=0; index < 8; index=index+1)
begin: gen_code_label
end
endgenerate
genvar index;
generate
case( u )
0 : begin end
1 : begin end
2 : begin end
3 : begin end
endcase
endgenerate
// reg angle;
// case (index)
// //Create the case statement
// 1 :
// begin
// generate
// genvar caseIndex;
// for (caseIndex = 0; caseIndex < 1024; caseIndex=caseIndex+1)
// begin
// caseIndex: angle = 2*pi*caseIndex/1024;
// end
// endgenerate
// end
// endcase
endmodule
frontends/read_verilog_logic/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
frontends/read_verilog_logic/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/read_verilog_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
frontends/read_verilog_param_defparam/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_param_defparam/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
parameter WIDTH = 8;
parameter DEPTH = 64;
parameter LOG2DEPTH = 6;
localparam L = 6;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
defparam u_mux16.WIDTH = 32;
defparam u_mux16.DEPTH = 64;
defparam u_mux16.LOG2DEPTH = 2;
endmodule
frontends/read_verilog_real_value_shift_concat/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_string/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_string/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
parameter FILE_OUT= "\"file1.txt\"";
reg [8*10:1] stringvar;
reg [7:0] q;
initial begin
stringvar="Starting";
q <= '1;
end
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/read_verilog_task_func/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/read_verilog_task_func/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire [7:0] temp_a,temp_b;
wire e;
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9/5) *( temp_in + 32);
end
endtask
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
always @ (temp_a)
begin
convert (temp_a, temp_b);
end
assign e = myfunction (a,b,c,d);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/run.sh deleted 100644 → 0
#!/bin/bash
set -x
test -d $1
test -f scripts/$2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
# cases where 'syntax error' or other errors are expected
if echo "$1" | grep ".*_error"; then
expected_string=""
#Change checked string for check other errors
if [ "$2" = "read_aiger_cant_interpret_first_char" ]; then
expected_string="ERROR: Line 80: cannot interpret first character"
elif [ "$2" = "read_aiger_unsup_aiger_file" ]; then
expected_string="ERROR: Unsupported AIGER file!"
elif [ "$2" = "read_aiger_invalid_aiger_header" ]; then
expected_string="ERROR: Invalid AIGER header"
elif [ "$2" = "read_aiger_cant_interpret_as_input" ]; then
expected_string="ERROR: Line 2 cannot be interpreted as an input!"
elif [ "$2" = "read_aiger_cant_interpret_as_and" ]; then
expected_string="ERROR: Line 6 cannot be interpreted as an AND!"
elif [ "$2" = "read_aiger_bad_state_property" ]; then
expected_string="ERROR: Line 4 cannot be interpreted as a bad state property!"
elif [ "$2" = "read_aiger_invalid_reset_literal" ]; then
expected_string="ERROR: Line 1 has invalid reset literal for latch!"
elif [ "$2" = "read_aiger_duplicate_definition" ]; then
expected_string="ERROR: Duplicate definition of module top!"
elif [ "$2" = "read_blif_syntax_error" ]; then
expected_string="ERROR: Syntax error in line"
elif [ "$2" = "read_blif_duplicate_defenition" ]; then
expected_string="ERROR: Duplicate definition of module "
elif [ "$2" = "read_ilang_parse_error" ]; then
expected_string="ERROR: Parser error in line "
elif [ "$2" = "read_json_nonstring_key" ]; then
expected_string="ERROR: Unexpected non-string key in JSON dict."
elif [ "$2" = "read_json_nonarray_bits_attr" ]; then
expected_string=" has non-array bits attribute."
elif [ "$2" = "read_json_unexpected_eof" ]; then
expected_string="ERROR: Unexpected EOF in JSON file."
elif [ "$2" = "read_json_invalid_direction" ]; then
expected_string="ERROR: JSON port node 'x' has invalid 'insdfasdfput' direction attribute."
elif [ "$2" = "read_json_no_bits" ]; then
expected_string=" has no bits attribute."
elif [ "$2" = "read_json_no_direction" ]; then
expected_string=" has no direction attribute."
elif [ "$2" = "read_json_unexpected_char" ]; then
expected_string="ERROR: Unexpected character in JSON file: "
elif [ "$2" = "verilog_defaults_missing_arg" ]; then
expected_string="ERROR: Command syntax error: Missing argument."
elif [ "$2" = "verilog_defaults_extra_arg" ]; then
expected_string="ERROR: Command syntax error: Extra argument."
elif [ "$2" = "verilog_defines_extra_arg" ]; then
expected_string="ERROR: Command syntax error: Extra argument."
elif [ "$2" = "read_liberty_invalid_bus_type" ]; then
expected_string="ERROR: Missing or invalid direction for bus B on cell bused_cell."
elif [ "$2" = "read_liberty_unsupp_type_for_bus" ]; then
expected_string="ERROR: Unknown or unsupported type for bus interface D on cell top."
elif [ "$2" = "read_liberty_bus_interface_only_in_lib_mode" ]; then
expected_string="ERROR: Error in cell top: bus interfaces are only supported in -lib mode."
elif [ "$2" = "read_liberty_latch_has_no_data_in" ]; then
expected_string="ERROR: Latch cell top has no data_in and/or enable attribute."
elif [ "$2" = "read_liberty_miss_func_on_output" ]; then
expected_string="ERROR: Missing function on output Y of cell top."
elif [ "$2" = "read_liberty_ff_has_no_next_stage_attr" ]; then
expected_string="ERROR: FF cell top has no next_state and/or clocked_on attribute."
elif [ "$2" = "read_liberty_parse_error_in_function" ]; then
expected_string="ERROR: Parser error in function expr "
elif [ "$2" = "read_liberty_cant_resolve_wire_name" ]; then
expected_string="ERROR: Can't resolve wire name s."
elif [ "$2" = "read_liberty_missing_direction" ]; then
expected_string="ERROR: Missing or invalid direction for pin A on cell top."
elif [ "$2" = "read_liberty_cant_open_input_file" ]; then
expected_string="ERROR: Can't open input file \`../libbbb.lib' for reading: No such file or directory"
elif [ "$2" = "read_liberty_redefenition_of_module" ]; then
expected_string="ERROR: Re-definition of cell/module top!"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo FAIL > ${1}_${2}.status
else
if grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
fi
else
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
sed -i 's/reg =/dummy =/' ./synth.v
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
else
COMMON_PREFIX=/usr/local/share/yosys
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
fi
touch .stamp
frontends/scripts/read_aiger_clk.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger -clk_name clk aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_blif_eblif.ys deleted 100644 → 0
read_blif -wideports ../eblif.eblif
synth -top top
write_verilog synth.v
frontends/scripts/read_blif_syntax_error.ys deleted 100755 → 0
read_blif ../blif_e1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_liberty.ys deleted 100644 → 0
read_liberty -lib ../lib.lib
design -reset
read_liberty ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_lib.ys deleted 100644 → 0
read_liberty -lib ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_miss_func_on_output.ys deleted 100644 → 0
read_liberty ../lib4.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_missing_direction.ys deleted 100644 → 0
read_liberty ../lib1.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_nooverwrite.ys deleted 100644 → 0
read_liberty -nooverwrite ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_parse_error_in_function.ys deleted 100644 → 0
read_liberty ../lib3.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_redefenition_of_module.ys deleted 100644 → 0
read_liberty ../lib.lib
read_liberty ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_setattr.ys deleted 100644 → 0
read_liberty -setattr a ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_unsupp_type_for_bus.ys deleted 100644 → 0
read_liberty -lib ../liblat1.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_noverific.ys deleted 100644 → 0
read -noverific
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_sv.ys deleted 100644 → 0
read -sv ../top.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_sv2005.ys deleted 100644 → 0
read -sv2005 ../top.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_sv2009.ys deleted 100644 → 0
read -sv2009 ../top.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_sv2012.ys deleted 100644 → 0
read -sv2012 ../top.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_undef.ys deleted 100644 → 0
read -formal ../top.v
read -define MACRO
read -undef MACRO
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_assert.ys deleted 100644 → 0
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_assert_assumes.ys deleted 100644 → 0
read_verilog -assert-assumes ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_assert_ast1.ys deleted 100644 → 0
read_verilog -sv -dump_ast1 ../top.v
synth -top top
write_verilog synth.v
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_assert_ast2.ys deleted 100644 → 0
read_verilog -sv -dump_ast2 ../top.v
synth -top top
write_verilog synth.v
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_assume_asserts.ys deleted 100644 → 0
read_verilog -assume-asserts ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_debug.ys deleted 100644 → 0
read_verilog -debug ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_defer.ys deleted 100644 → 0
read_verilog -defer ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_dname.ys deleted 100644 → 0
read_verilog -Dname ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_dname_value.ys deleted 100644 → 0
read_verilog -Dname=9 ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_dump_ast1.ys deleted 100644 → 0
read_verilog -dump_ast1 ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_dump_ast2.ys deleted 100644 → 0
read_verilog -dump_ast2 ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_dump_rtlil.ys deleted 100644 → 0
read_verilog -dump_rtlil ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_dump_vlog1.ys deleted 100644 → 0
read_verilog -dump_vlog1 ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_dump_vlog2.ys deleted 100644 → 0
read_verilog -dump_vlog2 ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_formal.ys deleted 100644 → 0
read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_i_dir.ys deleted 100644 → 0
read_verilog -I dir ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_icells.ys deleted 100644 → 0
read_verilog -icells ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_idir.ys deleted 100644 → 0
read_verilog -Idir ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_lib.ys deleted 100644 → 0
read_verilog -lib ../top.v
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_mem2reg.ys deleted 100644 → 0
read_verilog -mem2reg ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_no_dump_ptr.ys deleted 100644 → 0
read_verilog -no_dump_ptr ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_noassert.ys deleted 100644 → 0
read_verilog -noassert ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_noassume.ys deleted 100644 → 0
read_verilog -noassume ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_noautowire.ys deleted 100644 → 0
read_verilog -noautowire ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_nodpi.ys deleted 100644 → 0
read_verilog -nodpi ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_nolatches.ys deleted 100644 → 0
read_verilog -nolatches ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_nomem2reg.ys deleted 100644 → 0
read_verilog -nomem2reg ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_nomeminit.ys deleted 100644 → 0
read_verilog -nomeminit ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_noopt.ys deleted 100644 → 0
read_verilog -noopt ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_nooverwrite.ys deleted 100644 → 0
read_verilog -nooverwrite ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_nopp.ys deleted 100644 → 0
read_verilog -nopp ../top1.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_norestrict.ys deleted 100644 → 0
read_verilog -norestrict ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_overwrite.ys deleted 100644 → 0
read_verilog -overwrite ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_ppdump.ys deleted 100644 → 0
read_verilog -ppdump ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_setattr.ys deleted 100644 → 0
read_verilog -setattr attr ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_specify.ys deleted 100644 → 0
read_verilog -specify ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_sv.ys deleted 100644 → 0
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_sv_ast1.ys deleted 100644 → 0
read_verilog -sv -dump_ast1 ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_sv_ast2.ys deleted 100644 → 0
read_verilog -sv -dump_ast2 ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_verilog_yydebug.ys deleted 100644 → 0
read_verilog -yydebug ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_vhdl.ys deleted 100644 → 0
read -vhdl ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_vhdl2k.ys deleted 100644 → 0
read -vhdl2k ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_vhdl87.ys deleted 100644 → 0
read -vhdl87 ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_vhdl93.ys deleted 100644 → 0
read -vhdl93 ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_vlog2k.ys deleted 100644 → 0
read -vlog2k ../top.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/read_vlog95.ys deleted 100644 → 0
read -vlog95 ../top.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/verilog_defaults.ys deleted 100644 → 0
verilog_defaults -add "../top.v"
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defaults_clear.ys deleted 100644 → 0
verilog_defaults -add ../top1.v
verilog_defaults -clear
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends/scripts/verilog_defaults_extra_arg.ys deleted 100644 → 0
verilog_defaults -push -pop
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defaults_missing_arg.ys deleted 100644 → 0
verilog_defaults
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defaults_pop.ys deleted 100644 → 0
verilog_defaults -add "../top.v"
verilog_defaults -push
verilog_defaults -pop
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defaults_push.ys deleted 100644 → 0
verilog_defaults -add "../top.v"
verilog_defaults -push
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defines.ys deleted 100644 → 0
verilog_defines -Dtype
read_verilog ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_defines_d.ys deleted 100644 → 0
verilog_defines -D type
read_verilog ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_defines_extra_arg.ys deleted 100644 → 0
verilog_defines -aa
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defines_u.ys deleted 100644 → 0
verilog_defines -Dtype
verilog_defines -Utype
read_verilog ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_defines_u_val.ys deleted 100644 → 0
verilog_defines -D type
verilog_defines -U type
read_verilog ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_defines_val.ys deleted 100644 → 0
verilog_defines -Dtype=str
read_verilog ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_lexer.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_lexer_assert.ys deleted 100644 → 0
read_verilog -sv ../top2.v
design -reset
read_verilog -sv ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_lexer_sv.ys deleted 100644 → 0
read -sv ../top.sv
proc
write_verilog synth.v
frontends/verilog_defaults/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defaults/verilog_defaults.ys 0 → 100644
verilog_defaults -add "../top.v"
read_verilog
frontends/verilog_defaults/verilog_defaults_clear.ys 0 → 100644
verilog_defaults -add ../top1.v
verilog_defaults -clear
read_verilog ../top.v
frontends/verilog_defaults/verilog_defaults_extra_arg_fail.pat 0 → 100644
ERROR: Command syntax error: Extra argument.
frontends/verilog_defaults/verilog_defaults_missing_arg_fail.pat 0 → 100644
ERROR: Command syntax error: Missing argument.
frontends/verilog_defaults/verilog_defaults_pop.ys 0 → 100644
verilog_defaults -add "../top.v"
verilog_defaults -push
verilog_defaults -pop
read_verilog
frontends/verilog_defaults/verilog_defaults_push.ys 0 → 100644
verilog_defaults -add "../top.v"
verilog_defaults -push
read_verilog
frontends/verilog_defaults_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defaults_error/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_defaults_error/top1.v deleted 100644 → 0
module top1 (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
endmodule
frontends/verilog_defines/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defines/verilog_defines.ys 0 → 100644
verilog_defines -Dtype
read_verilog ../top.v
frontends/verilog_defines/verilog_defines_d.ys 0 → 100644
verilog_defines -D type
read_verilog ../top.v
frontends/verilog_defines/verilog_defines_extra_arg_fail.pat 0 → 100644
ERROR: Command syntax error: Extra argument.
frontends/verilog_defines/verilog_defines_u.ys 0 → 100644
verilog_defines -Dtype
verilog_defines -Utype
read_verilog ../top.v
frontends/verilog_defines/verilog_defines_u_val.ys 0 → 100644
verilog_defines -D type
verilog_defines -U type
read_verilog ../top.v
frontends/verilog_defines/verilog_defines_val.ys 0 → 100644
verilog_defines -Dtype=str
read_verilog ../top.v
frontends/verilog_defines_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defines_error/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer/top_always.v 0 → 100644
module mux2 (S,A,B,Y,Y1);
input S;
input A,B;
output reg Y,Y1;
always_ff @(*)
Y = (S)? B : A;
always_latch @(*)
Y1 = (~S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
frontends/read_aiger/top2.v → frontends/verilog_lexer/top_assume_assert.v
......@@ -7,13 +7,13 @@ module top
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
const integer Gsize = 10e2;
initial begin
begin
A = 0;
......@@ -21,23 +21,23 @@ module top
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
assert(eventually ASSERT);
//checker request_granted(y,cin);
r1: restrict property (y == cin);
//endchecker : request_granted
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/verilog_lexer/top_automatic_task.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
task automatic do_things;
input [31:0] number_of_things;
reg [31:0] tmp_thing;
endtask
endmodule
frontends/read_ilang_mux/top.v → frontends/verilog_lexer/top_casez.v
......@@ -2,15 +2,9 @@ module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
......@@ -25,14 +19,10 @@ wire[3:0] D;
always @*
begin
case( S )
casez( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
......@@ -51,16 +41,12 @@ wire[7:0] D;
always @*
begin
case( S )
casex( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
......@@ -69,13 +55,13 @@ end
endmodule
module mux16 (D, S, Y);
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
......@@ -91,20 +77,20 @@ mux2 u_mux2 (
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
......
frontends/verilog_lexer/top_enum_typedef.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
typedef enum {red,blue,green} e_color;
endmodule
frontends/verilog_lexer/top_interface_logic.v 0 → 100644
interface apb_if (input pclk);
logic [31:0] paddr;
logic [31:0] pwdata;
logic [31:0] prdata;
logic penable;
logic pwrite;
logic psel;
modport TB (input penable, output psel);
endinterface
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
frontends/verilog_lexer/top_package.v 0 → 100644
`resetall
package my_pkg;
// typedef enum bit [1:0] { RED, YELLOW, GREEN, RSVD } e_signal;
/* typedef struct { bit [3:0] signal_id;
bit active;
bit [1:0] timeout;
} e_sig_param;
function common ();
$display ("Called from somewhere");
endfunction
task run ();
endtask */
endpackage
{* AAA *}
//
\
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
reg a_vect[ 0 +: 8];
reg b_vect[ 0 -: 8];
//import my_pkg::*;
always @(*)
Y = (S)? B : A;
endmodule
frontends/verilog_lexer/top_specify_specparam.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
specify
specparam TRise = 10,
TFall = 15;
(S => M2) = (TRise, TFall) ;
endspecify
endmodule
frontends/verilog_lexer/top_supply.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire y,a,b;
buf (supply1) g1 (y, a);
buf (supply0) g2 (y, b);
endmodule
frontends/verilog_lexer/top_unique_priority.v 0 → 100644
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire a,c,d,e,g;
reg b,h,f;
always @(*)
begin
unique case (a)
0: b = c;
1: b = d;
endcase
unique case (g)
0: h = c;
1: h = d;
endcase
priority case (e)
0: f = c;
1: f = d;
endcase
end
endmodule
frontends/verilog_lexer/verilog_lexer_assert.ys 0 → 100644
read_verilog -sv ../top_assume_assert.v
frontends/verilog_lexer/verilog_lexer_automatic_task.ys 0 → 100644
read_verilog -sv ../top_automatic_task.v
frontends/verilog_lexer/verilog_lexer_enum_typedef.disable 0 → 100644
./top_enum_typedef.v:88: ERROR: syntax error, unexpected TOK_ENUM
frontends/verilog_lexer/verilog_lexer_enum_typedef.ys 0 → 100644
read_verilog -sv ../top_enum_typedef.v
frontends/verilog_lexer/verilog_lexer_interface_logic.ys 0 → 100644
read_verilog -sv ../top_interface_logic.v
frontends/verilog_lexer/verilog_lexer_specify_specparam.ys 0 → 100644
read_verilog -sv ../top_specify_specparam.v
frontends/verilog_lexer/verilog_lexer_supply.disable 0 → 100644
../top_supply.v:90: ERROR: syntax error, unexpected TOK_SUPPLY1
frontends/verilog_lexer/verilog_lexer_unique_priority.ys 0 → 100644
read_verilog -sv ../top_unique_priority.v
frontends/verilog_lexer_always_ff_latch/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_always_ff_latch/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always_ff @(*)
Y = (S)? B : A;
`else
always_latch @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_assert_assume_restrict/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out = 0;
wire patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign patt_out = in[1] + in[2];
assign patt_carry_out = in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
frontends/verilog_lexer_assert_assume_restrict/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
input clk,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/verilog_lexer_assert_assume_restrict/top2.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
const integer Gsize = 10e2;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(eventually ASSERT);
//checker request_granted(y,cin);
r1: restrict property (y == cin);
//endchecker : request_granted
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/verilog_lexer_automatic_task/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_automatic_task/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
task automatic do_things;
input [31:0] number_of_things;
reg [31:0] tmp_thing;
endtask
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_casez/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_casez/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
casez( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
casex( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_enum_typedef/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_enum_typedef/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
typedef enum {red,blue,green} e_color;
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
endmodule
frontends/verilog_lexer_interface_logic/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_interface_logic/top.v deleted 100644 → 0
interface apb_if (input pclk);
logic [31:0] paddr;
logic [31:0] pwdata;
logic [31:0] prdata;
logic penable;
logic pwrite;
logic psel;
modport TB (input penable, output psel);
endinterface
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_package/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_package/top.v deleted 100644 → 0
`resetall
package my_pkg;
// typedef enum bit [1:0] { RED, YELLOW, GREEN, RSVD } e_signal;
/* typedef struct { bit [3:0] signal_id;
bit active;
bit [1:0] timeout;
} e_sig_param;
function common ();
$display ("Called from somewhere");
endfunction
task run ();
endtask */
endpackage
{* AAA *}
//
\
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
reg a_vect[ 0 +: 8];
reg b_vect[ 0 -: 8];
//import my_pkg::*;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_specify_specparam/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_specify_specparam/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
parameter X = 1;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
specify
specparam TRise = 10,
TFall = 15;
(S => M2) = (TRise, TFall) ;
endspecify
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_supply/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_supply/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
casez( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
casex( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire y,a,b;
buf (supply1) g1 (y, a);
buf (supply0) g2 (y, b);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_unique_priority/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_unique_priority/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire a,c,d,e,g;
reg b,h,f;
always @(*)
begin
unique case (a)
0: b = c;
1: b = d;
endcase
unique case (g)
0: h = c;
1: h = d;
endcase
priority case (e)
0: f = c;
1: f = d;
endcase
end
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
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