Update

architecture/synth_xilinx_dsp/assert_area.py

@@ -30,12 +30,18 @@ for fn in glob.glob('*.v'):
 
     count_DFF = 0
     if Mreg and (A > 25 or B > 18):
-        count_DFF += A + B - 1
+        count_DFF += A + B
+        if not macc:
+            count_DFF -= 1 # For pure multipliers, expect last slice to absorb
+                           # at least one register
     if Preg and (A > 25 or B > 18):
-        count_DFF += A + B - 1
+        count_DFF += A + B
         if macc:
             count_DFF += 5 # In my testcases, accumulator is always
                            # 5bits bigger than multiplier result
+        else:
+            count_DFF -= 1 # For pure multipliers, expect last slice to absorb
+                           # at least one register
     # TODO: More assert on number of CARRY and LUTs
     count_CARRY = ''
     if not macc and (A <= 25 or B <= 18):

architecture/synth_xilinx_dsp/ug901b.v

@@ -51,6 +51,7 @@ generate
 	endgenerate
 endmodule
 
+(* gentb_skip *) // Prevents Yosys' test_autotb from operating on this module
 (* dont_touch = "yes" *)
 module sfir_shifter #(parameter dsize = 16, nbtap = 4) (
      input clk, 
@@ -68,6 +69,7 @@ end
 assign dataout = tmp[2*nbtap-1];
 endmodule
 
+(* gentb_skip *) // Prevents Yosys' test_autotb from operating on this module
 module sfir_even_symmetric_systolic_element #(parameter dsize = 16) (
     input clk, 
     input signed [dsize-1:0] coeffin, datain, datazin,
@@ -98,7 +100,7 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd ug901b; select t:DSP48E1 -assert-count 1; select t:FDRE -assert-count 1; select -assert-none t:DSP48E1 t:BUFG t:FDRE %% t:* %D";
+    wire [4095:0] assert_area = "cd ug901b; flatten; select t:DSP48E1 -assert-count 4; select t:FDRE -assert-count 128; select t:SRL16E -assert-count 16; select -assert-none t:DSP48E1 t:BUFG t:FDRE t:SRL16E %% t:* %D";
 endmodule
 `endif