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yosys-tests
Commit 609f294d by Eddie Hung
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Add test18-20

parent 6e23551e
Showing with 362 additions and 1 deletions
architecture/synth_xilinx_srl/test18.ys 0 → 100644
read_verilog -icells -DTEST18 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth18.v
cd synth; cd neg_clk_with_enable_with_init_inferred2[0].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[1].sr; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[2].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[3].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[4].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[5].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[6].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[7].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[8].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[9].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[10].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[11].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[12].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[13].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[14].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[15].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[16].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[17].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[18].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[19].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[20].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[21].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[22].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[23].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[24].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[25].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[26].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[27].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[28].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[29].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[30].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[31].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[32].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[33].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[34].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[35].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[36].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[37].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[38].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[39].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[40].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[41].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[42].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[43].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[44].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[45].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[46].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[47].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[48].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[49].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[50].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[51].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[52].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[53].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[54].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[55].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[56].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[57].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[58].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[59].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[60].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[61].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[62].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[63].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[64].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[65].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[66].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[67].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[68].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[69].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[70].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[71].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[72].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[73].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[74].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[75].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[76].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[77].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[78].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[79].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[80].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[81].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[82].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[83].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[84].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[85].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[86].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[87].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[88].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[89].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[90].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[91].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[92].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[93].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[94].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[95].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[96].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[97].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[98].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[99].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[100].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[101].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[102].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[103].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[104].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[105].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[106].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[107].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[108].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[109].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[110].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[111].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[112].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[113].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[114].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[115].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[116].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[117].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[118].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[119].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[120].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[121].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[122].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[123].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[124].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[125].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[126].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[127].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[128].sr; select t:FD* -assert-count 1; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[129].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
cd synth; cd neg_clk_with_enable_with_init_inferred2[130].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:FD* t:SRL16E t:SRLC32E %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test19.ys 0 → 100644
read_verilog -icells -DTEST19 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth19.v
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[0].sr; select t:FD* -assert-count 2; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[1].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[2].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[3].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[4].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[5].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[6].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[7].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[8].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[9].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[10].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[11].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[12].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[13].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[14].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 0; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[15].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[16].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[17].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[18].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[19].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[20].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[21].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[22].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[23].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[24].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[25].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[26].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[27].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[28].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[29].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[30].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 0; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[31].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[32].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[33].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[34].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[35].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[36].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[37].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[38].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[39].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[40].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[41].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[42].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[43].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[44].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[45].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[46].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 1; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[47].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[48].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[49].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[50].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[51].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[52].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[53].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[54].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[55].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[56].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[57].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[58].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[59].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[60].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[61].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[62].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 1; select t:MUXF8 -assert-count 0; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[63].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[64].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[65].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[66].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[67].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[68].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[69].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[70].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[71].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[72].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[73].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[74].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[75].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[76].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[77].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[78].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 2; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[79].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[80].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[81].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[82].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[83].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[84].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[85].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[86].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[87].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[88].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[89].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[90].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[91].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[92].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[93].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[94].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[95].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[96].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[97].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[98].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[99].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[100].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[101].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[102].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[103].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[104].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[105].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[106].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[107].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[108].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[109].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[110].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 3; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[111].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[112].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[113].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[114].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[115].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[116].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[117].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[118].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[119].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[120].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[121].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[122].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[123].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[124].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[125].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[126].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 0; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[127].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[128].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[129].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
cd synth; cd pos_clk_with_enable_no_init_inferred2_var_len[130].sr; select t:FD* -assert-count 0; select t:SRL16E -assert-count 1; select t:SRLC32E -assert-count 4; select t:MUXF7 -assert-count 2; select t:MUXF8 -assert-count 1; select t:LUT* -assert-count 1; select t:FD* t:SRL16E t:SRLC32E t:MUXF7 t:MUXF8 t:LUT* %% %n t:* %i -assert-none
architecture/synth_xilinx_srl/test20.ys 0 → 100644
read_verilog -icells -DTEST20 ../top.v
synth_xilinx
rename -top synth
clean -purge
write_verilog synth20.v
# Check that wide shift registers are not a problem
cd synth; cd neg_clk_no_enable_with_init_with_inferred2_N_width; select t:FD* -assert-count 0
architecture/synth_xilinx_srl/top.v
...@@ -120,6 +120,17 @@ generate ...@@ -120,6 +120,17 @@ generate
assign z[4] = a8; assign z[4] = a8;
end end
assign z[`N-1:5] = 'b0; // Suppress no driver warning assign z[`N-1:5] = 'b0; // Suppress no driver warning
`elsif TEST18
for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred2
shift_reg #(.depth(i+1), .neg_clk(1), .inferred(2), .init(1)) sr(clk, a[i], e, /*l*/, z[i], /* state */);
end
`elsif TEST19
for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_inferred2_var_len
shift_reg #(.depth(i+2), .inferred(2), .fixed_length(0)) sr(clk, a[i], e, l[$clog2(i+2)-1:0], z[i], /* state */);
end
`elsif TEST20
(* keep *)
shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred2_N_width(clk, a, r, /*l*/, z, /* state */);
`endif `endif
endgenerate endgenerate
endmodule endmodule
...@@ -168,7 +179,7 @@ generate ...@@ -168,7 +179,7 @@ generate
else else
assign state = {depth{1'b0}}; assign state = {depth{1'b0}};
end end
else begin else if (inferred == 1) begin
reg [depth-1:0] int [width-1:0]; reg [depth-1:0] int [width-1:0];
genvar j; genvar j;
...@@ -228,5 +239,65 @@ generate ...@@ -228,5 +239,65 @@ generate
else else
assign state = {depth{1'b0}}; assign state = {depth{1'b0}};
end end
else if (inferred == 2) begin
reg [width-1:0] int [depth-1:0];
genvar i, j;
for (i = 0; i < depth; i=i+1) begin
for (j = 0; j < width; j=j+1) begin
if (init) begin
initial int[i][j] <= ~((i+j) % 2);
end
if (i == 0) begin
if (neg_clk) begin
if (!er_is_reset) begin
always @(negedge clk) if (er) int[i] <= a[i];
end
else begin
always @(negedge clk or posedge er) if (er) int[i] <= 1'b0; else int[i] <= a[i];
end
end
else begin
if (!er_is_reset) begin
always @(posedge clk) if (er) int[i] <= a[i];
end
else begin
always @(posedge clk or posedge er) if (er) int[i] <= 1'b0; else int[i] <= a[i];
end
end
end
else begin
if (neg_clk) begin
if (!er_is_reset) begin
always @(negedge clk) if (er) int[i][j] <= int[i-1][j];
end
else begin
always @(negedge clk or posedge er) if (er) int[i] <= {depth{1'b0}}; else int[i][j] <= int[i-1][j];
end
end
else begin
if (!er_is_reset) begin
always @(posedge clk) if (er) int[i][j] <= int[i-1][j];
end
else begin
always @(posedge clk or posedge er) if (er) int[i] <= {depth{1'b0}}; else int[i][j] <= int[i-1][j];
end
end
end
end
//if (output_index >= 0)
// assign state = int[output_index];
//else if (output_xor)
// assign state = {depth{^int[0]}};
//else
assign state = {depth{1'b0}};
end
if (fixed_length > 0)
assign z = int[fixed_length-1];
else
assign z = int[l];
end
endgenerate endgenerate
endmodule endmodule
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