Commit 5dbed420 by Eddie Hung

Update xilinx_dsp tests

parent 13f65024
...@@ -4,15 +4,35 @@ import glob ...@@ -4,15 +4,35 @@ import glob
import re import re
import os import os
re_mux = re.compile(r'mul_(\d+)(s?)_(\d+)(s?)_A?B?P?_A?B?P?\.v') re_mux = re.compile(r'mul_(\d+)(s?)_(\d+)(s?)_(A?B?P?)_A?B?P?\.v')
for fn in glob.glob('*.v'): for fn in glob.glob('*.v'):
m = re_mux.match(fn) m = re_mux.match(fn)
if not m: continue if not m: continue
A,B = map(int, m.group(1,3)) A,B = map(int, m.group(1,3))
if not m.group(2): A += 1 Asigned, Bsigned = m.group(2,4)
if not m.group(4): B += 1 Areg = 'A' in m.group(5)
Breg = 'B' in m.group(5)
Preg = 'P' in m.group(5)
if not (Asigned and Bsigned):
A += 1
B += 1
Asigned = Bsigned = 1
if A < B:
A,B = B,A
Asigned,Bsigned = Bsigned,Asigned
X = (A + 23) // 24
if X > 1 and A % 24 == 1:
X -= 1 # No headroom needed on last multiplier
Y = (B+16) // 17
if Y > 1 and B % 17 == 1:
Y -= 1 # No headroom needed on last multiplier
count_MAC = X * Y
count_DFF = 0
if Preg:
count_DFF += A + B
# TODO: Assert on number of CARRY4s too
bn,_ = os.path.splitext(fn) bn,_ = os.path.splitext(fn)
...@@ -20,7 +40,8 @@ for fn in glob.glob('*.v'): ...@@ -20,7 +40,8 @@ for fn in glob.glob('*.v'):
print(''' print('''
`ifndef _AUTOTB `ifndef _AUTOTB
module __test ; module __test ;
wire [4095:0] assert_area = "cd %s; select t:DSP48E1 -assert-count 1; select t:* t:DSP48E1 %%d -assert-none"; wire [4095:0] assert_area = "cd {0}; select t:DSP48E1 -assert-count {1}; select t:FD* -assert-max {2}";
// {3} {4} {5} {6} X={7} Y={8}
endmodule endmodule
`endif `endif
''' % os.path.splitext(fn)[0], file=f) '''.format(os.path.splitext(fn)[0], count_MAC, count_DFF, A,B,Asigned,Bsigned,X,Y), file=f)
...@@ -19,12 +19,12 @@ if ! which iverilog > /dev/null ; then ...@@ -19,12 +19,12 @@ if ! which iverilog > /dev/null ; then
fi fi
#wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/generate.py -O generate_mul.py -o /dev/null #wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/generate.py -O generate_mul.py -o /dev/null
cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/generate.py generate_mul.py cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
python3 generate_mul.py PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
python3 ../assert_area.py python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\ ${MAKE:-make} -f ../../../../tools/autotest.mk $seed *__.v EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \ -p 'design -copy-to __test __test; \
synth_xilinx -abc9; \ synth_xilinx; \
design -copy-from __test *; \ design -copy-from __test *; \
select -assert-any __test; \ select -assert-any __test; \
script -scriptwire __test/w:assert_area'\ script -scriptwire __test/w:assert_area'\
......
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