Refine

architecture/run.sh

@@ -10,15 +10,17 @@ cd $1/work_$2
 
 touch .start
 
-if [ -f ../Makefile ]; then
-    make -C ..
+if [ -f ../run-test.sh ]; then
+	../run-test.sh
+	touch .stamp
+	exit 0
 else
     yosys -ql yosys.log ../../scripts/$2.ys
-fi
-if [ $? != 0 ] ; then
+    if [ $? != 0 ] ; then
         echo FAIL > ${1}_${2}.status
         touch .stamp
         exit 0
+    fi
 fi
 if [ -f "../../../../../techlibs/common/simcells.v" ]; then
     COMMON_PREFIX=../../../../../techlibs/common
@@ -69,14 +71,6 @@ elif [ "$1" = "synth_intel_cyclonev" ]; then
 elif [ "$1" = "synth_sf2" ]; then
     iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
 elif [ "$1" = "synth_xilinx" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-elif [ "$1" = "synth_xilinx_srl" ]; then
-    if grep 'fail' *.status; then
-	    echo fail > ${1}_${2}.status
-    else
-        echo pass > ${1}_${2}.status
-    fi
-    exit
     iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
 elif [ "$1" = "synth_greenpak4" ]; then
     iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v

architecture/synth_xilinx_srl/Makefile

-OUTDIR := work_synth_xilinx_srl
-YS := $(wildcard *.ys)
-TARGETS := $(patsubst %.ys,$(OUTDIR)/%.status,$(YS))
-
-.PHONY: all
-all: $(TARGETS)
-	echo ALL PASSED!
-
-$(OUTDIR)/test%.status: test%.ys
-	cd $(OUTDIR) && yosys -ql yosys$*.log ../$<
-	iverilog -DTEST$* $(OUTDIR)/synth$*.v -o $(OUTDIR)/testbench$*  testbench.v top.v ../common.v ../../../../techlibs/common/simcells.v ../../../../techlibs/xilinx/cells_sim.v
-	if ! vvp -N $(OUTDIR)/testbench$* > $(OUTDIR)/testbench$*.log 2>&1; then \
-		grep 'ERROR' $(OUTDIR)/testbench$*.log; \
-		echo fail > $@; \
-	elif grep 'ERROR' $(OUTDIR)/testbench$*.log || ! grep 'OKAY' $(OUTDIR)/testbench$*.log; then \
-		echo fail > $@; \
-	else \
-		echo pass > $@; \
-	fi
-
-$(OUTDIR)/test12.status:
-	wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O lfsr_generate.py
-	python3 lfsr_generate.py
-	cd $(OUTDIR) && yosys -ql yosys12.log ../test12.ys
-	iverilog -DTEST12 $(OUTDIR)/synth12.v -o $(OUTDIR)/testbench12  testbench.v top.v lfsr.v ../common.v ../../../../techlibs/common/simcells.v ../../../../techlibs/xilinx/cells_sim.v
-	if ! vvp -N $(OUTDIR)/testbench12 > $(OUTDIR)/testbench12.log 2>&1; then \
-		grep 'ERROR' $(OUTDIR)/testbench12.log; \
-		echo fail > $(OUTDIR)/test12.status; \
-	elif grep 'ERROR' $(OUTDIR)/testbench12.log || ! grep 'OKAY' $(OUTDIR)/testbench12.log; then \
-		echo fail > $(OUTDIR)/test12.status; \
-	else \
-		echo pass > $(OUTDIR)/test12.status; \
-	fi

architecture/synth_xilinx_srl/defines.vh

-`define N 131

architecture/synth_xilinx_srl/run-test.sh

 #!/bin/bash
+shopt -s extglob
 
 OPTIND=1
 seed=""    # default to no seed specified