Commit 5374bf55 by Miodrag Milanovic

Fix memory simulation scripts

parent 813415c7
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -a top
read_verilog ../top_mem.v
proc
memory_collect
sim -clock clk top
read_verilog ../top_mem.v
proc
memory_collect
sim -clockn clk top
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -d top
read_verilog -sv ../top_mem.v
proc
memory_collect
sim top
read_verilog ../top_mem.v
proc
memory_collect
sim -reset we_b top
read_verilog ../top_mem.v
proc
memory_collect
sim -resetn we_a top
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -rstlen 2 top
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -vcd vcd.vcd top
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -w top
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -w top
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