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yosys-tests
Commit 5374bf55 by Miodrag Milanovic
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Fix memory simulation scripts

parent 813415c7
Showing with 11 additions and 0 deletions
misc/sim/sim_a_mem.ys
read_verilog -sv ../top_mem.v read_verilog -sv ../top_mem.v
proc proc
memory_collect
sim -a top sim -a top
misc/sim/sim_clock_mem.ys
read_verilog ../top_mem.v read_verilog ../top_mem.v
proc proc
memory_collect
sim -clock clk top sim -clock clk top
misc/sim/sim_clockn.ys
read_verilog ../top_mem.v read_verilog ../top_mem.v
proc proc
memory_collect
sim -clockn clk top sim -clockn clk top
misc/sim/sim_d_mem.ys
read_verilog -sv ../top_mem.v read_verilog -sv ../top_mem.v
proc proc
memory_collect
sim -d top sim -d top
misc/sim/sim_mem.ys
read_verilog -sv ../top_mem.v read_verilog -sv ../top_mem.v
proc proc
memory_collect
sim top sim top
misc/sim/sim_reset.ys
read_verilog ../top_mem.v read_verilog ../top_mem.v
proc proc
memory_collect
sim -reset we_b top sim -reset we_b top
misc/sim/sim_resetn.ys
read_verilog ../top_mem.v read_verilog ../top_mem.v
proc proc
memory_collect
sim -resetn we_a top sim -resetn we_a top
misc/sim/sim_rstlen_mem.ys
read_verilog -sv ../top_mem.v read_verilog -sv ../top_mem.v
proc proc
memory_collect
sim -rstlen 2 top sim -rstlen 2 top
misc/sim/sim_vcd_mem.ys
read_verilog -sv ../top_mem.v read_verilog -sv ../top_mem.v
proc proc
memory_collect
sim -vcd vcd.vcd top sim -vcd vcd.vcd top
misc/sim/sim_w.ys
read_verilog -sv ../top_mem.v read_verilog -sv ../top_mem.v
proc proc
memory_collect
sim -w top sim -w top
misc/sim/sim_w_mem.ys
read_verilog -sv ../top_mem.v read_verilog -sv ../top_mem.v
proc proc
memory_collect
sim -w top sim -w top
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