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lvzhengyang
yosys-tests
Commits
5374bf55
Commit
5374bf55
authored
Jun 29, 2020
by
Miodrag Milanovic
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Fix memory simulation scripts
parent
813415c7
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11 changed files
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misc/sim/sim_a_mem.ys
+1
-0
misc/sim/sim_clock_mem.ys
+1
-0
misc/sim/sim_clockn.ys
+1
-0
misc/sim/sim_d_mem.ys
+1
-0
misc/sim/sim_mem.ys
+1
-0
misc/sim/sim_reset.ys
+1
-0
misc/sim/sim_resetn.ys
+1
-0
misc/sim/sim_rstlen_mem.ys
+1
-0
misc/sim/sim_vcd_mem.ys
+1
-0
misc/sim/sim_w.ys
+1
-0
misc/sim/sim_w_mem.ys
+1
-0
No files found.
misc/sim/sim_a_mem.ys
View file @
5374bf55
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -a top
misc/sim/sim_clock_mem.ys
View file @
5374bf55
read_verilog ../top_mem.v
proc
memory_collect
sim -clock clk top
misc/sim/sim_clockn.ys
View file @
5374bf55
read_verilog ../top_mem.v
proc
memory_collect
sim -clockn clk top
misc/sim/sim_d_mem.ys
View file @
5374bf55
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -d top
misc/sim/sim_mem.ys
View file @
5374bf55
read_verilog -sv ../top_mem.v
proc
memory_collect
sim top
misc/sim/sim_reset.ys
View file @
5374bf55
read_verilog ../top_mem.v
proc
memory_collect
sim -reset we_b top
misc/sim/sim_resetn.ys
View file @
5374bf55
read_verilog ../top_mem.v
proc
memory_collect
sim -resetn we_a top
misc/sim/sim_rstlen_mem.ys
View file @
5374bf55
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -rstlen 2 top
misc/sim/sim_vcd_mem.ys
View file @
5374bf55
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -vcd vcd.vcd top
misc/sim/sim_w.ys
View file @
5374bf55
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -w top
misc/sim/sim_w_mem.ys
View file @
5374bf55
read_verilog -sv ../top_mem.v
proc
memory_collect
sim -w top
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