Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
Commits
521b6e3d
Commit
521b6e3d
authored
Apr 21, 2019
by
Eddie Hung
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Remove incorrect comment
parent
8c483823
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
0 additions
and
1 deletions
+0
-1
architecture/synth_xilinx_srl/test14.ys
+0
-1
No files found.
architecture/synth_xilinx_srl/test14.ys
View file @
521b6e3d
...
@@ -5,7 +5,6 @@ rename -top synth
...
@@ -5,7 +5,6 @@ rename -top synth
clean -purge
clean -purge
write_verilog synth14.v
write_verilog synth14.v
# Check that non chain users block SRLs
cd synth; cd sr0; select t:SRLC32E -assert-count 1
cd synth; cd sr0; select t:SRLC32E -assert-count 1
cd synth; cd sr1; select t:SRLC32E -assert-count 1
cd synth; cd sr1; select t:SRLC32E -assert-count 1
cd synth; cd sr2; select t:SRLC32E -assert-count 1
cd synth; cd sr2; select t:SRLC32E -assert-count 1
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment