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yosys-tests
Commit 45402afc by SergeyDegtyar
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Review 'yosys' test group.

parent c0b775eb
Showing with 1549 additions and 1 deletions
run.sh
...@@ -16,7 +16,16 @@ if [ -f ../run-test.sh ]; then ...@@ -16,7 +16,16 @@ if [ -f ../run-test.sh ]; then
if [ $? != 0 ] ; then if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status echo FAIL > ${1}_${2}.status
else else
echo PASS > ${1}_${2}.status if [ -f "../$2.pat" ]; then
expectation=$(<../$2.pat)
if grep "$expectation" yosys.log; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
else
echo PASS > ${1}_${2}.status
fi
fi fi
touch .stamp touch .stamp
exit exit
......
yosys_reviewed/.gitignore 0 → 100644
*/work_*/
/.stamp
/run-test.mk
yosys_reviewed/Makefile 0 → 100644
PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
all::
run-test.mk: ./generate.py
@$(PYTHON_EXECUTABLE) ./generate.py > run-test.mk
include run-test.mk
.PHONY: all clean
yosys_reviewed/generate.py 0 → 100644
import os
is_heavy_enabled = int(os.getenv('ENABLE_HEAVY_TESTS', '0')) == 1
for root, dirs, files in sorted(os.walk(".")):
for file in files:
if file.endswith('run-test.sh'):
dir = os.path.basename(root)
work = os.path.splitext(file)[0]
heavy = os.path.exists(os.path.join(dir, "heavy_test"))
is_disabled = os.path.exists(os.path.join(dir, work + ".disable"))
print("all:: {0}/work_{1}/.stamp\n"
"{0}/work_{1}/.stamp:".format(dir, work))
if (is_disabled):
print("\t@echo 'Skipping disabled test {0}..'".format(dir, work))
continue
if (heavy and not is_heavy_enabled):
print("\t@echo 'Skipping heavy test {0}..'".format(dir, work))
continue
print("\t@echo 'Running {2}{1}..'\n"
"\t@../run.sh {0} {1}\n"
"clean::\n"
"\t@echo 'Cleaning {1}..'\n"
"\t@rm -rf {0}/work_{1}".format(dir, work, "heavy " if heavy else ""))
print(".PHONY: all clean")
yosys_reviewed/yosys/run-test.pat 0 → 100644
yosys -- Yosys Open SYnthesis Suite
yosys_reviewed/yosys/run-test.sh 0 → 100755
#!/bin/bash
yosys ../run_script.ys >> yosys.log
yosys_reviewed/yosys/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_backends/run-test.sh 0 → 100755
#!/bin/bash
yosys -b blif ../run_script.ys >> yosys.log
yosys_reviewed/yosys_backends/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_command_list/run-test.sh 0 → 100755
#!/bin/bash
yosys -H >> yosys.log
yosys_reviewed/yosys_command_list/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_dependencies/run-test.pat 0 → 100644
yosys -- Yosys Open SYnthesis Suite
yosys_reviewed/yosys_dependencies/run-test.sh 0 → 100755
#!/bin/bash
yosys -E tt.txt ../run_script.ys >> yosys.log
yosys_reviewed/yosys_dependencies/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_detailed_timing/run-test.sh 0 → 100755
#!/bin/bash
yosys -d ../run_script.ys >> yosys.log
yosys_reviewed/yosys_detailed_timing/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_enable_tracing/run-test.sh 0 → 100755
#!/bin/bash
yosys -X ../run_script.ys >> yosys.log
yosys_reviewed/yosys_enable_tracing/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_exec_command/run-test.sh 0 → 100755
#!/bin/bash
yosys -p help >> yosys.log
yosys_reviewed/yosys_exec_command/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_frontends/run-test.pat 0 → 100644
Parsing `../top.v' using frontend `verilog'
yosys_reviewed/yosys_frontends/run-test.sh 0 → 100755
#!/bin/bash
yosys -f verilog ../top.v >> yosys.log
yosys_reviewed/yosys_frontends/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_globally_en_log_mes/run-test.sh 0 → 100755
#!/bin/bash
yosys -g ../run_script.ys >> yosys.log
yosys_reviewed/yosys_globally_en_log_mes/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_header/run-test.pat 0 → 100644
Parsing `../top.v' using frontend `verilog'
yosys_reviewed/yosys_header/run-test.sh 0 → 100755
#!/bin/bash
yosys -P TOP:top.v ../top.v >> yosys.log
yosys_reviewed/yosys_header/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_headers/run-test.sh 0 → 100755
#!/bin/bash
yosys -v 3 ../run_script.ys >> yosys.log
yosys_reviewed/yosys_headers/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_help/run-test.pat 0 → 100644
print the help message for the specified command
yosys_reviewed/yosys_help/run-test.sh 0 → 100755
#!/bin/bash
yosys -h >> yosys.log
yosys_reviewed/yosys_help/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_help_for_command/run-test.sh 0 → 100755
#!/bin/bash
yosys -h abc >> yosys.log
yosys_reviewed/yosys_help_for_command/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_log_file/run-test.pat 0 → 100644
yosys -- Yosys Open SYnthesis Suite
yosys_reviewed/yosys_log_file/run-test.sh 0 → 100755
#!/bin/bash
yosys -l yosys.log ../run_script.ys
yosys_reviewed/yosys_log_file/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_log_file_lb_mode/run-test.pat 0 → 100644
yosys -- Yosys Open SYnthesis Suite
yosys_reviewed/yosys_log_file_lb_mode/run-test.sh 0 → 100755
#!/bin/bash
yosys -L yosys.log ../run_script.ys
yosys_reviewed/yosys_log_file_lb_mode/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_macro/run-test.sh 0 → 100755
#!/bin/bash
yosys -D YOSYS ../run_script.ys >> yosys.log
yosys_reviewed/yosys_macro/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_no_banner/run-test.pat 0 → 100644
Executing script file `../run_script.ys'
yosys_reviewed/yosys_no_banner/run-test.sh 0 → 100755
#!/bin/bash
yosys -Q ../run_script.ys >> yosys.log
yosys_reviewed/yosys_no_banner/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_no_footer/run-test.sh 0 → 100755
#!/bin/bash
yosys -T ../run_script.ys >> yosys.log
yosys_reviewed/yosys_no_footer/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_quiet/run-test.sh 0 → 100755
#!/bin/bash
yosys -q ../run_script.ys >> yosys.log
yosys_reviewed/yosys_quiet/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_randomize_alloc_point_addr/run-test.sh 0 → 100755
#!/bin/bash
yosys -M ../run_script.ys >> yosys.log
yosys_reviewed/yosys_randomize_alloc_point_addr/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_regexp/run-test.pat 0 → 100644
yosys -- Yosys Open SYnthesis Suite
yosys_reviewed/yosys_regexp/run-test.sh 0 → 100755
#!/bin/bash
yosys -W Parsing ../run_script.ys >> yosys.log
yosys_reviewed/yosys_regexp/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_regexp_e/run-test.pat 0 → 100644
yosys -- Yosys Open SYnthesis Suite
yosys_reviewed/yosys_regexp_e/run-test.sh 0 → 100755
#!/bin/bash
yosys -e abc ../run_script.ys >> yosys.log
yosys_reviewed/yosys_regexp_e/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_regexp_w/run-test.pat 0 → 100644
yosys -- Yosys Open SYnthesis Suite
yosys_reviewed/yosys_regexp_w/run-test.sh 0 → 100755
#!/bin/bash
yosys -w abc ../run_script.ys >> yosys.log
yosys_reviewed/yosys_regexp_w/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_script/run-test.pat 0 → 100644
Executing script file `../run_script.ys'
yosys_reviewed/yosys_script/run-test.sh 0 → 100755
#!/bin/bash
yosys -s ../run_script.ys >> yosys.log
yosys_reviewed/yosys_script/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_synth/run-test.sh 0 → 100755
#!/bin/bash
yosys -S ../run_script.ys >> yosys.log
yosys_reviewed/yosys_synth/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_tcl_script/run-test.sh 0 → 100755
#!/bin/bash
yosys -c ../run_script.tcl >> yosys.log
yosys_reviewed/yosys_tcl_script/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_time/run-test.sh 0 → 100755
#!/bin/bash
yosys -t ../run_script.ys >> yosys.log
yosys_reviewed/yosys_time/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_version/run-test.sh 0 → 100755
#!/bin/bash
yosys -V ../run_script.ys >> yosys.log
yosys_reviewed/yosys_version/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
yosys_reviewed/yosys_write_des_to_file/run-test.sh 0 → 100755
#!/bin/bash
yosys -o yosys.blif ../run_script.ys
cp yosys.blif yosys.log
yosys_reviewed/yosys_write_des_to_file/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
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