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yosys-tests
Unverified Commit 3cd49561 by Miodrag Milanović Committed by GitHub
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Merge pull request #47 from SergeyDegtyar/master 

 Add tests for error messages to 'frontends' group;  Test write_btor_no_driver removed.
parents a4a44c27 dd522d08
Showing with 3826 additions and 19 deletions
backends/Makefile
......@@ -35,7 +35,7 @@ $(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor
$(eval $(call template,write_btor_pmux,write_btor_pmux))
$(eval $(call template,write_btor_and_or,write_btor_and_or))
$(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type write_btor_no_driver))
$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type))
#write_edif
$(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
......
backends/run.sh
......@@ -33,8 +33,6 @@ if echo "$1" | grep ".*_error"; then
expected_string="ERROR: No top module found."
elif [ "$2" = "write_btor_unsupported_cell_type" ]; then
expected_string="ERROR: Unsupported cell type: "
elif [ "$2" = "write_btor_no_driver" ]; then
expected_string="ERROR: No driver for signal bit "
elif [ "$2" = "write_edif_cyclic_dependency" ]; then
expected_string="ERROR: Cyclic dependency between modules found! Cycle includes module "
elif [ "$2" = "write_edif_constant_nodes" ]; then
......
backends/scripts/write_btor_no_driver.ys deleted 100644 → 0
read_verilog ../top.v
memory
write_btor btor.btor
frontends/Makefile
......@@ -27,6 +27,7 @@ $(eval $(call template,read_blif_mux,read_blif read_blif_attr read_blif_buf read
$(eval $(call template,read_blif_pmux,read_blif read_blif_attr read_blif_buf read_blif_cname read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_tri,read_blif read_blif_attr read_blif_buf read_blif_conn read_blif_param read_blif_sop read_blif_wideports))
$(eval $(call template,read_blif_eblif,read_blif_eblif))
$(eval $(call template,read_blif_error, read_blif_syntax_error read_blif_duplicate_defenition ))
#read_ilang
$(eval $(call template,read_ilang,read_ilang read_ilang_selected))
......@@ -34,6 +35,7 @@ $(eval $(call template,read_ilang_fsm,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_mem,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_mux,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected))
$(eval $(call template,read_ilang_error,read_ilang_parse_error))
#read_json
$(eval $(call template,read_json,read_json))
......@@ -42,6 +44,7 @@ $(eval $(call template,read_json_logic,read_json))
$(eval $(call template,read_json_mem,read_json_mem))
$(eval $(call template,read_json_mux,read_json))
$(eval $(call template,read_json_tri,read_json))
$(eval $(call template,read_json_error, read_json_nonstring_key read_json_nonarray_bits_attr read_json_unexpected_eof read_json_invalid_direction read_json_no_bits read_json_no_direction read_json_unexpected_char ))
#read_liberty read_liberty_lib
$(eval $(call template,read_liberty,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
......@@ -55,6 +58,7 @@ $(eval $(call template,read_liberty_latch,read_liberty read_liberty_nooverwrite
$(eval $(call template,read_liberty_latch_n,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_diff_inv,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_tri,read_liberty read_liberty_nooverwrite read_liberty_ignore_miss_func read_liberty_ignore_miss_dir read_liberty_ignore_miss_data_latch read_liberty_setattr ))
$(eval $(call template,read_liberty_error, read_liberty_invalid_bus_type read_liberty_unsupp_type_for_bus read_liberty_bus_interface_only_in_lib_mode read_liberty_latch_has_no_data_in read_liberty_miss_func_on_output read_liberty_ff_has_no_next_stage_attr read_liberty_parse_error_in_function read_liberty_cant_resolve_wire_name read_liberty_missing_direction read_liberty_cant_open_input_file read_liberty_redefenition_of_module ))
#read_aiger
$(eval $(call template,read_aiger,read_aiger read_aiger_proc read_aiger_ascii read_aiger_module read_aiger_clk read_aiger_clk_module ))
......@@ -62,6 +66,7 @@ $(eval $(call template,read_aiger_latch,read_aiger_aig))
$(eval $(call template,read_aiger_logic,read_aiger_aig))
$(eval $(call template,read_aiger_ff,read_aiger_aig))
$(eval $(call template,read_aiger_mult,read_aiger_aig))
$(eval $(call template,read_aiger_error, read_aiger_cant_interpret_first_char read_aiger_unsup_aiger_file read_aiger_invalid_aiger_header read_aiger_cant_interpret_as_input read_aiger_cant_interpret_as_and read_aiger_bad_state_property read_aiger_invalid_reset_literal read_aiger_duplicate_definition ))
#read
# read_vhdl87 read_vhdl93 read_vhdl2k read_vhdl2008 read_vhdl - ERROR: This version of Yosys is built without Verific support.
......@@ -72,9 +77,11 @@ $(eval $(call template,read_verilog,read_verilog read_verilog_assert_assumes rea
#verilog_defaults
$(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push verilog_defaults_pop verilog_defaults_clear))
$(eval $(call template,verilog_defaults_error,verilog_defaults_missing_arg verilog_defaults_extra_arg))
#verilog_defines
$(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
$(eval $(call template,verilog_defines_error,verilog_defines_extra_arg))
#verilog_lexer
$(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))
......
frontends/read_aiger_error/aiger_ff1.aiger 0 → 100755
aaga 7 2 1 2 4
2
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_aiger_error/aiger_ff2.aiger 0 → 100755
aag 7 2 1 2 4 a
2
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_aiger_error/aiger_ff3.aiger 0 → 100755
aag 7 2 1 2 4
2 s
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_aiger_error/aiger_ff4.aiger 0 → 100755
aag 7 2 1 2 4
2
4
6 8
6
7f
8 4 10
10 13 15
12 2 6
14 3 7
frontends/read_blif_error/blif_e1.blif 0 → 100755
# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
.modell top
.inputs C S[0] S[1]
.outputs Y[0] Y[1] Y[2] Y[3]
.names $false
.names $true
1
.names $undef
.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
.names $false $1\Y[3:0][0]
1 1
.names $false $1\Y[3:0][1]
1 1
.names $false $1\Y[3:0][2]
1 1
.names $false $1\Y[3:0][3]
1 1
.names $procmux$3_Y[0] $0\Y[3:0][0]
1 1
.names $procmux$3_Y[1] $0\Y[3:0][1]
1 1
.names $procmux$3_Y[2] $0\Y[3:0][2]
1 1
.names $procmux$3_Y[3] $0\Y[3:0][3]
1 1
.end
frontends/read_blif_error/blif_seg_fault.blif 0 → 100755
# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
.model top
.inputs C S[0] S[1]
.outputs Y[0] Y[1] Y[2] Y[3]
.names $false
.names $true
1
.names $undef
.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
.names $false $1\Y[3:0][0]
1 1
.names
1 1
.names $false $1\Y[3:0][2]
1 1
.names $false $1\Y[3:0][3]
1 1
.names $procmux$3_Y[0] $0\Y[3:0][0]
1 1
.names $procmux$3_Y[1] $0\Y[3:0][1]
1 1
.names $procmux$3_Y[2] $0\Y[3:0][2]
1 1
.names $procmux$3_Y[3] $0\Y[3:0][3]
1 1
.end
frontends/read_blif_error/eblif_seg_fault.eblif 0 → 100755
.model top
.names a b
.inputs a
.outputs b
.conn a b
.names a b c
11 1
.cname $my_and_gate
.latch a_and_b dff_q re clk 0
.attr my_design.v:42
.end
frontends/read_blif_error/top.v 0 → 100755
module top(C, S, Y);
input C;
input [1:0] S;
output reg [3:0] Y;
initial Y = 0;
always @(posedge C) begin
case (S)
2'b00: Y <= 4'b0001;
2'b01: Y <= 4'b0010;
2'b10: Y <= 4'b0100;
2'b11: Y <= 4'b1000;
endcase
end
endmodule
frontends/read_ilang_error/file.il 0 → 100644
autoidx 15
attribute \cells_not_processed 1
attribute \src "top.v:1"
module \top
attribute \src "top.v:17"
wire $0\B[0:0]
attribute \src "top.v:19"
attribute \unused_bits "1"
wire width 2 $and$top.v:19$4_Y
attribute \src "top.v:18"
wire $logic_and$top.v:18$2_Y
attribute \src "top.v:20"
wire $logic_and$top.v:20$6_Y
attribute \src "top.v:20"
wire $logic_not$top.v:20$5_Y
attribute \src "top.v:18"
wire $logic_or$top.v:18$3_Y
attribute \src "top.v:20"
wire $logic_or$top.v:20$7_Y
attribute \src "top.v:21"
attribute \unused_bits "1"
wire width 2 $or$top.v:21$8_Y
wire $procmux$10_Y
attribute \src "top.v:8"
wire input 5 \A
attribute \init 1'0
attribute \src "top.v:9"
wire output 6 \B
attribute \src "top.v:6"
wire input 4 \clk
attribute \src "top.v:3"
wire width 2 input 1 \x
attribute \src "top.v:4"
wire width 2 input 2 \y
attribute \src "top.v:5"
wire width 2 input 3 \z
attribute \src "top.v:19"
cell $and $and$top.v:19$4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \z
connect \Y $and$top.v:19$4_Y
end
attribute \src "top.v:18"
cell $logic_and $logic_and$top.v:18$2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \y
connect \B \z
connect \Y $logic_and$top.v:18$2_Y
end
attribute \src "top.v:20"
cell $logic_and $logic_and$top.v:20$6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \y
connect \B $logic_not$top.v:20$5_Y
connect \Y $logic_and$top.v:20$6_Y
end
attribute \src "top.v:20"
cell $logic_not $logic_not$top.v:20$5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \z
connect \Y $logic_not$top.v:20$5_Y
end
attribute \src "top.v:18"
cell $logic_or $logic_or$top.v:18$3
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:18$2_Y
connect \Y $logic_or$top.v:18$3_Y
end
attribute \src "top.v:20"
cell $logic_or $logic_or$top.v:20$7
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:20$6_Y
connect \Y $logic_or$top.v:20$7_Y
end
attribute \src "top.v:21"
cell $or $or$top.v:21$8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \x
connect \Y $or$top.v:21$8_Y
end
attribute \src "top.v:17"
cell $dff $procdff$14
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D $0\B[0:0]
connect \Q \B
end
attribute \src "top.v:18"
cell $mux $procmux$10
parameter \WIDTH 1
connect \A \B
connect \B $and$top.v:19$4_Y [0]
connect \S $logic_or$top.v:18$3_Y
connect \Y $procmux$10_Y
end
attribute \src "top.v:20"
cell $mux $procmux$12
parameter \WIDTH 1
connect \A $procmux$10_Y
connect \B $or$top.v:21$8_Y [0]
connect \S $logic_or$top.v:20$7_Y
connect \Y $0\B[0:0]
end
end
frontends/read_ilang_error/ilang.ilang 0 → 100644
# Generated by Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
autoidx 15
attribute \cells_not_processed 1
attribute \src "top.v:1"
module \top
attribute \src "top.v:17"
wire $0\B[0:0]
attribute \src "top.v:19"
attribute \unused_bits "1"
wire width 2 $and$top.v:19$4_Y
attribute \src "top.v:18"
wire $logic_and$top.v:18$2_Y
attribute \src "top.v:20"
wire $logic_and$top.v:20$6_Y
attribute \src "top.v:20"
wire $logic_not$top.v:20$5_Y
attribute \src "top.v:18"
wire $logic_or$top.v:18$3_Y
attribute \src "top.v:20"
wire $logic_or$top.v:20$7_Y
attribute \src "top.v:21"
attribute \unused_bits "1"
wire width 2 $asdfasdfasfor$top.v:21$8_Y
wire $procmux$10_Y
attribute \src "top.v:8"
wire input 5 \A
attribute \init 1'0
attribute \src "top.v:9"
wire output 6 \B
attribute \src "top.v:6"
wire input 4 \clk
attribute \src "top.v:3"
wire width 2 input 1 \x
attribute \src "top.v:4"
wire width 2 input 2 \y
attribute \src "top.v:5"
wire width 2 input 3 \z
attribute \src "top.v:19"
cell $and $and$top.v:19$4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \z
connect \Y $and$top.v:19$4_Y
end
attribute \src "top.v:18"
cell $logic_and $logic_and$top.v:18$2
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \y
connect \B \z
connect \Y $logic_and$top.v:18$2_Y
end
attribute \src "top.v:20"
cell $logic_and $logic_and$top.v:20$6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \y
connect \B $logic_not$top.v:20$5_Y
connect \Y $logic_and$top.v:20$6_Y
end
attribute \src "top.v:20"
cell $logic_not $logic_not$top.v:20$5
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A \z
connect \Y $logic_not$top.v:20$5_Y
end
attribute \src "top.v:18"
cell $logic_or $logic_or$top.v:18$3
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:18$2_Y
connect \Y $logic_or$top.v:18$3_Y
end
attribute \src "top.v:20"
cell $logic_or $logic_or$top.v:20$7
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \x
connect \B $logic_and$top.v:20$6_Y
connect \Y $logic_or$top.v:20$7_Y
end
attribute \src "top.v:21"
cell $or $or$top.v:21$8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
connect \A \A
connect \B \x
connect \Y $or$top.v:21$8_Y
end
attribute \src "top.v:17"
cell $dff $procdff$14
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D $0\B[0:0]
connect \Q \B
end
attribute \src "top.v:18"
cell $mux $procmux$10
parameter \WIDTH 1
connect \A \B
connect \B $and$top.v:19$4_Y [0]
connect \S $logic_or$top.v:18$3_Y
connect \Y $procmux$10_Y
end
attribute \src "top.v:20"
cell $mux $procmux$12
parameter \WIDTH 1
connect \A $procmux$10_Y
connect \B $or$top.v:21$8_Y [0]
connect \S $logic_or$top.v:20$7_Y
connect \Y $0\B[0:0]
end
end
frontends/read_ilang_error/testbench.v 0 → 100644
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_comb out_test(.A(patt_B), .B(B));
endmodule
frontends/read_ilang_error/top.v 0 → 100644
module top
(
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
frontends/read_json_error/json1.json 0 → 100644
{
"creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
"modules": {
"top": {
"attributes": {
"cells_not_processed": 1,
"src": "top.v:1"
},
"ports": {
"x": {
"directisson": "inpusdfsdft",
"bitsss": [ a ]
},
"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
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}
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}
frontends/read_json_error/json7.json 0 → 100644
{
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"cin": {
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},
"$procdff$6": {
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"WIDTH": 1
},
"attributes": {
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"port_directions": {
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},
"$procdff$7": {
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frontends/read_json_error/json8.json 0 → 100644
{
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"modules": {
"top": {
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"ports": {
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"bits": [ 2 ]
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"y": {
"direction": "input",
"bits": [ 3 ]
},
"cin": {
"direction": "input",
"bits": [ 4 ]
},
"A": {
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},
"cout": {
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}
},
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},
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},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$top.v:21$4": {
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"type": "$add",
"parameters": {
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}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": 0,
"WIDTH": 1
},
"attributes": {
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"port_directions": {
"CLK": "input",
"D": "input",
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3: {
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"cin": {
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"cout": {
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}
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"x": {
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"y": {
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}
}
frontends/read_liberty_error/lib.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,pf);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib1.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : 2 ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib2.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!s)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib3.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
function : "(!A*)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/lib4.lib 0 → 100644
library (Cell_EX2) {
technology (cmos);
delay_model : table_lookup;
capacitive_load_unit (1,f);
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1A";
default_fanout_load : 0.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
input_threshold_pct_rise : 50.0;
input_threshold_pct_fall : 50.0;
output_threshold_pct_rise : 50.0;
output_threshold_pct_fall : 50.0;
slew_lower_threshold_pct_fall : 10.0;
slew_lower_threshold_pct_rise : 10.0;
slew_upper_threshold_pct_fall : 90.0;
slew_upper_threshold_pct_rise : 90.0;
lu_table_template (delay_template4x4) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1,2,3,4");
index_2 ("1,2,3,4");
}
cell (top) {
area : 2;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00376;
rise_capacitance : 0.00376;
fall_capacitance : 0.00377;
rise_capacitance_range (0.00376 , 0.00376) ;
fall_capacitance_range (0.00377 , 0.00377) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.08000;
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.01000, 0.02000, 0.04000, 0.08000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
cell (INVX2) {
area : 3;
cell_footprint : inv;
pin (A) {
direction : input ;
capacitance : 0.00676;
rise_capacitance : 0.00676;
fall_capacitance : 0.00677;
rise_capacitance_range (0.00676 , 0.00676) ;
fall_capacitance_range (0.00677 , 0.00677) ;
clock : false;
max_transition : 1.0;
}
pin (Y) {
direction : output;
max_capacitance : 0.16000;
function : "(!A)";
timing () {
related_pin : "A";
timing_sense : negative_unate;
cell_rise (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.05545, 0.08432, 0.13771, 0.24632", \
"0.07093, 0.10601, 0.16334, 0.26969", \
"0.09321, 0.13663, 0.20648, 0.32107", \
"0.12336, 0.18027, 0.26781, 0.40737");
}
rise_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.09501, 0.14667, 0.25660, 0.48700", \
"0.13380, 0.18147, 0.28263, 0.50271", \
"0.19812, 0.25305, 0.35174, 0.55511", \
"0.32615, 0.38683, 0.49515, 0.69333");
}
cell_fall (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.04962, 0.07644, 0.12297, 0.21732", \
"0.06032, 0.09421, 0.14752, 0.24018", \
"0.07225, 0.11581, 0.18296, 0.28919", \
"0.08114, 0.13786, 0.22567, 0.36035");
}
fall_transition (delay_template4x4) {
index_1 ("0.12500, 0.25000, 0.50000, 1.00000");
index_2 ("0.02000, 0.04000, 0.08000, 0.16000");
values ("0.08067, 0.12114, 0.20638, 0.38782", \
"0.11950, 0.15830, 0.23419, 0.40548", \
"0.19046, 0.23320, 0.31117, 0.46523", \
"0.32214, 0.37613, 0.46164, 0.61834");
}
}
}
}
}
frontends/read_liberty_error/libff.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "dff";
ff("IQ", "IQN") {
clocked_on : " CLK ";
clear : " CLR ";
}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_error/liblat.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
clear : "CLR" ;}
pin(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_error/liblat1.lib 0 → 100644
library(top) {
/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1uA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit(1,pf);
/* positive edge triggered D flip-flop with active low reset */
cell(top) {
area : 972;
cell_footprint : "latch";
latch(IQ, IQN) {
enable : "CLK" ;
data_in : "D" ;
clear : "CLR" ;}
type ( BUS4 ) {
base_type : arraysss ;
data_type : bit ;
bit_width : 4 ;
bit_from : 0 ;
bit_to : 3 ;
downto :false ;
}
bus(D) {
direction : input;
capacitance : 0.0225;
timing() { /* hold time constraint for a rising transition on G */
timing_type : hold_rising;
rise_constraint(scalar) { values("-0.298"); }
fall_constraint(scalar) { values("-0.298"); }
related_pin : "CLK";
}
timing() { /* setup time constraint for a rising transition on G */
timing_type : setup_rising;
rise_constraint(scalar) { values("0.018"); }
fall_constraint(scalar) { values("0.018"); }
related_pin : "CLK";
}
} /* end of pin D */
pin ( CLK ) {
direction : input;
capacitance : 0.0585;
clock : true;
} /* end of pin CLK */
pin ( CLR ) {
direction : input;
capacitance : 0.0135;
} /* end of pin CLR */
pin ( Q ) {
direction : output;
function : "IQ";
timing () { /* propagation delay from rising edge of CLK to Q */
timing_type : rising_edge;
cell_rise(lu5x5) { values( "0.018" );}
rise_transition(lu5x5) { values( "0.018" );}
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLK";
} /* end of Q timing related to CLK */
timing () { /* propagation delay from falling edge of clear to Q=0 */
timing_type : clear;
timing_sense : positive_unate;
cell_fall(lu5x5) { values( "0.018" );}
fall_transition(lu5x5) { values( "0.018" );}
related_pin : "CLR";
} /* end of Q timing related to CLR */
} /* end of pin Q */
} /* end of cell dff */
}
frontends/read_liberty_error/liblat2.lib 0 → 100644
library (ExamBus) {
date : "May 14, 2002";
revision : 2002.05;
bus_naming_style :"%s[%d]";/* Optional; this is the
default */
type (bus4) {
base_type : array;/* Required */
data_type : bit;/* Required if base_type is array */
bit_width : 4;/* Optional; default is 1 */
bit_from : 0;/* Optional MSB; defaults to 0 */
bit_to : 3;/* Optional LSB; defaults to 0 */
downto : false;/* Optional; defaults to false */
}
cell (bused_cell) {
area : 10;
bus (A) {
bus_type : bus4;
direction : input;
capacitance : 3;
pin (A[0:2]) {
capacitance : 2;
}
pin (A[3]) {
capacitance : 2.5;
}
}
bus (B) {
bus_type : bus4;
capacitance : 2;
}
pin (E) {
direction : input ;
capacitance : 2 ;
}
bus(X) {
bus_type : bus4;
direction : output;
capacitance : 1;
pin (X[0:3]) {
function : "A & B’";
timing() {
related_pin : "A B";
/* A[0] and B[0] are related to X[0],
A[1] and B[1] are related to X[1], etc. */
}
}
}
bus (Y) {
bus_type : bus4;
direction : output;
capacitance : 1;
pin (Y[0:3]) {
function : "B";
three_state : "!E";
timing () {
related_pin : "A[0:3] B E";
}
internal_power() {
when: "E" ;
related_pin : B ;
power() {
}
}
internal_power() {
related_pin : B ;
power() {
}
}
}
}
bus (Z) {
bus_type : bus4;
direction : output;
pin (Z[0:1]) {
function : "!A[0:1]";
timing () {
related_pin : "A[0:1]";
}
internal_power() {
related_pin : "A[0:1]";
power() {
}
}
}
pin (Z[2]) {
function : "A[2]";
timing () {
related_pin : "A[2]";
}
internal_power() {
related_pin : "A[0:1]";
power() {
}
}
}
pin (Z[3]) {
function : "!A[3]";
timing () {
related_pin : "A[3]";
}
internal_power() {
related_pin : "A[0:1]";
power() {
}
}
}
}
pin_opposite("Y[0:1]","Z[0:1]");
/* Y[0] is opposite to Z[0], etc. */
pin_equal("Y[2:3] Z[2:3]");
/* Y[2], Y[3], Z[2], and Z[3] are equal */
cell (bused_cell2) {
area : 20;
bus (A) {
bus_type : bus41;
direction : input;
capacitance : 1;
pin (A[0:3]) {
capacitance : 2;
}
pin (A[3]) {
capacitance : 2.5;
}
}
bus (B) {
bus_type : bus4;
direction : input;
capacitance : 2;
}
pin (E) {
direction : input ;
capacitance : 2 ;
bus(X) {
bus_type : bus4;
direction : output;
capacitance : 1;
pin (X[0:3]) {
function : "A & B’";
timing() {
related_pin : "A B";
/* A[0] and B[0] are related to X[0],
A[1] and B[1] are related to X[1], etc. */
}
}
}
}
frontends/read_liberty_error/testbench.v 0 → 100644
module testbench;
reg a;
wire b;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 a = 0;
repeat (10000) begin
#5 a = ~a;
end
$display("OKAY");
end
top uut (
.A(a),
.Y(b)
);
assert_comb b_test(.A(~a),.B(b));
endmodule
frontends/run.sh
......@@ -10,34 +10,120 @@ cd $1/work_$2
touch .start
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
# cases where 'syntax error' or other errors are expected
if echo "$1" | grep ".*_error"; then
expected_string=""
#Change checked string for check other errors
if [ "$2" = "read_aiger_cant_interpret_first_char" ]; then
expected_string="ERROR: Line 80: cannot interpret first character"
elif [ "$2" = "read_aiger_unsup_aiger_file" ]; then
expected_string="ERROR: Unsupported AIGER file!"
elif [ "$2" = "read_aiger_invalid_aiger_header" ]; then
expected_string="ERROR: Invalid AIGER header"
elif [ "$2" = "read_aiger_cant_interpret_as_input" ]; then
expected_string="ERROR: Line 2 cannot be interpreted as an input!"
elif [ "$2" = "read_aiger_cant_interpret_as_and" ]; then
expected_string="ERROR: Line 6 cannot be interpreted as an AND!"
elif [ "$2" = "read_aiger_bad_state_property" ]; then
expected_string="ERROR: Line 4 cannot be interpreted as a bad state property!"
elif [ "$2" = "read_aiger_invalid_reset_literal" ]; then
expected_string="ERROR: Line 1 has invalid reset literal for latch!"
elif [ "$2" = "read_aiger_duplicate_definition" ]; then
expected_string="ERROR: Duplicate definition of module top!"
elif [ "$2" = "read_blif_syntax_error" ]; then
expected_string="ERROR: Syntax error in line"
elif [ "$2" = "read_blif_duplicate_defenition" ]; then
expected_string="ERROR: Duplicate definition of module "
elif [ "$2" = "read_ilang_parse_error" ]; then
expected_string="ERROR: Parser error in line "
elif [ "$2" = "read_json_nonstring_key" ]; then
expected_string="ERROR: Unexpected non-string key in JSON dict."
elif [ "$2" = "read_json_nonarray_bits_attr" ]; then
expected_string=" has non-array bits attribute."
elif [ "$2" = "read_json_unexpected_eof" ]; then
expected_string="ERROR: Unexpected EOF in JSON file."
elif [ "$2" = "read_json_invalid_direction" ]; then
expected_string="ERROR: JSON port node 'x' has invalid 'insdfasdfput' direction attribute."
elif [ "$2" = "read_json_no_bits" ]; then
expected_string=" has no bits attribute."
elif [ "$2" = "read_json_no_direction" ]; then
expected_string=" has no direction attribute."
elif [ "$2" = "read_json_unexpected_char" ]; then
expected_string="ERROR: Unexpected character in JSON file: "
elif [ "$2" = "verilog_defaults_missing_arg" ]; then
expected_string="ERROR: Command syntax error: Missing argument."
elif [ "$2" = "verilog_defaults_extra_arg" ]; then
expected_string="ERROR: Command syntax error: Extra argument."
elif [ "$2" = "verilog_defines_extra_arg" ]; then
expected_string="ERROR: Command syntax error: Extra argument."
elif [ "$2" = "read_liberty_invalid_bus_type" ]; then
expected_string="ERROR: Missing or invalid direction for bus B on cell bused_cell."
elif [ "$2" = "read_liberty_unsupp_type_for_bus" ]; then
expected_string="ERROR: Unknown or unsupported type for bus interface D on cell top."
elif [ "$2" = "read_liberty_bus_interface_only_in_lib_mode" ]; then
expected_string="ERROR: Error in cell top: bus interfaces are only supported in -lib mode."
elif [ "$2" = "read_liberty_latch_has_no_data_in" ]; then
expected_string="ERROR: Latch cell top has no data_in and/or enable attribute."
elif [ "$2" = "read_liberty_miss_func_on_output" ]; then
expected_string="ERROR: Missing function on output Y of cell top."
elif [ "$2" = "read_liberty_ff_has_no_next_stage_attr" ]; then
expected_string="ERROR: FF cell top has no next_state and/or clocked_on attribute."
elif [ "$2" = "read_liberty_parse_error_in_function" ]; then
expected_string="ERROR: Parser error in function expr "
elif [ "$2" = "read_liberty_cant_resolve_wire_name" ]; then
expected_string="ERROR: Can't resolve wire name s."
elif [ "$2" = "read_liberty_missing_direction" ]; then
expected_string="ERROR: Missing or invalid direction for pin A on cell top."
elif [ "$2" = "read_liberty_cant_open_input_file" ]; then
expected_string="ERROR: Can't open input file \`../libbbb.lib' for reading: No such file or directory"
elif [ "$2" = "read_liberty_redefenition_of_module" ]; then
expected_string="ERROR: Re-definition of cell/module top!"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo FAIL > ${1}_${2}.status
else
if grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
fi
else
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
sed -i 's/reg =/dummy =/' ./synth.v
fi
sed -i 's/reg =/dummy =/' ./synth.v
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
else
else
COMMON_PREFIX=/usr/local/share/yosys
fi
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
fi
if ! vvp -N testbench > testbench.log 2>&1; then
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
else
echo PASS > ${1}_${2}.status
fi
fi
touch .stamp
frontends/scripts/read_aiger_bad_state_property.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch1.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_cant_interpret_as_and.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff4.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_cant_interpret_as_input.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff3.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_cant_interpret_first_char.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger1.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_duplicate_definition.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_invalid_aiger_header.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff2.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_invalid_reset_literal.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch2.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_aiger_unsup_aiger_file.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff1.aiger
synth -top top
write_verilog synth.v
frontends/scripts/read_blif_duplicate_defenition.ys 0 → 100755
read_verilog ../top.v
synth -top top
write_blif blif1.blif
read_blif blif1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_blif_syntax_error.ys 0 → 100755
read_blif ../blif_e1.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
frontends/scripts/read_ilang_parse_error.ys 0 → 100644
read_ilang ../ilang.ilang
dump -n -o file1.il
write_verilog synth.v
frontends/scripts/read_json_invalid_direction.ys 0 → 100644
read_json ../json4.json
write_verilog synth.v
frontends/scripts/read_json_no_bits.ys 0 → 100644
read_json ../json3.json
write_verilog synth.v
frontends/scripts/read_json_no_direction.ys 0 → 100644
read_json ../json2.json
write_verilog synth.v
frontends/scripts/read_json_nonarray_bits_attr.ys 0 → 100644
read_json ../json7.json
write_verilog synth.v
frontends/scripts/read_json_nonstring_key.ys 0 → 100644
read_json ../json8.json
write_verilog synth.v
frontends/scripts/read_json_unexpected_char.ys 0 → 100644
read_json ../json1.json
write_verilog synth.v
frontends/scripts/read_json_unexpected_eof.ys 0 → 100644
read_json ../json5.json
write_verilog synth.v
frontends/scripts/read_liberty_bus_interface_only_in_lib_mode.ys 0 → 100644
read_liberty ../liblat1.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_cant_open_input_file.ys 0 → 100644
read_liberty ../libbbb.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_cant_resolve_wire_name.ys 0 → 100644
read_liberty ../lib2.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_ff_has_no_next_stage_attr.ys 0 → 100644
read_liberty ../libff.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_invalid_bus_type.ys 0 → 100644
read_liberty -lib ../liblat2.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_latch_has_no_data_in.ys 0 → 100644
read_liberty ../liblat.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_miss_func_on_output.ys 0 → 100644
read_liberty ../lib4.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_missing_direction.ys 0 → 100644
read_liberty ../lib1.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_parse_error_in_function.ys 0 → 100644
read_liberty ../lib3.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_redefenition_of_module.ys 0 → 100644
read_liberty ../lib.lib
read_liberty ../lib.lib
synth -top top
write_verilog synth.v
frontends/scripts/read_liberty_unsupp_type_for_bus.ys 0 → 100644
read_liberty -lib ../liblat1.lib
synth -top top
write_verilog synth.v
frontends/scripts/verilog_defaults_extra_arg.ys 0 → 100644
verilog_defaults -push -pop
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defaults_missing_arg.ys 0 → 100644
verilog_defaults
read_verilog
proc
write_verilog synth.v
frontends/scripts/verilog_defines_extra_arg.ys 0 → 100644
verilog_defines -aa
read_verilog
proc
write_verilog synth.v
frontends/verilog_defaults_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defaults_error/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_defaults_error/top1.v 0 → 100644
module top1 (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
endmodule
frontends/verilog_defines_error/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_defines_error/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
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