Commit 39190375 by SergeyDegtyar

'regression' tests update. Not grepping strings where it is possible.

parent 074b684f
read_verilog ../top.v
select n:\\SUM/N10
tee -o result.log select -list
select -assert-any n:\\SUM/N10
read_verilog ../top.v
synth_greenpak4 -part SLG46621V
select GP_INV
tee -o result.log select -list
select -assert-count 1 t:GP_INV
......@@ -19,6 +19,5 @@ abc -liberty ../osu018_stdcells_edit.lib
clean
select DFFSR
tee -o result.log select -list
select -assert-count 0 t:DFFSR
......@@ -20,5 +20,5 @@ design -copy-from netlist_v2 -as netlist_new netlist_v2
equiv_make -inames netlist_old netlist_new miter_netlist
equiv_simple -undef -seq 10
equiv_induct -undef -seq 10
tee -o result.log equiv_status
tee -o result.log equiv_status -assert
......@@ -4,4 +4,4 @@ read_verilog ../top.v;
rename -top gate; design -stash gate;
design -copy-from gold -as gold gold;
design -copy-from gate -as gate gate;
tee -o result.log equiv_make gold gate equiv
equiv_make gold gate equiv
tee -o result.log read_liberty ../lib.lib
write_verilog synth.v
read_liberty ../lib.lib
tee -o result.log read_verilog ../top.v
read_verilog ../top.v
prep
write_verilog synth.v
select -assert-count 4 t:$dff
read_verilog ../top.v
tee -o result.log synth -top top
write_verilog synth.v
synth -top top
select -assert-count 1 t:$_DFF_P_
select -assert-none t:$_DFF_P_ %% t:* %D
......@@ -6,4 +6,5 @@ fsm
opt
memory
opt
tee -o result.log synth_xilinx -top tc
synth_xilinx -top tc
select -assert-count 12 t:FDRE
read_verilog ../top.v
synth_xilinx -flatten
tee -o result.log stat
select -assert-count 1 t:RAMB36E1
tee -a result.log read_verilog ../top.v
tee -a result.log synth_xilinx
tee -a result.log flatten
tee -a result.log dump top
read_verilog ../top.v
synth_xilinx
flatten
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:FDRE_1
read_verilog ../top.v
tee -a result.log synth_xilinx
synth_xilinx
select -assert-count 4 t:FDRE
......@@ -4,4 +4,4 @@ memory_dff -nordff
memory_collect
opt_reduce
clean
tee -a result.log write_firrtl firrtl.firrtl
write_firrtl firrtl.firrtl
read_verilog ../top.v
tee -a result.log prep
prep
select -assert-none t:$dlatch
read_verilog ../top.v
prep -top picorv32 -nordff
opt -fast
tee -a result.log write_smt2 picorv32.smt2
write_smt2 picorv32.smt2
......@@ -3,4 +3,4 @@ proc
memory_dff -nordff
opt_reduce
clean
tee -a result.log write_firrtl firrtl.firrtl
write_firrtl firrtl.firrtl
read_verilog ../*.v
tee -a result.log synth_ice40 -top SuperTopEntity -json TopEntity.json
synth_ice40 -top SuperTopEntity -json TopEntity.json
read_verilog -sv ../top.v
proc
wreduce -keepdc
tee -a result.log dump
select -assert-count 1 t:$mux
read_verilog ../top.v
tee -a result.log synth_xilinx
synth_xilinx
select -assert-none t:RAM64X1D
read_verilog ../top.v
tee -a result.log synth_xilinx -nodram
synth_xilinx -nodram
select -assert-none t:FDRE
read -formal ../top.v
hierarchy -top top
synth
write_verilog -noattr result.log
select -assert-count 1 t:$_NOR_
select -assert-none t:$_NOR_ %% t:* %D
......@@ -4,5 +4,5 @@ dff2dffe
simplemap
opt
opt_rmdff
stat
tee -o result.log dump
select -assert-count 1 t:$_DFF_N_
select -assert-none t:$_DFF_N_ %% t:* %D
......@@ -3,4 +3,6 @@ proc
opt
techmap
muxcover -nopartial
tee -o result.log stat
stat
select -assert-count 1 t:$_MUX4_
select -assert-none t:$_MUX4_ %% t:* %D
......@@ -5,4 +5,4 @@ select -set buf w:w1 %coe1 w:w1 %d
# set the keep attribute for the $_BUF_ from w1 to w2
setattr -set keep 1 @buf
opt_clean
tee -o result.log stat
select -assert-count 1 t:$_BUF_
read_verilog ../top.v
proc; opt; wreduce; simplemap; muxcover -mux4=150
tee -o result.log stat
select -assert-count 1 t:$_MUX4_
read_verilog ../top.v
proc; pmux2shiftx -norange; opt -full
tee -o result.log stat
select -assert-count 1 t:$pmux
select -assert-count 3 t:$eq
read_verilog -sv ../top.sv
hierarchy -check -top TopModule
proc
tee -o result.log flatten
flatten
read_verilog -sv ../top.v
proc
select -assert-count 0 t:$dlatch
tee -o result.log dump
read_verilog ../top.v
hierarchy -top top
proc
tee -o result.log flatten
flatten
read_verilog ../top.v
tee -o result.log synth_xilinx
synth_xilinx
tee -o result.log read -formal ../top.v
read -formal ../top.v
read_verilog ../top.v
synth -top top
muxcover -mux8
tee -o result.log stat
select -assert-count 9 t:$_MUX8_
......@@ -10,5 +10,3 @@ cd dff # Constrain all select calls below inside the top module
select -assert-count 4 t:$adff
select -assert-count 1 t:$mux
select -assert-none t:$adff t:$mux %% t:* %D
tee -o result.log stat
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