'regression' tests update. Not grepping strings where it is possible.

regression/run.sh

@@ -21,6 +21,7 @@ if [ "$1" = "issue_00089" ] ||\
    [ "$1" = "issue_00594" ] ||\
    [ "$1" = "issue_00603" ] ||\
    [ "$1" = "issue_00635" ] ||\
+   [ "$1" = "issue_00639" ] ||\
    [ "$1" = "issue_00763" ] ||\
    [ "$1" = "issue_00814" ] ||\
    [ "$1" = "issue_01063" ] ||\
@@ -38,6 +39,8 @@ if [ "$1" = "issue_00089" ] ||\
 		expected_string="Failed to detect width for identifier"
 	elif [ "$1" = "issue_00594" ]; then
 		expected_string="Single range expected"
+	elif [ "$1" = "issue_00639" ]; then
+		expected_string="ERROR: Found 3 unproven \$equiv cells in 'equiv_status -assert'."
 	elif [ "$1" = "issue_00763" ]; then
 		expected_string="Invalid nesting"
 	elif [ "$1" = "issue_00814" ]; then
@@ -61,33 +64,9 @@ if [ "$1" = "issue_00089" ] ||\
 	fi
 
 # cases without any additional checks (only checks in .ys script)
-elif [ "$1" = "issue_01364" ] ||\
-	 [ "$1" = "issue_01372" ] ||\
-	 [ "$1" = "issue_00623" ] ||\
-	 [ "$1" = "issue_00656" ] ||\
-	 [ "$1" = "issue_01014" ] ||\
-	 [ "$1" = "issue_01193" ] ||\
-	 [ "$1" = "issue_01206" ] ||\
-	 [ "$1" = "issue_01216" ] ||\
-	 [ "$1" = "issue_01225" ] ||\
-	 [ "$1" = "issue_01259" ] ||\
-	 [ "$1" = "issue_01360" ]; then
-
-	yosys -ql yosys.log ../../scripts/$2.ys;
-
-	if [ $? != 0 ] ; then
-    	echo FAIL > ${1}_${2}.status
-    	touch .stamp
-    	exit 0
-	else
-		echo PASS > ${1}_${2}.status
-	fi
-
-# cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
 elif [ "$1" = "issue_00502" ] ||\
      [ "$1" = "issue_00524" ] ||\
      [ "$1" = "issue_00527" ] ||\
-     [ "$1" = "issue_00639" ] ||\
      [ "$1" = "issue_00642" ] ||\
      [ "$1" = "issue_00644" ] ||\
      [ "$1" = "issue_00655" ] ||\
@@ -96,7 +75,6 @@ elif [ "$1" = "issue_00502" ] ||\
 	 [ "$1" = "issue_00689" ] ||\
 	 [ "$1" = "issue_00699" ] ||\
 	 [ "$1" = "issue_00708" ] ||\
-	 [ "$1" = "issue_00737" ] ||\
 	 [ "$1" = "issue_00774" ] ||\
 	 [ "$1" = "issue_00781" ] ||\
 	 [ "$1" = "issue_00785" ] ||\
@@ -118,30 +96,16 @@ elif [ "$1" = "issue_00502" ] ||\
 	 [ "$1" = "issue_00938" ] ||\
 	 [ "$1" = "issue_00940" ] ||\
 	 [ "$1" = "issue_00948" ] ||\
-	 [ "$1" = "issue_00954" ] ||\
-	 [ "$1" = "issue_00955" ] ||\
-	 [ "$1" = "issue_00956" ] ||\
 	 [ "$1" = "issue_00961" ] ||\
-	 [ "$1" = "issue_00968" ] ||\
 	 [ "$1" = "issue_00981" ] ||\
-	 [ "$1" = "issue_00982" ] ||\
 	 [ "$1" = "issue_00987" ] ||\
 	 [ "$1" = "issue_00993" ] ||\
-	 [ "$1" = "issue_00997" ] ||\
-	 [ "$1" = "issue_01002" ] ||\
 	 [ "$1" = "issue_01016" ] ||\
-	 [ "$1" = "issue_01022" ] ||\
-	 [ "$1" = "issue_01023" ] ||\
 	 [ "$1" = "issue_01033" ] ||\
 	 [ "$1" = "issue_01034" ] ||\
-	 [ "$1" = "issue_01040" ] ||\
 	 [ "$1" = "issue_01047" ] ||\
-	 [ "$1" = "issue_01065" ] ||\
 	 [ "$1" = "issue_01070" ] ||\
-	 [ "$1" = "issue_01084" ] ||\
 	 [ "$1" = "issue_01091" ] ||\
-	 [ "$1" = "issue_01115" ] ||\
-	 [ "$1" = "issue_01118" ] ||\
 	 [ "$1" = "issue_01128" ] ||\
 	 [ "$1" = "issue_01132" ] ||\
 	 [ "$1" = "issue_01135" ] ||\
@@ -149,9 +113,47 @@ elif [ "$1" = "issue_00502" ] ||\
 	 [ "$1" = "issue_01220" ] ||\
 	 [ "$1" = "issue_01223" ] ||\
 	 [ "$1" = "issue_01231" ] ||\
-	 [ "$1" = "issue_01243" ] ||\
 	 [ "$1" = "issue_01273" ] ||\
 	 [ "$1" = "issue_01329" ] ||\
+     [ "$1" = "issue_01364" ] ||\
+	 [ "$1" = "issue_01372" ] ||\
+	 [ "$1" = "issue_00623" ] ||\
+	 [ "$1" = "issue_00656" ] ||\
+	 [ "$1" = "issue_01014" ] ||\
+	 [ "$1" = "issue_01023" ] ||\
+	 [ "$1" = "issue_01084" ] ||\
+	 [ "$1" = "issue_01193" ] ||\
+	 [ "$1" = "issue_01206" ] ||\
+	 [ "$1" = "issue_01216" ] ||\
+	 [ "$1" = "issue_01225" ] ||\
+	 [ "$1" = "issue_01259" ] ||\
+	 [ "$1" = "issue_01360" ]; then
+
+	yosys -ql yosys.log ../../scripts/$2.ys;
+
+	if [ $? != 0 ] ; then
+    	echo FAIL > ${1}_${2}.status
+    	touch .stamp
+    	exit 0
+	else
+		echo PASS > ${1}_${2}.status
+	fi
+
+# cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
+elif [ "$1" = "issue_00737" ] ||\
+	 [ "$1" = "issue_00954" ] ||\
+	 [ "$1" = "issue_00955" ] ||\
+	 [ "$1" = "issue_00956" ] ||\
+	 [ "$1" = "issue_00968" ] ||\
+	 [ "$1" = "issue_00982" ] ||\
+	 [ "$1" = "issue_00997" ] ||\
+	 [ "$1" = "issue_01002" ] ||\
+	 [ "$1" = "issue_01022" ] ||\
+	 [ "$1" = "issue_01040" ] ||\
+	 [ "$1" = "issue_01065" ] ||\
+	 [ "$1" = "issue_01115" ] ||\
+	 [ "$1" = "issue_01118" ] ||\
+	 [ "$1" = "issue_01243" ] ||\
 	 [ "$1" = "issue_00329" ] ||\
 	 [ "$1" = "issue_01126" ] ||\
 	 [ "$1" = "issue_01161" ] ||\
@@ -160,70 +162,8 @@ elif [ "$1" = "issue_00502" ] ||\
 
 	expected_string=""
 	expected="1"
-	if [ "$1" = "issue_00502" ]; then
-		expected_string="\\SUM/N10"
-	elif [ "$1" = "issue_00524" ]; then
-		expected_string="GP_INV"
-	elif [ "$1" = "issue_00527" ]; then
-		expected_string="DFFSR"
-		expected="0"
-	elif [ "$1" = "issue_00639" ]; then
-		expected_string="Found a total"
-	elif [ "$1" = "issue_00642" ] ||\
-		 [ "$1" = "issue_00644" ] ||\
-		 [ "$1" = "issue_00689" ] ||\
-		 [ "$1" = "issue_00699" ] ||\
-		 [ "$1" = "issue_00708" ] ||\
-		 [ "$1" = "issue_00826" ] ||\
-		 [ "$1" = "issue_00862" ] ||\
-		 [ "$1" = "issue_00870" ] ||\
-		 [ "$1" = "issue_00948" ] ||\
-		 [ "$1" = "issue_00987" ]; then
-		expected_string="Successfully finished Verilog frontend"
-	elif [ "$1" = "issue_00655" ]; then
-		expected_string="Executing EDIF backend"
-	elif [ "$1" = "issue_00675" ]; then
-		expected_string="Presumably equivalent wires"
-	elif [ "$1" = "issue_00685" ]; then
-		expected_string="Imported 0 cell"
-	elif [ "$1" = "issue_00737" ]; then
-		expected_string="A:"
-	elif [ "$1" = "issue_00774" ] ||\
-		 [ "$1" = "issue_00781" ] ||\
-		 [ "$1" = "issue_00785" ]; then
-		expected_string="Executing BLIF backend"
-	elif [ "$1" = "issue_00810" ]; then
-		expected_string="Executing ILANG backend"
-	elif [ "$1" = "issue_00823" ]; then
-		expected_string="Executing Verilog backend"
-	elif [ "$1" = "issue_00831" ]; then
-		expected_string="Executing SMT2 backend"
-	elif [ "$1" = "issue_00835" ]; then
-		expected_string="Replacing memory"
-	elif [ "$1" = "issue_00857" ]; then
-		expected_string="_DFF_P_                        1"
-	elif [ "$1" = "issue_00865" ]; then
-		expected_string="FDRE                           12"
-	elif [ "$1" = "issue_00867" ]; then
-		expected_string="RAMB36E1                        1"
-	elif [ "$1" = "issue_00873" ]; then
-		expected_string="has an unprocessed 'init' attribute."
-	elif [ "$1" = "issue_00888" ]; then
-		expected_string="FDRE                            4"
-	elif [ "$1" = "issue_00922" ]; then
-		expected_string="ERROR: Unclocked write port 0 on memory top.ram."
-		expected="0"
-	elif [ "$1" = "issue_00931" ]; then
-		expected_string="Number of cells:                  5"
-	elif [ "$1" = "issue_00935" ]; then
-		expected_string="Found logic loop in module"
-		expected="0"
-	elif [ "$1" = "issue_00938" ]; then
-		expected_string="terminate called after throwing"
-		expected="0"
-	elif [ "$1" = "issue_00940" ]; then
-		expected_string="failed: return code 134"
-		expected="0"
+	if [ "$1" = "issue_00737" ]; then
+		expected_string="ATTR \\\A:"
 	elif [ "$1" = "issue_00954" ]; then
 		expected_string="out = 4'1000"
 	elif [ "$1" = "issue_00955" ]; then
@@ -231,73 +171,32 @@ elif [ "$1" = "issue_00502" ] ||\
 	elif [ "$1" = "issue_00956" ]; then
 		expected_string="Wire inivalue.r_val has an unprocessed 'init' attribute"
 		expected="0"
-	elif [ "$1" = "issue_00961" ]; then
-		expected_string="Executing PROC_DFF pass"
 	elif [ "$1" = "issue_00968" ]; then
 		expected_string="assign o_value = { 4'hx, i_value }"
-	elif [ "$1" = "issue_00981" ]; then
-		expected_string="Executing CHECK pass"
 	elif [ "$1" = "issue_00982" ]; then
 		expected_string="INIT 1'0"
-	elif [ "$1" = "issue_00993" ]; then
-		expected_string="_DFF_P_                        1"
 	elif [ "$1" = "issue_00997" ]; then
 		expected_string="h0"
 	elif [ "$1" = "issue_01002" ]; then
 		expected_string="Estimated number of LCs:         87"
-	elif [ "$1" = "issue_01016" ]; then
-		expected_string="cell \$mux \$ternary\$../top.v:5"
 	elif [ "$1" = "issue_01022" ]; then
 		expected_string="connect \\\b 32'11111111111111111111111111111111"
-	elif [ "$1" = "issue_01023" ]; then
-		expected_string="Continuing TECHMAP pass"
-	elif [ "$1" = "issue_01033" ]; then
-		expected_string="RAM64X1D         "
-		expected="0"
-	elif [ "$1" = "issue_01034" ]; then
-		expected_string="FDRE         "
-		expected="0"
 	elif [ "$1" = "issue_01040" ]; then
 		expected_string=".subckt dut_sub a\[2\]=a\[2\] a\[3\]=a\[3\] a\[4\]=a\[4\] a\[5\]=a\[5\] a\[6\]=a\[6\]"
-	elif [ "$1" = "issue_01047" ]; then
-		expected_string="assign y = ~(w\[0\] | w\[1\]);"
 	elif [ "$1" = "issue_01065" ]; then
 		expected_string="Driver-driver conflict for"
 		expected="0"
-	elif [ "$1" = "issue_01070" ]; then
-		expected_string="cell \$_DFF_N_"
-	elif [ "$1" = "issue_01084" ]; then
-		expected_string="Successfully finished Verilog frontend"
-	elif [ "$1" = "issue_01091" ]; then
-		expected_string="\$_MUX4_                         1"
 	elif [ "$1" = "issue_01115" ]; then
 		expected_string="connect \\\o 33'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
 	elif [ "$1" = "issue_01118" ]; then
 		expected_string="connect \\\o \[0\] 1'0"
-	elif [ "$1" = "issue_01128" ]; then
-		expected_string="\$_BUF_                          1"
-	elif [ "$1" = "issue_01132" ]; then
-		expected_string="\$_MUX4_                         1"
-	elif [ "$1" = "issue_01135" ]; then
-		expected_string="\$pmux                           1"
-	elif [ "$1" = "issue_01145" ] ||\
-		 [ "$1" = "issue_01220" ]; then
-		expected_string="Executing FLATTEN pass (flatten design)."
-	elif [ "$1" = "issue_01223" ]; then
-		expected_string=" Executing CHECK pass (checking for obvious problems)."
-	elif [ "$1" = "issue_01231" ]; then
-		expected_string="Successfully finished Verilog frontend."
+	elif [ "$1" = "issue_01126" ]; then
+		expected_string="assign d = c\\[5:0\\]"
 	elif [ "$1" = "issue_01243" ]; then
 		expected_string="assign y = reg_assign;"
-	elif [ "$1" = "issue_01273" ]; then
-		expected_string="\$_MUX8_                         9"
-	elif [ "$1" = "issue_01329" ]; then
-		expected_string="\$mux                            1"
 	elif [ "$1" = "issue_00329" ]; then
 		expected_string="wire \\[-1"
 		expected="0"
-	elif [ "$1" = "issue_01126" ]; then
-		expected_string="assign d = c\\[5:0\\]"
 	elif [ "$1" = "issue_01161" ]; then
 		expected_string="assign z0 = b"
 	elif [ "$1" = "issue_01217" ]; then

regression/scripts/issue_00502.ys

 read_verilog ../top.v
-select n:\\SUM/N10
-tee -o result.log select -list
+select -assert-any n:\\SUM/N10
 

regression/scripts/issue_00524.ys

 read_verilog ../top.v
 synth_greenpak4 -part SLG46621V
-select GP_INV
-tee -o result.log select -list
-
+select -assert-count 1 t:GP_INV

regression/scripts/issue_00527.ys

@@ -19,6 +19,5 @@ abc -liberty ../osu018_stdcells_edit.lib
 
 clean
 
-select DFFSR
-tee -o result.log select -list
+select -assert-count 0 t:DFFSR
 

regression/scripts/issue_00639.ys

@@ -20,5 +20,5 @@ design -copy-from netlist_v2 -as netlist_new netlist_v2
 equiv_make -inames netlist_old netlist_new miter_netlist
 equiv_simple -undef -seq 10
 equiv_induct -undef -seq 10
-tee -o result.log equiv_status
+tee -o result.log equiv_status -assert
 

regression/scripts/issue_00675.ys

@@ -4,4 +4,4 @@ read_verilog ../top.v;
 rename -top gate; design -stash gate;
 design -copy-from gold -as gold gold;
 design -copy-from gate -as gate gate;
-tee -o result.log equiv_make gold gate equiv
+equiv_make gold gate equiv

regression/scripts/issue_00685.ys

-tee -o result.log read_liberty ../lib.lib
-write_verilog synth.v
+read_liberty ../lib.lib

regression/scripts/issue_00835.ys

-tee -o result.log read_verilog ../top.v
+read_verilog ../top.v
 prep
-write_verilog synth.v
+select -assert-count 4 t:$dff
 

regression/scripts/issue_00857.ys

 read_verilog ../top.v
-tee -o result.log synth -top top
-write_verilog synth.v
+synth -top top
+select -assert-count 1 t:$_DFF_P_
+select -assert-none t:$_DFF_P_ %% t:* %D
 

regression/scripts/issue_00865.ys

@@ -6,4 +6,5 @@ fsm
 opt
 memory
 opt
-tee -o result.log synth_xilinx -top tc
+synth_xilinx -top tc
+select -assert-count 12 t:FDRE

regression/scripts/issue_00867.ys

 read_verilog ../top.v
 synth_xilinx -flatten
-tee -o result.log stat
+select -assert-count 1 t:RAMB36E1

regression/scripts/issue_00873.ys

-tee -a result.log read_verilog ../top.v
-tee -a result.log synth_xilinx
-tee -a result.log flatten
-tee -a result.log dump top
-
+read_verilog ../top.v
+synth_xilinx
+flatten
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
+select -assert-count 1 t:FDRE_1

regression/scripts/issue_00888.ys

 read_verilog ../top.v
-tee -a result.log synth_xilinx
-
+synth_xilinx
+select -assert-count 4 t:FDRE

regression/scripts/issue_00922.ys

@@ -4,4 +4,4 @@ memory_dff -nordff
 memory_collect
 opt_reduce
 clean
-tee -a result.log write_firrtl firrtl.firrtl
+write_firrtl firrtl.firrtl

regression/scripts/issue_00931.ys

 read_verilog ../top.v
-tee -a result.log prep
+prep
+select -assert-none t:$dlatch

regression/scripts/issue_00935.ys

 read_verilog ../top.v
 prep -top picorv32 -nordff
 opt -fast
-tee -a result.log write_smt2 picorv32.smt2
+write_smt2 picorv32.smt2

regression/scripts/issue_00938.ys

@@ -3,4 +3,4 @@ proc
 memory_dff -nordff
 opt_reduce
 clean
-tee -a result.log write_firrtl firrtl.firrtl
+write_firrtl firrtl.firrtl

regression/scripts/issue_00940.ys

 read_verilog ../*.v
-tee -a result.log synth_ice40 -top SuperTopEntity -json TopEntity.json
+synth_ice40 -top SuperTopEntity -json TopEntity.json

regression/scripts/issue_01016.ys

 read_verilog -sv ../top.v
 proc
 wreduce -keepdc
-tee -a result.log dump
+select -assert-count 1 t:$mux
 

regression/scripts/issue_01033.ys

 read_verilog ../top.v
-tee -a result.log synth_xilinx
+synth_xilinx
+select -assert-none t:RAM64X1D
 

regression/scripts/issue_01034.ys

 read_verilog ../top.v
-tee -a result.log synth_xilinx -nodram
+synth_xilinx -nodram
+select -assert-none t:FDRE
 

regression/scripts/issue_01047.ys

 read -formal ../top.v
 hierarchy -top top
 synth
-write_verilog -noattr result.log
+select -assert-count 1 t:$_NOR_
+select -assert-none t:$_NOR_ %% t:* %D

regression/scripts/issue_01070.ys

@@ -4,5 +4,5 @@ dff2dffe
 simplemap
 opt
 opt_rmdff
-stat
-tee -o result.log dump
+select -assert-count 1 t:$_DFF_N_
+select -assert-none t:$_DFF_N_ %% t:* %D

regression/scripts/issue_01091.ys

@@ -3,4 +3,6 @@ proc
 opt
 techmap
 muxcover -nopartial
-tee -o result.log stat
+stat
+select -assert-count 1 t:$_MUX4_
+select -assert-none t:$_MUX4_ %% t:* %D

regression/scripts/issue_01128.ys

@@ -5,4 +5,4 @@ select -set buf w:w1 %coe1 w:w1 %d
 # set the keep attribute for the $_BUF_ from w1 to w2
 setattr -set keep 1 @buf
 opt_clean
-tee -o result.log stat
+select -assert-count 1 t:$_BUF_

regression/scripts/issue_01132.ys

 read_verilog ../top.v
 proc; opt; wreduce; simplemap; muxcover -mux4=150
-tee -o result.log stat
+select -assert-count 1 t:$_MUX4_

regression/scripts/issue_01135.ys

 read_verilog ../top.v
 proc; pmux2shiftx -norange; opt -full
-tee -o result.log stat
+select -assert-count 1 t:$pmux
+select -assert-count 3 t:$eq

regression/scripts/issue_01145.ys

 read_verilog -sv ../top.sv
 hierarchy -check -top TopModule
 proc
-tee -o result.log flatten
+flatten

regression/scripts/issue_01193.ys

 read_verilog -sv ../top.v
 proc
 select -assert-count 0 t:$dlatch
+tee -o result.log dump

regression/scripts/issue_01220.ys

 read_verilog ../top.v
 hierarchy -top top
 proc
-tee -o result.log flatten
+flatten

regression/scripts/issue_01223.ys

 read_verilog ../top.v
-tee -o result.log synth_xilinx
+synth_xilinx

regression/scripts/issue_01231.ys

-tee -o result.log read -formal ../top.v
+read -formal ../top.v

regression/scripts/issue_01273.ys

 read_verilog ../top.v
 synth -top top
 muxcover -mux8
-tee -o result.log stat
+select -assert-count 9 t:$_MUX8_

regression/scripts/issue_01329.ys

@@ -10,5 +10,3 @@ cd dff # Constrain all select calls below inside the top module
 select -assert-count 4 t:$adff
 select -assert-count 1 t:$mux
 select -assert-none t:$adff t:$mux %% t:* %D
-
-tee -o result.log stat