Unverified Commit 32db6edd by Miodrag Milanović Committed by GitHub

Merge pull request #9 from SergeyDegtyar/master

Add new tests to 'simple' and 'misc' test groups
parents 7d7c08ec 50fc2cde
......@@ -48,7 +48,7 @@ $(eval $(call template,scc, scc scc_all_cell_types scc_expect scc_max_depth scc_
$(eval $(call template,scatter, scatter ))
#rename
$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat))
$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire))
#qwp
#qwp_v - exception
......@@ -72,4 +72,72 @@ $(eval $(call template,cover, cover cover_q cover_o cover_dir cover_a ))
#insbuf ERROR: Found error in internal cell
#$(eval $(call template,insbuf,insbuf insbuf_cell))
#add
$(eval $(call template,add, add add_wire add_input add_output add_inout add_global_input ))
#blackbox
$(eval $(call template,blackbox, blackbox ))
#bugpoint ERROR: No such command: autoidx (type 'help' for a command overview)
#$(eval $(call template,bugpoint, bugpoint bugpoint_yosys bugpoint_script bugpoint_grep bugpoint_fast bugpoint_clean bugpoint_modules bugpoint_ports bugpoint_cells bugpoint_connections ))
#chformal
$(eval $(call template,chformal, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
$(eval $(call template,chformal_dff, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
#chtype
$(eval $(call template,chtype, chtype chtype_map chtype_selection chtype_set))
#connect
#connect_nomap_port connect_port - ERROR: Can't find cell $2.
$(eval $(call template,connect, connect_nomap_set connect_nomap_unset connect_nounset_set connect_set connect_unset))
#connwrappers
$(eval $(call template,connwrappers, connwrappers connwrappers_signed connwrappers_unsigned connwrappers_port ))
#plugin
$(eval $(call template,plugin, plugin plugin_i plugin_a plugin_l ))
#select
$(eval $(call template,select, select select_all select_add select_add_all select_assert_any select_assert_count select_assert_max select_assert_min select_assert_none select_clear select_count select_del select_list select_module select_none select_read select_set select_write select_add_A_eq select_add_a_eq select_add_A_lesseq select_add_a_lesseq select_add_A_less select_add_a_less select_add_A_moreeq select_add_a_moreeq select_add_A_more select_add_a_more select_add_A select_add_a select_add_c select_add_i select_add_mid select_add_m select_add_n select_add_obj select_add_o select_add_p select_add_r_eq select_add_r_lesseq select_add_r_less select_add_r_moreeq select_add_r_more select_add_r select_add_ss select_add_s select_add_t select_add_w select_add_x ))
$(eval $(call template,select_mem, select select_all select_add select_add_all select_assert_any select_assert_count_mem select_assert_max_mem select_assert_min select_assert_none select_clear select_count select_del select_list select_module_mem select_none select_read select_set select_write select_add_A_eq select_add_a_eq select_add_A_lesseq select_add_a_lesseq select_add_A_less select_add_a_less select_add_A_moreeq select_add_a_moreeq select_add_A_more select_add_a_more select_add_A select_add_a select_add_c select_add_i select_add_mid select_add_m select_add_n select_add_obj select_add_o select_add_p select_add_r_eq select_add_r_lesseq select_add_r_less select_add_r_moreeq select_add_r_more select_add_r select_add_ss select_add_s select_add_t select_add_w select_add_x ))
$(eval $(call template,select_ls, select_ls select_ls_top))
$(eval $(call template,select_cd, select_cd select_cd_up select_cd_module ))
$(eval $(call template,select_stack,select_%a select_%cie select_%ci select_%coe select_%co select_%C select_%c select_%i select_%M select_%m select_%n select_%R4 select_%R select_%s select_%u select_%x_%D select_%x_%d select_%xe select_%))
#setattr
$(eval $(call template,setattr, setattr setattr_mod setattr_set setattr_top setattr_unset setattr_set_proc ))
$(eval $(call template,setattr_mem, setattr setattr_mod setattr_set setattr_top setattr_unset setattr_set_proc ))
#setparam
#setparam_type
#ERROR: Found error in internal cell \top.$procdff$4 ($dff) at kernel/rtlil.cc:715:
$(eval $(call template,setparam, setparam setparam_set setparam_unset setparam_top ))
#chparam
$(eval $(call template,chparam, chparam chparam_set chparam_top chparam_list ))
#setundef
$(eval $(call template,setundef, setundef_one setundef_anyseq setundef_anyconst setundef_init setundef_random setundef_undef setundef_undriven setundef_expose))
#assertpmux
$(eval $(call template,assertpmux, assertpmux assertpmux_noinit assertpmux_always))
#eval
$(eval $(call template,eval, eval eval_set eval_set_undef eval_table eval_show eval_brute_force_equiv_checker eval_show_not_set eval_table_set eval_vloghammer_report eval_vloghammer_report_rtl))
#freduce
$(eval $(call template,freduce, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_dff, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_mem, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
#miter -assert
$(eval $(call template,miter_assert, miter_assert miter_assert_flatten ))
$(eval $(call template,miter_assert_assume, miter_assert miter_assert_flatten ))
#sat
$(eval $(call template,sat, sat_dump_cnf sat_dump_json sat_dump_vcd sat_initsteps sat_maxsteps sat_max sat_prove_x sat_set_all_undef_at sat_set_all_undef sat_set_any_undef_at sat_set_any_undef sat_set_def_at sat_set_def sat_set_init sat_set sat_show sat_stepsize sat_tempinduct_skip sat_unset_at ))
#sim
$(eval $(call template,sim,sim sim_a sim_clock sim_d sim_n sim_rstlen sim_vcd sim_w sim_zinit ))
$(eval $(call template,sim_mem,sim sim_a sim_clockn sim_clock_mem sim_d sim_n sim_resetn sim_reset sim_rstlen sim_vcd sim_w sim_zinit_mem ))
.PHONY: all clean
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top(C, S, Y);
input C;
input [1:0] S;
output reg [3:0] Y;
initial Y = 0;
always @(posedge C) begin
case (S)
2'b00: Y <= 4'b0001;
2'b01: Y <= 4'b0010;
2'b10: Y <= 4'b0100;
2'b11: Y <= 4'b1000;
endcase
end
endmodule
module bb
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top
(
input x,
input y,
input cin,
output A,
output cout
);
bb u_bb (x,y,cin,A,cout);
endmodule
module bb
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top
(
input x,
input y,
input cin,
output A,
output cout
);
bb u_bb (x,y,cin,A,cout);
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
parameter X = 1;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (.x(x),.o(o),.y(1'b0));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
read_verilog ../top.v
tee -o result.log add -wire w 0
read_verilog ../top.v
tee -o result.log add -global_input gi 32000
read_verilog ../top.v
tee -o result.log add -inout \34 3
read_verilog ../top.v
add -input i 2
tee -o result.log add -input i 2
read_verilog ../top.v
tee -o result.log add -output o 3
read_verilog ../top.v
tee -o result.log add -wire w 1
read_verilog ../top.v
proc
tee -o result.log assertpmux
read_verilog ../top.v
proc
tee -o result.log assertpmux -always
read_verilog ../top.v
proc
tee -o result.log assertpmux -noinit
read_verilog ../top.v
tee -o result.log blackbox bb
read_verilog ../top.v
tee -o result.log bugpoint
read_verilog ../top.v
tee -o result.log bugpoint -cells
read_verilog ../top.v
tee -o result.log bugpoint -clean
read_verilog ../top.v
tee -o result.log bugpoint -connections
read_verilog ../top.v
tee -o result.log bugpoint -fast
read_verilog ../top.v
tee -o result.log bugpoint -grep "Yosys"
read_verilog ../top.v
tee -o result.log bugpoint -modules
read_verilog ../top.v
tee -o result.log bugpoint -ports
read_verilog ../top.v
tee -o result.log bugpoint -script script.ys
read_verilog ../top.v
tee -o result.log bugpoint -yosys yosys.ys
read_verilog -sv ../top.v
tee -o result.log chformal -remove
read_verilog -sv ../top.v
tee -o result.log chformal -assert -remove
read_verilog -sv ../top.v
tee -o result.log chformal -assert2assume
read_verilog -sv ../top.v
tee -o result.log chformal -assume -remove
read_verilog -sv ../top.v
tee -o result.log chformal -assume2assert
read_verilog -sv ../top.v
tee -o result.log chformal -cover -remove
read_verilog -sv ../top.v
tee -o result.log chformal -delay 2
read_verilog -sv ../top.v
tee -o result.log chformal -early
read_verilog -sv ../top.v
tee -o result.log chformal -fair -remove
read_verilog -sv ../top.v
tee -o result.log chformal -fair2live
read_verilog -sv ../top.v
tee -o result.log chformal -fair2live -assert2assume
read_verilog -sv ../top.v
tee -o result.log chformal -live -remove
read_verilog -sv ../top.v
tee -o result.log chformal -live2fair
read_verilog -sv ../top.v
proc
tee -o result.log chformal -early
read_verilog -sv ../top.v
tee -o result.log chformal -skip 2
read_verilog ../top.v
proc
tee -o result.log chparam
read_verilog ../top.v
proc
tee -o result.log chparam -set X 2 top
tee -o result.log chparam -list
read_verilog ../top.v
proc
tee -o result.log chparam -set X 2 top
read_verilog ../top.v
proc
tee -o result.log chparam top
read_verilog -sv ../top.v
proc
tee -o result.log chtype
read_verilog -sv ../top.v
proc
tee -o result.log chtype -map $dff $adff $2
read_verilog -sv ../top.v
proc
tee -o result.log chtype $2
read_verilog -sv ../top.v
proc
tee -o result.log chtype -set $adff $2
read_verilog -sv ../top.v
proc
tee -o result.log connect -nomap -port $dff d q
read_verilog -sv ../top.v
proc
tee -o result.log connect -nomap -set d q
read_verilog -sv ../top.v
proc
tee -o result.log connect -nomap -unset d q
read_verilog -sv ../top.v
proc
tee -o result.log connect -nounset -set d q
read_verilog -sv ../top.v
proc
tee -o result.log connect -port $2 d q
read_verilog -sv ../top.v
proc
tee -o result.log connect -set d q
read_verilog -sv ../top.v
proc
tee -o result.log connect -unset d q
read_verilog ../top.v
proc
tee -o result.log connwrappers
read_verilog ../top.v
proc
tee -o result.log connwrappers -port $dff d 32000 1
read_verilog ../top.v
proc
tee -o result.log connwrappers -signed $dff d 3
read_verilog ../top.v
proc
tee -o result.log connwrappers -unsigned $dff d 0
read_verilog ../top.v
proc
tee -o result.log eval middle
read_verilog ../top.v
proc
tee -o result.log eval -brute_force_equiv_checker_x top top
read_verilog ../top.v
proc
tee -o result.log eval -set x 1 -set y 0 middle
read_verilog ../top.v
proc
tee -o result.log eval -set-undef middle
read_verilog ../top.v
proc
tee -o result.log eval -set x 1 -set y 0 -show o middle
read_verilog ../top.v
proc
tee -o result.log eval -show o middle
read_verilog ../top.v
proc
tee -o result.log eval -table o middle
read_verilog ../top.v
proc
tee -o result.log eval -set-undef -table o middle
read_verilog ../top.v
proc
tee -o result.log eval -vloghammer_report mid dle x 1
read_verilog ../top.v
proc
tee -o result.log eval -vloghammer_report u_ rtl y 1
read_verilog ../top.v
proc
tee -o result.log freduce
synth
tee -o result.log freduce
read_verilog ../top.v
proc
tee -o result.log freduce -dump fred
read_verilog ../top.v
proc
tee -o result.log freduce -inv
read_verilog ../top.v
proc
tee -o result.log freduce -stop 1
read_verilog ../top.v
proc
tee -o result.log freduce -v
read_verilog ../top.v
proc
tee -o result.log freduce -vv
read_verilog -sv ../top.v
proc
tee -o result.log miter -assert -make_outputs top
tee -o result.log miter -assert -make_outputs middle
read_verilog -sv ../top.v
proc
tee -o result.log miter -assert -flatten top
tee -o result.log miter -assert -flatten middle
tee -o result.log plugin
read_verilog ../top.v
tee -o result.log plugin -i /usr/local/share/yosys/plugins/vhdl.so -a alias
read_verilog ../top.v
tee -o result.log plugin -i /usr/local/share/yosys/plugins/vhdl.so
read_verilog ../top.v
tee -o result.log plugin -l
plugin -i /usr/local/share/yosys/plugins/vhdl.so -a alias
tee -o result.log plugin -l
read_verilog ../top.v
proc
tee -o result.log rename -enumerate
tee -o result.log rename -enumerate middle mid_module
read_verilog ../top.v
proc
tee -o result.log rename -src
tee -o result.log rename -src middle mid_module
read_verilog ../top.v
proc
tee -o result.log rename -wire middle mid_module
read_verilog ../top.v
proc
tee -o result.log sat -dump_cnf cnf.cnf middle
read_verilog ../top.v
proc
tee -o result.log sat -dump_json json.json middle
read_verilog ../top.v
proc
tee -o result.log sat -dump_vcd vcd.vcd middle
read_verilog ../top.v
proc
tee -o result.log sat -initsteps 3 middle
read_verilog ../top.v
proc
tee -o result.log sat -max 3 middle
read_verilog ../top.v
proc
tee -o result.log sat -maxsteps 0 middle
read_verilog ../top.v
proc
tee -o result.log sat -prove-x x 1 middle
read_verilog ../top.v
proc
tee -o result.log sat -set x 3 middle
read_verilog ../top.v
proc
tee -o result.log sat -set-all-undef x middle
read_verilog ../top.v
proc
tee -o result.log sat -set-all-undef-at 3 x middle
read_verilog ../top.v
proc
tee -o result.log sat -set-any-undef x middle
read_verilog ../top.v
proc
tee -o result.log sat -set-any-undef-at 3 x middle
read_verilog ../top.v
proc
tee -o result.log sat -set-def x middle
read_verilog ../top.v
proc
tee -o result.log sat -set-def-at 3 x middle
read_verilog ../top.v
proc
tee -o result.log sat -set-init x 0 middle
read_verilog ../top.v
proc
tee -o result.log sat -show x middle
read_verilog ../top.v
proc
tee -o result.log sat -stepsize 3 middle
read_verilog ../top.v
proc
tee -o result.log sat -tempinduct-skip 3 middle
read_verilog ../top.v
proc
tee -o result.log sat -unset-at 3 x middle
read_verilog ../top.v
proc
tee -o result.log select
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %%
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %c
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %R
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %R 4
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %a
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %ci:+[A] */t:$mux
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %cie:+[A] */t:$mux
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %co:+[Y] */t:$mux
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %i
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %M
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %n
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %s
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %coe:+[Y] */t:$mux %u
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %x:+[A] */t:$mux %D
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select */t:$mux %xe:+[A] */t:$mux
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add top
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add a:o>o
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add A:top
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add A:top=top
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add A:top<top
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add A:top<=top
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add A:top>=top
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add *
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add c:$2
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add i:x
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add m:*
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add top/u_mid
tee -o result.log select -list
read_verilog ../top.v
tee -o result.log select -add n:*
proc
tee -o result.log select -add n:*
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add o:A
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add top/o
tee -o result.log select -list
read_verilog ../top.v
tee -o result.log select -add p:$*
tee -o result.log select -list
read_verilog ../top.v
tee -o result.log select -add r:*
proc
tee -o result.log select -add r:*
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add r:*=*
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add r:add<add
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add r:add<=add
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add r:add>add
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add r:add>=add
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add s:1
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add s:1:6
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add t:$add
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add w:o
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add x:o
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select *
tee -o result.log select -list
read_verilog ../top.v
select -add top
tee -o result.log select -assert-any top
proc
select -add top
tee -o result.log select -assert-any top
tee -o result.log select -list
read_verilog ../top.v
select -add top
tee -o result.log select -assert-count 11 top
proc
tee -o result.log select -assert-count 11 top
tee -o result.log select -list
read_verilog ../top.v
select -add top
tee -o result.log select -assert-count 32 top
proc
tee -o result.log select -assert-count 62 top
tee -o result.log select -list
read_verilog ../top.v
select -add top
tee -o result.log select -assert-max 15 top
proc
select -add top
tee -o result.log select -assert-max 15 top
tee -o result.log select -list
read_verilog ../top.v
select -add top
tee -o result.log select -assert-max 32 top
proc
select -add top
tee -o result.log select -assert-max 62 top
tee -o result.log select -list
read_verilog ../top.v
select -add top
tee -o result.log select -assert-min 2 top
proc
select -add top
tee -o result.log select -assert-min 2 top
tee -o result.log select -list
read_verilog ../top.v
select -none
tee -o result.log select -assert-none x
proc
select -none
tee -o result.log select -assert-none x
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log cd
read_verilog ../top.v
proc
tee -o result.log cd middle
read_verilog ../top.v
proc
tee -o result.log cd middle
tee -o result.log cd ..
read_verilog ../top.v
proc
select -add top -add middle
tee -o result.log select -clear
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top -add middle
tee -o result.log select -count
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top
tee -o result.log select -del top
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top -add middle
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log select -add top
tee -o result.log ls
read_verilog ../top.v
proc
tee -o result.log ls top
read_verilog ../top.v
proc
select -add top -add middle
tee -o result.log select -module middle
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top -add top
tee -o result.log select -module top
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top -add middle
tee -o result.log select -none
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top -add middle
select -write select_f
tee -o result.log select -read select_f
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top
tee -o result.log select -set top top
tee -o result.log select @top
tee -o result.log select -list
read_verilog ../top.v
proc
select -add top -add middle
tee -o result.log select -write select_f
tee -o result.log select -list
read_verilog ../top.v
proc
tee -o result.log setattr
read_verilog ../top.v
proc
tee -o result.log setattr -mod -set u 1 top
read_verilog ../top.v
proc
tee -o result.log setattr -set u 1 top
read_verilog ../top.v
tee -o result.log setattr -set u 1 top
read_verilog ../top.v
proc
tee -o result.log setattr top
read_verilog ../top.v
proc
tee -o result.log setattr -set u 1 top
tee -o result.log setattr -unset u top
read_verilog ../top.v
proc
tee -o result.log setparam
read_verilog ../top.v
proc
tee -o result.log setparam -set WIDTH 1 top
read_verilog ../top.v
proc
tee -o result.log setparam top
read_verilog ../top.v
proc
tee -o result.log setparam -type $mux -set WIDTH 1 top
read_verilog ../top.v
proc
tee -o result.log setparam -set WIDTH 1 top
tee -o result.log setparam -unset WIDT top
read_verilog ../top.v
proc
tee -o result.log setundef -anyconst
read_verilog ../top.v
proc
tee -o result.log setundef -anyseq
read_verilog ../top.v
proc
tee -o result.log setundef -zero -expose -undriven
read_verilog ../top.v
proc
tee -o result.log setundef -zero -init
read_verilog ../top.v
proc
tee -o result.log setundef -one
read_verilog ../top.v
proc
tee -o result.log setundef -random 256
read_verilog ../top.v
proc
tee -o result.log setundef -undef
read_verilog ../top.v
proc
tee -o result.log setundef -zero -undriven
read_verilog -sv ../top.v
proc
tee -o result.log sim top
read_verilog -sv ../top.v
proc
tee -o result.log sim -a top
read_verilog -sv ../top.v
proc
tee -o result.log sim -clock x top
read_verilog ../top.v
proc
tee -o result.log sim -clock clk top
read_verilog ../top.v
proc
tee -o result.log sim -clockn clk top
read_verilog -sv ../top.v
proc
tee -o result.log sim -d top
read_verilog -sv ../top.v
proc
tee -o result.log sim -n 5 top
read_verilog ../top.v
proc
tee -o result.log sim -reset we_b top
read_verilog ../top.v
proc
tee -o result.log sim -resetn we_a top
read_verilog -sv ../top.v
proc
tee -o result.log sim -rstlen 2 top
read_verilog -sv ../top.v
proc
tee -o result.log sim -vcd vcd.vcd top
read_verilog -sv ../top.v
proc
tee -o result.log sim -w top
read_verilog -sv ../top.v
proc
tee -o result.log sim -zinit top
read_verilog ../top.v
memory_collect
proc
tee -o result.log sim -zinit top
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter WIDTH = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid (x,y,o);
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
//assign cout = cin? y : x;
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module u_rtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
......@@ -107,5 +107,16 @@ $(eval $(call template,extract_counter_sync_reset,extract_counter extract_counte
$(eval $(call template,shregmap,shregmap shregmap_clkpol_any shregmap_clkpol_neg shregmap_clkpol_pos shregmap_enpol_any shregmap_enpol_any_or_none shregmap_enpol_neg shregmap_enpol_none shregmap_enpol_pos shregmap_init shregmap_keep_after shregmap_keep_before shregmap_match shregmap_maxlen shregmap_minlen shregmap_params shregmap_tech shregmap_zinit))
$(eval $(call template,shregmap_resetable,shregmap shregmap_clkpol_any shregmap_clkpol_neg shregmap_clkpol_pos shregmap_enpol_any shregmap_enpol_any_or_none shregmap_enpol_neg shregmap_enpol_none shregmap_enpol_pos shregmap_init shregmap_keep_after shregmap_keep_before shregmap_match shregmap_maxlen shregmap_minlen shregmap_params shregmap_tech shregmap_zinit))
#design_import
$(eval $(call template,design_import, design_import design_import_as ))
#async2sync
$(eval $(call template,async2sync,async2sync))
#flowmap
$(eval $(call template,flowmap,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
$(eval $(call template,flowmap_latch,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
$(eval $(call template,flowmap_mem,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
.PHONY: all clean
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
module testbench;
reg [7:0] in;
wire pi_and,i_and;
wire pi_or,i_or;
wire pi_xor,i_xor;
wire pi_nand,i_nand;
wire pi_nor,i_nor;
wire pi_xnor,i_xnor;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in),
.o_and(i_and),
.o_or(i_or),
.o_xor(i_xor),
.o_nand(i_nand),
.o_nor(i_nor),
.o_xnor(i_xnor)
);
assign pi_and = &in;
assign pi_or = |in;
assign pi_xor = ^in;
assign pi_nand = ~&in;
assign pi_nor = ~|in;
assign pi_xnor = ~^in;
assert_comb and_test(.A(pi_and), .B(i_and));
endmodule
module top
(
input [7:0] x,
output o_and,
output o_or,
output o_xor,
output o_nand,
output o_nor,
output o_xnor
);
`ifndef BUG
assign o_and = &x;
assign o_or = |x;
assign o_xor = ^x;
assign o_nand = ~&x;
assign o_nor = ~|x;
assign o_xnor = ~^x;
`else
assign o_and = ~&x;
assign o_or = &x;
assign o_xor = ~^x;
assign o_nand = &x;
assign o_nor = ^x;
assign o_xnor = ~&x;
`endif
endmodule
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
module testbench;
reg en;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3;
reg lat,nlat,alat,alatn = 0;
top uut (
.en (en ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 )
);
always @(posedge en) begin
#3;
dinA <= dinA + 1;
end
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( dinA[2] )
lat <= 1'b0;
else if ( dinA[1] )
lat <= 1'b1;
else if ( en )
lat <= dinA[0];
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( !dinA[2] )
nlat <= 1'b0;
else if ( !dinA[1] )
nlat <= 1'b1;
else if (!en)
nlat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( dinA[2] )
alat <= 1'b0;
else if (en)
alat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( !dinA[2] )
alatn <= 1'b0;
else if (!en)
alatn <= dinA[0];
assert_dff lat_test(.clk(en), .test(doutB), .pat(lat));
assert_dff nlat_test(.clk(en), .test(doutB1), .pat(nlat));
assert_dff alat_test(.clk(en), .test(doutB2), .pat(alat));
assert_dff alatn_test(.clk(en), .test(doutB3), .pat(alatn));
endmodule
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
wire [7:0] q_a,q_b;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module top
(
input [7:0] data_a, data_b,
input [5:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
read_verilog ../top.v
proc
async2sync
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
design -save top
design -import top
write_verilog synth.v
read_verilog ../top.v
proc
design -save top
design -import top -as top_new
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -cells $dff top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -debug top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -debug-relax top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -maxlut 4 top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -minlut 2 top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -optarea 3 top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -r-alpha 3 top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -r-beta 3 top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -r-gamma 3 top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -relax top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -relax -debug top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap -relax -debug-relax top
write_verilog synth.v
read_verilog ../top.v
synth -top top
flowmap top
write_verilog synth.v
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