Skip to content

Y
yosys-tests
Commit 2c633693 by SergeyDegtyar
Options

Fix regressions on build #179

parent 58aa1c9e
Showing with 2 additions and 2 deletions
architecture/run.sh
...@@ -100,9 +100,9 @@ else ...@@ -100,9 +100,9 @@ else
elif [ "$1" = "synth_ice40_fulladder" ]; then elif [ "$1" = "synth_ice40_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "ice40_wrapcarry" ]; then elif [ "$1" = "ice40_wrapcarry" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v $TECHLIBS_PREFIX/ice40/abc_model.v
elif [ "$1" = "ice40_wrapcarry_adders" ]; then elif [ "$1" = "ice40_wrapcarry_adders" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v $TECHLIBS_PREFIX/ice40/abc_model.v
elif [ "$1" = "synth_intel" ]; then elif [ "$1" = "synth_intel" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
elif [ "$1" = "synth_intel_a10gx" ]; then elif [ "$1" = "synth_intel_a10gx" ]; then
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment