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lvzhengyang
yosys-tests
Commits
2ba32455
Commit
2ba32455
authored
Jul 17, 2020
by
Miodrag Milanovic
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Plain Diff
clock buffering is no default anymore
parent
c3cc2229
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10 changed files
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24 additions
and
42 deletions
+24
-42
architecture/synth_sf2/synth_sf2.ys
+0
-2
architecture/synth_sf2/synth_sf2_clkbuf.ys
+8
-8
architecture/synth_sf2/synth_sf2_edif.ys
+2
-4
architecture/synth_sf2/synth_sf2_json.ys
+2
-4
architecture/synth_sf2/synth_sf2_noflatten.ys
+2
-4
architecture/synth_sf2/synth_sf2_noiobs.ys
+2
-4
architecture/synth_sf2/synth_sf2_retime.ys
+2
-4
architecture/synth_sf2/synth_sf2_run.ys
+2
-4
architecture/synth_sf2/synth_sf2_top.ys
+2
-4
architecture/synth_sf2/synth_sf2_vlog.ys
+2
-4
No files found.
architecture/synth_sf2/synth_sf2.ys
View file @
2ba32455
...
@@ -9,7 +9,6 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,7 +9,6 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
...
@@ -25,7 +24,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,7 +24,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
...
...
architecture/synth_sf2/synth_sf2_clkbuf.ys
View file @
2ba32455
...
@@ -5,28 +5,28 @@ hierarchy -top dff
...
@@ -5,28 +5,28 @@ hierarchy -top dff
proc
proc
#-assert option was skipped because of unproven cells
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2
-clkbuf
# equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLK
INT
select -assert-count 1 t:CLK
BUF
select -assert-count
2
t:INBUF
select -assert-count
1
t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CLK
INT
t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CLK
BUF
t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
proc
proc
#-assert option was skipped because of unproven cells
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2
-clkbuf
# equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLK
INT
select -assert-count 1 t:CLK
BUF
select -assert-count
3
t:INBUF
select -assert-count
2
t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLK
INT
t:INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:CLK
BUF
t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_edif.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_json.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_noflatten.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_noiobs.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_retime.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_run.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_top.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_vlog.ys
View file @
2ba32455
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
...
@@ -9,11 +9,10 @@ equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
design -load read
hierarchy -top dffe
hierarchy -top dffe
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -25,8 +24,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffe # Constrain all select calls below inside the top module
cd dffe # Constrain all select calls below inside the top module
stat
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:
CLKINT t:
INBUF t:OUTBUF t:SLE %% t:* %D
select -assert-none t:CFG3 t:INBUF t:OUTBUF t:SLE %% t:* %D
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