More tests

architecture/synth_xilinx_srl/test13.ys

@@ -5,5 +5,7 @@ clean -purge
 write_verilog synth13.v
 
 # Check that non chain users block SRLs
-cd synth; cd sr_fixed_length_other_users; select t:SRL* -assert-count 0
-cd synth; cd sr_var_length_other_users; select t:SRL* -assert-count 0
+cd synth; cd sr_fixed_length_other_users_port; select t:SRL* -assert-count 0
+cd synth; cd sr_var_length_other_users_port; select t:SRL* -assert-count 0
+cd synth; cd sr_fixed_length_other_users_xor; select t:SRL* -assert-count 0
+cd synth; cd sr_var_length_other_users_xor; select t:SRL* -assert-count 0

architecture/synth_xilinx_srl/testbench.v

@@ -48,9 +48,7 @@ module testbench;
 
     generate
         genvar i;
-        // FIXME: https://github.com/YosysHQ/yosys/issues/873
-        //for (i = 0; i < `N; i=i+1) begin
-        for (i = 1; i < `N; i=i+1) begin
+        for (i = 0; i < `N; i=i+1) begin
             always @(posedge clk)
                 a[i] <= $random;
             assert_dff zp_test(.clk(clk), .test(z[i]), .pat(y[i]));

architecture/synth_xilinx_srl/top.v

@@ -5,74 +5,74 @@ generate
     genvar i;
 `ifdef TEST1
     for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred
-        shift_reg #(.depth(i+1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state0 */);
+        shift_reg #(.depth(i+1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state */);
     end
 `elsif TEST2
     for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_no_init_not_inferred
-        shift_reg #(.depth(i+1)) sr(clk, a[i], e, /*l*/, z[i], /* state0 */);
+        shift_reg #(.depth(i+1)) sr(clk, a[i], e, /*l*/, z[i], /* state */);
     end
 `elsif TEST3
     for (i = 0; i < `N; i=i+1) begin : pos_clk_with_enable_with_init_inferred
-        shift_reg #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i], /* state0 */);
+        shift_reg #(.depth(i+1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i], /* state */);
     end
 `elsif TEST4
     for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_not_inferred
-        shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state0 */);
+        shift_reg #(.depth(i+1), .neg_clk(1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state */);
     end
 `elsif TEST5
     for (i = 0; i < `N; i=i+1) begin : neg_clk_no_enable_no_init_inferred
-        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state0 */);
+        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1)) sr(clk, a[i], 1'b1, /*l*/, z[i], /* state */);
     end
 `elsif TEST6
     for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred
-        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i], /* state0 */);
+        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1)) sr(clk, a[i], e, /*l*/, z[i], /* state */);
     end
 `elsif TEST7
     // Check that use of resets block shreg
-    shift_reg #(.depth(129), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[1], r, /*l*/, z[0], /* state0 */);
-    shift_reg #(.depth(129), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[2], r, /*l*/, z[1], /* state0 */);
-    shift_reg #(.depth(128), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset_var_len(clk, a[2], r, l, z[2], /* state0 */);
-    shift_reg #(.depth(129), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset_var_len(clk, a[3], r, l, z[3], /* state0 */);
+    shift_reg #(.depth(129), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset(clk, a[1], r, /*l*/, z[0], /* state */);
+    shift_reg #(.depth(129), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset(clk, a[2], r, /*l*/, z[1], /* state */);
+    shift_reg #(.depth(128), .er_is_reset(1)) pos_clk_no_enable_no_init_not_inferred_with_reset_var_len(clk, a[2], r, l[6:0], z[2], /* state */);
+    shift_reg #(.depth(129), .neg_clk(1), .inferred(1), .init(1), .er_is_reset(1)) neg_clk_no_enable_with_init_with_inferred_with_reset_var_len(clk, a[3], r, l, z[3], /* state */);
     assign z[`N-1:4] = 'b0; // Suppress no driver warning
 `elsif TEST8
     // Check multi-bit works
     (* keep *)
-    shift_reg #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, /*l*/, z, /* state0 */);
+    shift_reg #(.depth(`N), .width(`N)) pos_clk_no_enable_no_init_not_inferred_N_width(clk, a, r, /*l*/, z, /* state */);
 `elsif TEST9
     (* keep *)
-    shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, /*l*/, z, /* state0 */);
+    shift_reg #(.depth(`N), .width(`N), .neg_clk(1), .inferred(1), .init(1)) neg_clk_no_enable_with_init_with_inferred_N_width(clk, a, r, /*l*/, z, /* state */);
 `elsif TEST10
-    // FIXME: YosysHQ/yosys#873
-    for (i = /*0*/1; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred_var_len
-        shift_reg #(.depth(i+1), .fixed_length(0)) sr(clk, a[i], 1'b1, l[$clog2(i+1)-1:0], z[i], /* state0 */);
+    for (i = 0; i < `N; i=i+1) begin : pos_clk_no_enable_no_init_not_inferred_var_len
+        shift_reg #(.depth(i+2), .fixed_length(0)) sr(clk, a[i], 1'b1, l[$clog2(i+2)-1:0], z[i], /* state */);
     end
-    assign z[0] = 'b0; // Suppress no driver warning
 `elsif TEST11
-    // FIXME: YosysHQ/yosys#873
-    for (i = /*0*/1; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred_var_len
-        shift_reg #(.depth(i+1), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0)) sr(clk, a[i], e, l[$clog2(i+1)-1:0], z[i], /* state0 */);
+    for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred_var_len
+        shift_reg #(.depth(i+2), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0)) sr(clk, a[i], e, l[$clog2(i+2)-1:0], z[i], /* state */);
     end
-    assign z[0] = 'b0; // Suppress no driver warning
 `elsif TEST12
     for (i = 0; i < `N; i=i+1) begin : lfsr
         lfsr #(.len(i+3)) sr(clk, z[i]);
     end
 `elsif TEST13
-    // Check that non chain users (i.e. output port, in non flattened case) block SRLs
-    shift_reg #(.depth(128), .output_index(0)) sr_fixed_length_other_users(clk, a[0], r, /*l*/, z[0], /* state0 */);
-    shift_reg #(.depth(128), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0), .output_index(0)) sr_var_length_other_users(clk, a[1], e, l[$clog2(128)-1:0], z[1], /* state0 */);
-    assign z[`N-1:2] = 'b0; // Suppress no driver warning
+    // Check that non chain users block SRLs
+    // (i.e. output port, in non flattened case)
+    shift_reg #(.depth(128), .output_index(0)) sr_fixed_length_other_users_port(clk, a[0], r, /*l*/, z[0], /* state */);
+    shift_reg #(.depth(128), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0), .output_index(0)) sr_var_length_other_users_port(clk, a[1], e, l[$clog2(128)-1:0], z[1], /* state */);
+    shift_reg #(.depth(128), .output_xor(1)) sr_fixed_length_other_users_xor(clk, a[2], r, /*l*/, z[2], /* state */);
+    shift_reg #(.depth(128), .neg_clk(1), .inferred(1), .init(1), .fixed_length(0), .output_xor(1)) sr_var_length_other_users_xor(clk, a[3], e, l[$clog2(128)-1:0], z[3], /* state */);
+    assign z[`N-1:4] = 'b0; // Suppress no driver warning
 `endif
 endgenerate
 endmodule
 
-module shift_reg #(parameter width=1, depth=1) (input clk, input [width-1:0] a, input er, input [$clog2(depth)-1:0] l, output [width-1:0] z, output [depth-1:0] state0);
+module shift_reg #(parameter width=1, depth=1) (input clk, input [width-1:0] a, input er, input [$clog2(depth)-1:0] l, output [width-1:0] z, output [depth-1:0] state);
 parameter inferred = 0;
 parameter init = 0;
 parameter neg_clk = 0;
 parameter er_is_reset = 0;
 parameter fixed_length = depth;
 parameter output_index = -1;
+parameter output_xor = 0;
 generate 
     if (inferred == 0) begin
         wire [depth:0] int [width-1:0];
@@ -103,9 +103,11 @@ generate
             end
         end
         if (output_index >= 0)
-            assign state0 = int[output_index][depth:1];
+            assign state = int[output_index][depth:1];
+        else if (output_xor)
+            assign state = {depth{^int[0][depth:1]}};
         else
-            assign state0 = {depth{1'b0}};
+            assign state = {depth{1'b0}};
     end
     else begin
         reg [depth-1:0] int [width-1:0];
@@ -161,9 +163,11 @@ generate
             end
         end
         if (output_index >= 0)
-            assign state0 = int[output_index];
+            assign state = int[output_index];
+        else if (output_xor)
+            assign state = {depth{^int[0]}};
         else
-            assign state0 = {depth{1'b0}};
+            assign state = {depth{1'b0}};
     end
 endgenerate
 endmodule