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lvzhengyang
yosys-tests
Commits
25ef4356
Commit
25ef4356
authored
Jan 27, 2019
by
Miodrag Milanovic
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Enabled Anlogic tests
parent
a55974ec
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2 changed files
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6 additions
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6 deletions
+6
-6
architecture/Makefile
+4
-6
architecture/run.sh
+2
-0
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architecture/Makefile
View file @
25ef4356
...
...
@@ -17,14 +17,12 @@ clean::
))
endef
#achronix
(in the code '-flatten' but in the help '-noflatten')
#achronix
$(eval
$(call
template,synth_achronix,synth_achronix
synth_achronix_top
synth_achronix_vout
synth_achronix_run
synth_achronix_noflatten
synth_achronix_retime))
#anlogic
#../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to bind wire/reg/memory `A' in `testbench.uut._09_'
#../../../../../techlibs/anlogic/cells_sim.v:20: error: Unable to elaborate r-value: (INIT)>>(A)
#$(eval $(call template,synth_anlogic,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
#$(eval $(call template,synth_anlogic_fulladder,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval
$(call
template,synth_anlogic,synth_anlogic
synth_anlogic_top
synth_anlogic_edif
synth_anlogic_json
synth_anlogic_run
synth_anlogic_noflatten
synth_anlogic_retime))
$(eval
$(call
template,synth_anlogic_fulladder,synth_anlogic
synth_anlogic_top
synth_anlogic_edif
synth_anlogic_json
synth_anlogic_run
synth_anlogic_noflatten
synth_anlogic_retime))
#coolrunner2
$(eval
$(call
template,synth_coolrunner2,synth_coolrunner2
synth_coolrunner2_top
synth_coolrunner2_vout
synth_coolrunner2_run
synth_coolrunner2_noflatten
synth_coolrunner2_retime))
...
...
@@ -41,7 +39,7 @@ $(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout
#ice40
$(eval
$(call
template,synth_ice40,synth_ice40
synth_ice40_top
synth_ice40_blif
synth_ice40_edif
synth_ice40_json
synth_ice40_run
synth_ice40_noflatten
synth_ice40_flatten
synth_ice40_retime
synth_ice40_nocarry
synth_ice40_nodffe
synth_ice40_nobram
synth_ice40_abc2
synth_ice40_vpr))
#intel
(in the code '-flatten' but in the help '-noflatten')
#intel
$(eval
$(call
template,synth_intel,synth_intel
synth_intel_top
synth_intel_vqm
synth_intel_vpr
synth_intel_run
synth_intel_noflatten
synth_intel_retime
synth_intel_noiopads
synth_intel_nobram
synth_intel_max10
))
$(eval
$(call
template,synth_intel_cycloneiv,synth_intel_cycloneiv
))
$(eval
$(call
template,synth_intel_cycloneive,synth_intel_cycloneive
))
...
...
architecture/run.sh
View file @
25ef4356
...
...
@@ -15,6 +15,8 @@ elif [ "$1" = "synth_achronix" ]; then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/achronix/speedster22i/cells_sim.v
elif
[
"
$1
"
=
"synth_anlogic"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
elif
[
"
$1
"
=
"synth_anlogic_fulladder"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
elif
[
"
$1
"
=
"synth_coolrunner2"
]
;
then
iverilog
-o
testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
elif
[
"
$1
"
=
"synth_gowin"
]
;
then
...
...
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