Two more fixes

architecture/synth_ice40/synth_ice40_wide_ffs.ys

@@ -41,8 +41,8 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffse # Constrain all select calls below inside the top module
 stat
-select -assert-count 1 t:SB_DFFE
-select -assert-count 2 t:SB_DFFESR
+
+select -assert-count 3 t:SB_DFFESR
 select -assert-count 1 t:SB_DFFESS
 select -assert-count 4 t:SB_LUT4
-select -assert-none t:SB_DFFE t:SB_DFFESR t:SB_DFFESS t:SB_LUT4 %% t:* %D
+select -assert-none t:SB_DFFESR t:SB_DFFESS t:SB_LUT4 %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys

@@ -21,6 +21,5 @@ select -assert-count 1 t:LUT2
 select -assert-count 10 t:LUT3
 select -assert-count 24 t:LUT4
 select -assert-count 16 t:RAM128X1D
-select -assert-count 8 t:INV
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D t:INV %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:RAM128X1D %% t:* %D