Update test cases

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_bytewrite_ram_1b.ys

@@ -18,6 +18,7 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 32 t:FDRE
 select -assert-count 32 t:LUT2
+select -assert-count 4 t:LUT6
 select -assert-count 32 t:RAM32X1D
 
-select -assert-none t:BUFG t:FDRE t:LUT2 t:RAM32X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT6 t:RAM32X1D %% t:* %D

regression/issue_00867/issue_00867.ys

 read_verilog top.v
 synth_xilinx -flatten
-select -assert-count 1 t:RAMB36E1
+select -assert-count 3 t:RAMB18E1