Fix intel architecture tests

architecture/Makefile

@@ -54,7 +54,7 @@ $(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ic
 $(eval $(call template,synth_ice40_error,synth_ice40_fully_selected))
 
 #intel
-$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_noiopads synth_intel_nobram synth_intel_max10 ))
+$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_iopads synth_intel_nobram synth_intel_max10 ))
 $(eval $(call template,synth_intel_cycloneiv,synth_intel_cycloneiv  ))
 $(eval $(call template,synth_intel_cycloneive,synth_intel_cycloneive   ))
 $(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))

architecture/run.sh

@@ -19,7 +19,7 @@ if echo "$1" | grep ".*_error"; then
 	elif [ "$2" = "synth_greenpak4_invalid_part" ]; then
 		expected_string="ERROR: Invalid part name: "
 	elif [ "$2" = "synth_intel_invalid_family" ]; then
-		expected_string="ERROR: Invalid or not family specified"
+		expected_string="ERROR: Invalid or no family specified:"
 	elif [ "$2" = "synth_xilinx_invalid_arch" ]; then
 		expected_string="ERROR: Invalid Xilinx -family setting: "
 	fi

architecture/scripts/synth_intel_noiopads.ys → architecture/scripts/synth_intel_iopads.ys

 read_verilog ../top.v
-synth_intel -noiopads
+synth_intel -iopads
 write_verilog synth.v