Update backends group.

- write_aiger;
- write_blif;
- write_btor;
- write_edif;
- write_firrtl;
- write_ilang.

backends_reviewed/.gitignore

+*/work_*/
+/.stamp
+/run-test.mk

backends_reviewed/Makefile

+PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
+
+all:: run-test.mk
+	@touch .stamp
+	@$(MAKE) -f run-test.mk 
+clean:: run-test.mk
+	@rm -f .stamp
+	@$(MAKE) -f run-test.mk clean
+
+run-test.mk: ../generate.py
+	@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
+
+.PHONY: all clean

backends_reviewed/write_aiger/top3.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+
+endmodule

backends_reviewed/write_aiger/top_diff_cells.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

backends_reviewed/write_aiger/top_two_mods.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule
+
+module top2
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

backends_reviewed/write_aiger/top_x_z.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output X
+ );
+
+ reg ASSERT = 1'bX;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 1'bX;
+        cout = 1'bZ;
+    end
+ end
+
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 1'bX;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 1'bZ;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+assign X = 1'bX;
+
+endmodule
+

backends_reviewed/write_aiger/write_aiger.pat

+aig 5 5 0 2 0
+2
+10
+c

backends_reviewed/write_aiger/write_aiger.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger result.out
+design -reset
+read_aiger result.out

backends_reviewed/write_aiger/write_aiger_B.pat

+aig 5 5 0 2 0 1 0 0 0
+2
+10
+0
+c

backends_reviewed/write_aiger/write_aiger_B.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -B result.out
+design -reset
+read_aiger result.out

backends_reviewed/write_aiger/write_aiger_I.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -I aiger.aiger
+design -reset
+read_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_O.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -O aiger.aiger
+design -reset
+read_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_ascii.pat

+aag 5 5 0 2 0
+2
+4
+6
+8
+10
+2
+10
+c

backends_reviewed/write_aiger/write_aiger_ascii.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -ascii result.out
+design -reset
+read_aiger result.out

backends_reviewed/write_aiger/write_aiger_ascii_diff_cells.ys

+read_verilog -sv ../top_diff_cells.v
+aigmap
+write_aiger -ascii aiger.aiger

backends_reviewed/write_aiger/write_aiger_cant_find_top_module_fail.pat

+ERROR: Can't find top module in current design!

backends_reviewed/write_aiger/write_aiger_cant_find_top_module_fail.ys

+read_verilog -sv ../top_two_mods.v
+aigmap
+write_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_cant_open_file_fail.pat

+ERROR: Can't open file

backends_reviewed/write_aiger/write_aiger_cant_open_file_fail.ys

+read_verilog -sv ../top_x_z.v
+aigmap
+write_aiger -map tt/tt.map aiger.aiger

backends_reviewed/write_aiger/write_aiger_diff_cells.ys

+read_verilog -sv ../top_diff_cells.v
+aigmap
+write_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_diff_cells_proc.ys

+read_verilog -sv ../top_diff_cells.v
+synth
+aigmap
+write_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_map.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -map a.map aiger.aiger
+design -reset
+read_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_miter.pat

+aig 11 3 2 0 6 2
+16
+22
+8
+10

backends_reviewed/write_aiger/write_aiger_miter.ys

+read_verilog -sv ../top3.v
+synth -top top
+aigmap
+write_aiger -miter result.out
+design -reset
+read_aiger result.out

backends_reviewed/write_aiger/write_aiger_miter_and_asserts_fail.pat

+ERROR: Running AIGER back-end in -miter mode, but design contains \$assert, \$assume, \$live and/or \$fair cells!

backends_reviewed/write_aiger/write_aiger_miter_and_asserts_fail.ys

+read_verilog -sv ../top_x_z.v
+aigmap
+write_aiger -miter aiger.aiger

backends_reviewed/write_aiger/write_aiger_symbols.pat

+i1 x
+i2 y
+i3 cin
+o0 A
+o1 cout

backends_reviewed/write_aiger/write_aiger_symbols.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -symbols result.out
+design -reset
+read_aiger result.out

backends_reviewed/write_aiger/write_aiger_symbols_diff_cells.ys

+read_verilog -sv ../top_diff_cells.v
+aigmap
+write_aiger -symbols aiger.aiger

backends_reviewed/write_aiger/write_aiger_unsupported_cell_type_fail.pat

+ERROR: Unsupported cell type:

backends_reviewed/write_aiger/write_aiger_unsupported_cell_type_fail.ys

+read_verilog -sv ../top_x_z.v
+synth
+write_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_vmap.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -vmap a.map aiger.aiger
+design -reset
+read_aiger aiger.aiger

backends_reviewed/write_aiger/write_aiger_zinit.ys

+read_verilog -sv ../top3.v
+aigmap
+write_aiger -zinit aiger.aiger
+design -reset
+read_aiger aiger.aiger

backends_reviewed/write_blif/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg A1,cout1;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(negedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(*) begin
+    if (x)
+        A <=  A1|y~&cin;
+end
+always @(*) begin
+    if (~x)
+        cout <=  cout1&cin~|y;
+end
+
+bb ubb (cin,y,x,A);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+
+ output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+endmodule

backends_reviewed/write_blif/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends_reviewed/write_blif/top_mux.v

+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+ 	assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M16
+);
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

backends_reviewed/write_blif/write_blif.ys

+read_verilog -sv ../top.v
+proc
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_abc_and_nor.ys

+read_verilog -sv ../top.v
+synth
+abc -g AND,XOR,NOR
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_abc_lut.ys

+read_verilog -sv ../top.v
+synth
+abc -lut 2
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_abc_sop.ys

+read_verilog -sv ../top.v
+synth
+abc -sop
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_andnot.ys

+read_verilog -sv ../top.v
+synth
+abc -g ANDNOT,ORNOT
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_aoi4.ys

+read_verilog -sv ../top.v
+abc -g AOI4
+synth -top top
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_attr.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -attr blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_blackbox.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -blackbox blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_buf.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -buf a a a blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_cant_find_top_module_fail.pat

+ERROR: Can't find top module

backends_reviewed/write_blif/write_blif_cant_find_top_module_fail.ys

+read_verilog -sv ../top.v
+proc
+write_blif -top u blif1.blif

backends_reviewed/write_blif/write_blif_cmos3.ys

+read_verilog -sv ../top.v
+synth
+abc -g cmos3
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_cmos4.ys

+read_verilog -sv ../top_mux.v
+synth -top top
+abc -g cmos4
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_cname.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -cname blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_conn.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -conn blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_false.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -false a a blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_gates.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -gates blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_iattr.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -iattr blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_icells.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -icells blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_impltf.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -impltf blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_iname.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -iname blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_noalias.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -noalias blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_opt.ys

+read_verilog -sv ../top.v
+proc
+opt
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_param.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -param blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_synth_top.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_top.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -top top blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_true.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -true a a blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_unbuf.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -unbuf a a a blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_undef.ys

+read_verilog -sv ../top.v
+synth -top top
+write_blif -undef a a blif.blif
+design -reset
+read_blif blif.blif

backends_reviewed/write_blif/write_blif_unmapped_mem_fail.pat

+ERROR: Found unmapped memories in module

backends_reviewed/write_blif/write_blif_unmapped_mem_fail.ys

+read_verilog -sv ../top_mem.v
+proc
+write_blif -top u blif1.blif

backends_reviewed/write_blif/write_blif_unmapped_proc_fail.pat

+ERROR: Found unmapped processes in module

backends_reviewed/write_blif/write_blif_unmapped_proc_fail.ys

+read_verilog -sv ../top.v
+write_blif blif1.blif

backends_reviewed/write_btor/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(posedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

backends_reviewed/write_btor/top_and_or.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+
+ initial begin
+    B = 0;
+ end
+
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+
+endmodule

backends_reviewed/write_btor/top_div_mod.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output reg B,C
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    A <=  y / too;
+end
+always @(posedge x) begin
+        cout <=  y + A % foo;
+end
+assign {B,C} =  {cout,A} << 1;
+
+endmodule

backends_reviewed/write_btor/top_fsm.v

+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (b == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (a == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (a == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (a == 1'b1 && b == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (a == 1'b1 || b == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign s   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign f = (st == S13) ? 1'b1 : 1'b0;
+
+	assign bs   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule

backends_reviewed/write_btor/top_init_assert.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(posedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

backends_reviewed/write_btor/top_logic.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg A1,cout1;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ~^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+
+endmodule

backends_reviewed/write_btor/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends_reviewed/write_btor/top_no_top_mod.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+end
+
+endmodule
+
+module top2
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+
+end
+always @(posedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+
+end
+
+endmodule
+

backends_reviewed/write_btor/top_pmux.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

backends_reviewed/write_btor/top_shift.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output reg B,C
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    A <=  y >> too;
+end
+always @(posedge x) begin
+        cout <=  y + A >>> foo;
+end
+assign {B,C} =  {cout,A} << 1;
+
+endmodule

backends_reviewed/write_btor/top_shift_shiftx.v

+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input   clock,reset,req_0,req_1;
+ output  gnt_0,gnt_1;
+ wire    clock,reset,req_0,req_1;
+ reg     gnt_0,gnt_1;
+
+ parameter SIZE = 3           ;
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+   state <=  #1  IDLE;
+   gnt_0 <= 0;
+   gnt_1 <= 0;
+ end else
+  case(state)
+    IDLE : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+                 gnt_0 <= 1;
+               end else if (req_1 == 1'b1) begin
+                 gnt_1 <= 1;
+                 state <=  #1  GNT0;
+               end else begin
+                 state <=  #1  IDLE;
+               end
+    GNT0 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+               end else begin
+                 gnt_0 <= 0;
+                 state <=  #1  IDLE;
+               end
+    GNT1 : if (req_1 == 1'b1) begin
+                 state <=  #1  GNT2;
+				 gnt_1 <= req_0;
+               end
+    GNT2 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT1;
+				 gnt_1 <= req_1;
+               end
+    default : state <=  #1  IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+            .reset(rst),
+            .req_0(a),
+            .req_1(b),
+            .gnt_0(g0),
+            .gnt_1(g1));
+
+endmodule

backends_reviewed/write_btor/top_shiftx.v

+
+// VERIFIC-SKIP
+
+module top(a, y);
+
+input signed [4:0] a;
+output signed y;
+
+integer i = 0, j = 0;
+reg [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule

backends_reviewed/write_btor/top_unsupp_cell.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

backends_reviewed/write_btor/write_btor.ys

+read_verilog -sv ../top.v
+hierarchy -top top
+proc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_abc.ys

+read_verilog -sv ../top.v
+synth
+abc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_abc_and_nor.ys

+read_verilog -sv ../top.v
+synth -top top
+abc -g AND,XOR,NOR
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_and_or.ys

+read_verilog -sv ../top_and_or.v
+proc
+write_btor btor.btor
+design -reset
+read_verilog  -sv ../top_and_or.v
+synth -top top
+write_verilog synth.v

backends_reviewed/write_btor/write_btor_andnot.ys

+read_verilog -sv ../top.v
+synth -top top
+abc -g ANDNOT,ORNOT
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_aoi4.ys

+read_verilog -sv ../top.v
+abc -g cmos4
+synth -top top
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_cmos3.ys

+read_verilog -sv ../top.v
+synth -top top
+abc -g cmos3
+write_btor btor6.btor

backends_reviewed/write_btor/write_btor_div_mod.ys

+read_verilog -sv ../top_div_mod.v
+hierarchy -top top
+proc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_fsm.ys

+read_verilog -sv ../top_fsm.v
+proc
+pmux2shiftx
+hierarchy -top top
+flatten
+write_btor btor.btor
+write_verilog synth.v

backends_reviewed/write_btor/write_btor_init_assert.ys

+read_verilog -sv ../top_init_assert.v
+hierarchy -top top
+proc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_logic.ys

+read_verilog -sv ../top_logic.v
+hierarchy -top top
+proc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_mem.ys

+read_verilog -sv ../top_mem.v
+memory
+proc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_mem_s.ys

+read_verilog -sv ../top_mem.v
+memory
+proc
+write_btor -s btor.btor

backends_reviewed/write_btor/write_btor_mem_v.ys

+read_verilog -sv ../top_mem.v
+memory
+proc
+write_btor -v btor.btor

backends_reviewed/write_btor/write_btor_no_top_module_fail.pat

+ERROR: No top module found.

backends_reviewed/write_btor/write_btor_no_top_module_fail.ys

+read_verilog -sv ../top_no_top_mod.v
+proc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_oai3.ys

+read_verilog -sv ../top_fsm.v
+synth -top top
+abc -g cmos3
+write_btor btor6.btor

backends_reviewed/write_btor/write_btor_oai4.ys

+read_verilog -sv ../top_fsm.v
+abc -g OAI4
+synth -top top
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_pmux.ys

+read_verilog -sv ../top_pmux.v
+proc
+write_btor -v btor.btor
+synth -top top
+write_verilog synth.v

backends_reviewed/write_btor/write_btor_proc.ys

+read_verilog -sv ../top.v
+proc_prune
+proc_init
+proc_mux
+proc_dff
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_s.ys

+read_verilog -sv ../top.v
+hierarchy -top top
+proc
+write_btor -s btor.btor

backends_reviewed/write_btor/write_btor_shift.ys

+read_verilog -sv ../top_shift.v
+proc
+pmux2shiftx
+hierarchy -top top
+flatten
+write_btor btor.btor
+write_verilog synth.v

backends_reviewed/write_btor/write_btor_shift_shiftx.ys

+read_verilog -sv ../top_shift_shiftx.v
+proc
+pmux2shiftx
+hierarchy -top top
+flatten
+write_btor btor.btor
+write_verilog synth.v

backends_reviewed/write_btor/write_btor_shiftx.ys

+read_verilog -sv ../top_shiftx.v
+proc
+pmux2shiftx
+hierarchy -top top
+flatten
+write_btor btor.btor
+write_verilog synth.v

backends_reviewed/write_btor/write_btor_simplemap.ys

+read_verilog -sv ../top.v
+synth -top top
+simplemap
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_synth.ys

+read_verilog -sv ../top.v
+synth -top top
+write_btor btor1.btor

backends_reviewed/write_btor/write_btor_unsupported_cell_type_fail.pat

+ERROR: Unsupported cell type: $_DFF_N_

backends_reviewed/write_btor/write_btor_unsupported_cell_type_fail.ys

+read_verilog -sv ../top_unsupp_cell.v
+synth
+abc
+write_btor btor.btor

backends_reviewed/write_btor/write_btor_v.ys

+read_verilog -sv ../top.v
+hierarchy -top top
+proc
+write_btor -v btor.btor

backends_reviewed/write_edif/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ wire bb_out;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+
+bb ubb (cin,y,x,bb_out);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+endmodule

backends_reviewed/write_edif/top_const_nodes.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output X
+ );
+
+ wire bb_out;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+
+assign X = 1'bX;
+
+bb ubb (cin,y,x,bb_out);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+endmodule

backends_reviewed/write_edif/top_cyclic_dep.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout,
+ output X
+ );
+
+ wire bb_out;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+
+assign X = 1'bX;
+
+bb ubb (cin,y,x,bb_out);
+
+endmodule
+
+(* black_box *) module bb(in1, in2, clk, out1);
+ input in1;
+ input in2;
+ input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
+
+	top utop (in1,in2,clk,out1);
+endmodule

backends_reviewed/write_edif/top_unmap_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends_reviewed/write_edif/write_edif.pat

+    (cell top
+      (cellType GENERIC)
+      (view VIEW_NETLIST
+        (viewType NETLIST)
+        (interface
+          (port cout (direction OUTPUT))
+          (port A (direction OUTPUT))
+          (port cin (direction INPUT))
+          (port y (direction INPUT))
+          (port x (direction INPUT))
+        )

backends_reviewed/write_edif/write_edif.ys

+read_verilog ../top.v
+proc
+write_edif result.out

backends_reviewed/write_edif/write_edif_attrprop.pat

+            (property src (string "../top.v:39")))

backends_reviewed/write_edif/write_edif_attrprop.ys

+read_verilog ../top.v
+proc
+write_edif -attrprop result.out

backends_reviewed/write_edif/write_edif_constant_nodes_fail.pat

+ERROR: Design contains constant nodes (map with "hilomap" first).

backends_reviewed/write_edif/write_edif_constant_nodes_fail.ys

+read_verilog -sv ../top_const_nodes.v
+proc
+write_edif -nogndvcc edif.edif

backends_reviewed/write_edif/write_edif_cyclic_dependency_fail.pat

+ERROR: Cyclic dependency between modules found! Cycle includes module bb.

backends_reviewed/write_edif/write_edif_cyclic_dependency_fail.ys

+read_verilog -sv ../top_cyclic_dep.v
+proc
+write_edif edif.edif

backends_reviewed/write_edif/write_edif_no_module_found_fail.pat

+ERROR: No module found in design!

backends_reviewed/write_edif/write_edif_no_module_found_fail.ys

+write_edif edif.edif

backends_reviewed/write_edif/write_edif_nogndvcc.ys

+read_verilog ../top.v
+proc
+write_edif -nogndvcc result.out

backends_reviewed/write_edif/write_edif_nogndvcc_n.pat

+cell GND

backends_reviewed/write_edif/write_edif_pvector_ang.ys

+read_verilog ../top.v
+proc
+write_edif -pvector ang edif.edif

backends_reviewed/write_edif/write_edif_pvector_bra.ys

+read_verilog ../top.v
+proc
+write_edif -pvector bra edif.edif

backends_reviewed/write_edif/write_edif_pvector_par.ys

+read_verilog ../top.v
+proc
+write_edif -pvector par edif.edif

backends_reviewed/write_edif/write_edif_top.pat

+(edif top

backends_reviewed/write_edif/write_edif_top.ys

+read_verilog ../top.v
+proc
+write_edif -top top result.out

backends_reviewed/write_edif/write_edif_unmapped_mem_fail.pat

+ERROR: Found unmapped memories in module top: unmapped memories are not supported in EDIF backend!

backends_reviewed/write_edif/write_edif_unmapped_mem_fail.ys

+read_verilog ../top_unmap_mem.v
+proc
+write_edif -top top edif.edif

backends_reviewed/write_edif/write_edif_unmapped_proc_fail.pat

+ERROR: Found unmapped processes in module bb: unmapped processes are not supported in EDIF backend!

backends_reviewed/write_edif/write_edif_unmapped_proc_fail.ys

+read_verilog ../top.v
+write_edif -top top edif.edif

backends_reviewed/write_firrtl/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+
+ initial begin
+    B = 0;
+ end
+
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+
+endmodule

backends_reviewed/write_firrtl/top_complex_write_enable.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [0:0] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends_reviewed/write_firrtl/top_fsm.v

+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input   clock,reset,req_0,req_1;
+ output  gnt_0,gnt_1;
+ wire    clock,reset,req_0,req_1;
+ reg     gnt_0,gnt_1;
+
+ parameter SIZE = 3           ;
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+   state <=  #1  IDLE;
+   gnt_0 <= 0;
+   gnt_1 <= 0;
+ end else
+  case(state)
+    IDLE : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+                 gnt_0 <= 1;
+               end else if (req_1 == 1'b1) begin
+                 gnt_1 <= 1;
+                 state <=  #1  GNT0;
+               end else begin
+                 state <=  #1  IDLE;
+               end
+    GNT0 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+               end else begin
+                 gnt_0 <= 0;
+                 state <=  #1  IDLE;
+               end
+    GNT1 : if (req_1 == 1'b1) begin
+                 state <=  #1  GNT2;
+				 gnt_1 <= req_0;
+               end
+    GNT2 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT1;
+				 gnt_1 <= req_1;
+               end
+    default : state <=  #1  IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+            .reset(rst),
+            .req_0(a),
+            .req_1(b),
+            .gnt_0(g0),
+            .gnt_1(g1));
+
+endmodule

backends_reviewed/write_firrtl/top_inout_port.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	inout reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[0:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends_reviewed/write_firrtl/top_logic.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg A1,cout1;
+ reg int1,int2,int3;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ~^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+
+always @(posedge x)
+begin
+ if (x == 1'b1) begin
+	int1 = x ^ y;
+ end
+ if (x != 1'b1) begin
+	if (y > 1'b0) begin
+		if (cin < 1'b1) begin
+			int2 = cout1;
+		end
+	end
+ end
+end
+ always @(posedge x)
+ if (x >= 1'b1) begin
+	if (y <= 1'b0) begin
+		int3 = A1;
+	end
+ end
+
+endmodule

backends_reviewed/write_firrtl/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends_reviewed/write_firrtl/top_mul.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign cout =  cin / y;
+assign A =  cin * x;
+
+endmodule

backends_reviewed/write_firrtl/top_negative_edge_ff.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+
+endmodule

backends_reviewed/write_firrtl/top_paramod.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle #(1'b0) u_mid1 (.x(x),.o(o),.y(1'b0));
+middle #(1'b0) u_mid2 (.x(x),.o(o),.y(1'b1));
+middle #(1'b0) u_mid3 (.x(x),.o(o),.y(1'bX));
+middle #(1'b0) u_mid4 (.x(x),.o(o),.y(1'bX));
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+parameter Y = 1'b1;
+
+urtl u_urtl (.x(x),.o(o),.y(Y));
+endmodule
+
+module urtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

backends_reviewed/write_firrtl/top_pow.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout,
+ output signed pow,
+ output signed pow2
+ );
+
+ wire p,n;
+
+assign pow = 2 ** y;
+assign pow2 = 2 ** 2;
+
+assign p =  +x;
+assign n =  -x;
+assign A =  cin * x;
+
+endmodule

backends_reviewed/write_firrtl/top_reduce.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+ wire A1,cout1;
+
+assign A1 =  ~y + &cin;
+assign cout1 = cin ? |y : ^A;
+
+assign A =  A1|y~&cin~^A1;
+assign cout =  cout1&cin~|y;
+
+endmodule

backends_reviewed/write_firrtl/top_reduce_bool.v

+module top(input clk,
+		 input 	       rst,
+		 input [31:0]  in_count,
+		 input 	       in_valid,
+		 output        in_ready,
+
+		 input 	       out_ready,
+		 output        out_valid);
+
+   reg [31:0] 		       r_remaining_count;
+   reg 			       r_valid;
+   reg 			       r_ready;
+
+   assign out_valid = r_valid;
+   assign in_ready = r_ready;
+
+   always @(posedge clk) begin
+      if (rst) begin
+	 r_remaining_count <= 0;
+	 r_valid <= 0;
+	 r_ready <= 0;
+      end else begin
+	 if (r_remaining_count == 0) begin
+	    if (r_ready && in_valid) begin
+	       r_remaining_count <= in_count;
+	       r_valid <= in_count != 0;
+	       r_ready <= 0;
+	    end else begin
+	       r_ready <= 1;
+	       r_valid <= 0;
+	    end
+	 end else begin
+	    r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
+	    r_ready <= 0;
+
+	    if (out_valid && out_ready) begin
+	       r_remaining_count <= r_remaining_count - 1;
+	    end
+	 end
+      end
+   end
+
+endmodule

backends_reviewed/write_firrtl/top_shift.v

+module top
+(
+ input signed x,
+ input signed y,
+ input signed cin,
+
+ output signed A,
+ output signed cout,
+ output signed B,C,
+ output signed D,E
+ );
+
+
+assign A =  y >> x;
+assign cout =  y + A >>> y;
+assign D =  y >> 2;
+assign E =  y + A >>> 2;
+assign {B,C} =  {cout,A} << 1;
+
+endmodule

backends_reviewed/write_firrtl/top_shiftx.v

+
+// VERIFIC-SKIP
+
+module top(a, y);
+
+input signed [4:0] a;
+output signed y;
+
+integer signed i = 0, j = 0;
+reg signed [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule

backends_reviewed/write_firrtl/top_sub.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign cout =  cin % y;
+assign A =  cin - x;
+
+endmodule

backends_reviewed/write_firrtl/write_firrtl.ys

+read_verilog ../top.v
+proc
+write_firrtl firrtl.firrtl

backends_reviewed/write_firrtl/write_firrtl_complex_write_enable_fail.pat

+ERROR: Complex write enable on port 1 on memory top.ram.

backends_reviewed/write_firrtl/write_firrtl_complex_write_enable_fail.ys

+read_verilog ../top_complex_write_enable.v
+proc
+memory
+write_firrtl firrtl.firrtl

backends_reviewed/write_firrtl/write_firrtl_fsm.ys

+read_verilog ../top_fsm.v
+proc
+pmux2shiftx
+clean
+write_firrtl firrtl.firrtl

backends_reviewed/write_firrtl/write_firrtl_fully_selected_fail.pat

+ERROR: This command only operates on fully selected designs!

backends_reviewed/write_firrtl/write_firrtl_fully_selected_fail.ys

+read_verilog ../top_complex_write_enable.v
+proc
+memory_dff -nordff
+memory_collect
+opt_reduce
+clean
+select top22
+write_firrtl firrtl.firrtl

backends_reviewed/write_firrtl/write_firrtl_inout_port_fail.pat

+ERROR: Module port top.q_a is inout!

backends_reviewed/write_firrtl/write_firrtl_inout_port_fail.ys

+read_verilog ../top_inout_port.v
+proc
+memory_dff -nordff
+memory_collect
+opt_reduce
+clean
+write_firrtl firrtl.firrtl

backends_reviewed/write_firrtl/write_firrtl_logic.ys

+read_verilog ../top_logic.v
+proc
+write_firrtl firrtl.firrtl

backends_reviewed/write_firrtl/write_firrtl_mem.pat

+    mem ram:
+      data-type => UInt<8>
+      depth => 64
+      reader => r0
+      reader => r1
+      writer => w0
+      writer => w1
+      read-latency => 0
+      write-latency => 1
+      read-under-write => undefined

backends_reviewed/write_firrtl/write_firrtl_mem.ys

+read_verilog ../top_mem.v
+proc
+memory_dff -nordff
+memory_collect
+opt_reduce
+clean
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_mem_wr.pat

+    mem ram:
+      data-type => UInt<8>
+      depth => 64
+      reader => r0
+      reader => r1
+      writer => w0
+      writer => w1
+      read-latency => 0
+      write-latency => 1
+      read-under-write => undefined

backends_reviewed/write_firrtl/write_firrtl_mem_wr.ys

+read_verilog ../top_mem.v
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_mul.pat

+    _mul____top_mul_v_12_2 <= mul(cin, asUInt(x))
+    _div____top_mul_v_11_1 <= div(cin, asUInt(y))

backends_reviewed/write_firrtl/write_firrtl_mul.ys

+read_verilog ../top_mul.v
+proc
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_negative_edge_ff_fail.pat

+ERROR: Negative edge clock on FF top.$procdff$6.

backends_reviewed/write_firrtl/write_firrtl_negative_edge_ff_fail.ys

+read_verilog ../top_negative_edge_ff.v
+proc
+write_firrtl firrtl.firrtl

backends_reviewed/write_firrtl/write_firrtl_paramod.pat

+_ternary____top_paramod_v_16_2 <= mux(cin, y, x)

backends_reviewed/write_firrtl/write_firrtl_paramod.ys

+read_verilog ../top_paramod.v
+proc
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_pow.pat

+    _pow____top_pow_v_16_2 <= asUInt(bits(shl(SInt(1), 2), 31, 0))
+    _pow____top_pow_v_15_1 <= asUInt(bits(dshl(SInt(1), asUInt(y)), 31, 0))

backends_reviewed/write_firrtl/write_firrtl_pow.ys

+read_verilog -noopt ../top_pow.v
+proc
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_reduce.pat

+    _reduce_xor____top_reduce_v_14_5 <= xorr(pad(A, 1))
+    _reduce_or____top_reduce_v_14_4 <= orr(pad(y, 1))
+    _add____top_reduce_v_13_3 <= add(_not____top_reduce_v_13_1_Y, asUInt(_reduce_and____top_reduce_v_13_2_Y))
+    _reduce_and____top_reduce_v_13_2 <= andr(pad(cin, 1))

backends_reviewed/write_firrtl/write_firrtl_reduce.ys

+read_verilog ../top_reduce.v
+proc
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_reduce_bool.pat

+_ne____top_reduce_bool_v_26_4 <= neq(in_count, UInt<32>(0))

backends_reviewed/write_firrtl/write_firrtl_reduce_bool.ys

+read_verilog ../top_reduce_bool.v
+prep -top top -nordff
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_shift.pat

+    _shl____top_shift_v_18_7 <= bits(shl(cat(cout, A), 1), 1, 0)
+    _sshr____top_shift_v_17_6 <= asUInt(shr(asSInt(_add____top_shift_v_17_5_Y), 2))
+    _add____top_shift_v_17_5 <= asUInt(add(asSInt(y), asSInt(A)))
+    _shr____top_shift_v_16_4 <= asUInt(shr(asUInt(asSInt(y)), 2))
+    _sshr____top_shift_v_15_3 <= asUInt(dshr(asSInt(_add____top_shift_v_15_2_Y), asUInt(y)))
+    _add____top_shift_v_15_2 <= asUInt(add(asSInt(y), asSInt(A)))
+    _shr____top_shift_v_14_1 <= asUInt(dshr(asUInt(asSInt(y)), asUInt(x)))

backends_reviewed/write_firrtl/write_firrtl_shift.ys

+read_verilog ../top_shift.v
+proc
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_shiftx.pat

+_shiftx____top_shiftx_v_21_107 <= dshr(lut, a)

backends_reviewed/write_firrtl/write_firrtl_shiftx.ys

+read_verilog ../top_shiftx.v
+proc
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_sub.pat

+    _sub____top_sub_v_12_2 <= asUInt(sub(cin, asUInt(x)))
+    _mod____top_sub_v_11_1 <= rem(cin, asUInt(y))

backends_reviewed/write_firrtl/write_firrtl_sub.ys

+read_verilog ../top_sub.v
+proc
+write_firrtl result.out

backends_reviewed/write_firrtl/write_firrtl_unclocked_write_port_fail.pat

+ERROR: Unclocked write port 0 on memory top.ram.

backends_reviewed/write_firrtl/write_firrtl_unclocked_write_port_fail.ys

+read_verilog ../top_mem.v
+
+memory
+proc
+write_firrtl firrtl.firrtl
+write_verilog synth.v

backends_reviewed/write_ilang/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+
+ initial begin
+    B = 0;
+ end
+
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+
+always @(negedge clk) begin
+    if (x || y && z)
+        A <=  x & z;
+end
+
+endmodule

backends_reviewed/write_ilang/top_fsm.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

backends_reviewed/write_ilang/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

backends_reviewed/write_ilang/top_mux.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

backends_reviewed/write_ilang/top_tri.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;
+    output [1:0] o;
+
+    wire [1:0] io;
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? en : 1'bZ;
+
+    assign o = io;
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

backends_reviewed/write_ilang/write_ilang.ys

+read_verilog ../top.v
+write_ilang ilang.ilang
+proc
+dump -o file.il
+write_ilang result.out
+dump -n -o file1.il
+design -reset
+read_ilang result.out

backends_reviewed/write_ilang/write_ilang_error_fail.pat

+ERROR: Can't open file `tt/file1.il' for writing: No such file or directory

backends_reviewed/write_ilang/write_ilang_error_fail.ys

+read_verilog ../top.v
+write_ilang ilang.ilang
+proc
+dump -o file.il
+write_ilang ilang.ilang
+dump -n -o tt/file1.il
+synth

backends_reviewed/write_ilang/write_ilang_fsm.ys

+read_verilog ../top_fsm.v
+write_ilang ilang.ilang
+proc
+dump -o file.il
+write_ilang result.out
+dump -n -o file1.il
+design -reset
+read_ilang result.out

backends_reviewed/write_ilang/write_ilang_mem.ys

+read_verilog ../top_mem.v
+write_ilang result2.out
+proc
+write_ilang result1.out
+memory
+dump -o file.il
+write_ilang result.out
+dump -n -o file1.il
+design -reset
+read_ilang result.out

backends_reviewed/write_ilang/write_ilang_mux.ys

+read_verilog ../top_mux.v
+write_ilang ilang.ilang
+proc
+dump -o file.il
+write_ilang result.out
+dump -n -o file1.il
+design -reset
+read_ilang result.out

backends_reviewed/write_ilang/write_ilang_selected.ys

+read_verilog ../top.v
+write_ilang -selected ilang.ilang
+proc
+dump -a file.il
+write_ilang -selected ilang.ilang
+dump -m -a file1.il
+design -reset
+read_ilang ilang.ilang

backends_reviewed/write_ilang/write_ilang_tri.ys

+read_verilog ../top_tri.v
+write_ilang ilang.ilang
+proc
+dump -o file.il
+write_ilang result.out
+dump -n -o file1.il
+design -reset
+read_ilang result.out