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lvzhengyang
yosys-tests
Commits
13cc6608
Commit
13cc6608
authored
Jul 06, 2020
by
Miodrag Milanovic
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Update test according to latest changes
parent
14087ec4
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4 changed files
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12 additions
and
29 deletions
+12
-29
architecture/synth_ecp5/ecp5_ffinit.ys
+0
-19
architecture/synth_ecp5/synth_ecp5_wide_ffs.ys
+1
-1
architecture/synth_ecp5/top_wide_ffs.v
+1
-1
architecture/synth_gowin/synth_gowin_nobram.ys
+10
-8
No files found.
architecture/synth_ecp5/ecp5_ffinit.ys
deleted
100644 → 0
View file @
14087ec4
read_verilog ../top.v
read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v
proc
flatten
tribuf -logic
deminout
synth -run coarse
memory_bram -rules +/ecp5/lutrams.txt
techmap -map +/ecp5/brams_map.v
opt -fast -mux_undef -undriven -fine
techmap -map +/techmap.v -map +/ecp5/arith_map.v
abc -dff
opt -fast -mux_undef -undriven -fine
dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*
techmap -D NO_LUT -map +/ecp5/cells_map.v
opt_expr -mux_undef
simplemap
ecp5_ffinit
write_verilog synth.v
architecture/synth_ecp5/synth_ecp5_wide_ffs.ys
View file @
13cc6608
...
@@ -44,6 +44,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
...
@@ -44,6 +44,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd dffsr # Constrain all select calls below inside the top module
cd dffsr # Constrain all select calls below inside the top module
stat
stat
select -assert-count 4 t:TRELLIS_FF
select -assert-count 4 t:TRELLIS_FF
select -assert-count
5
t:LUT4
select -assert-count
4
t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
write_verilog synth.v
write_verilog synth.v
architecture/synth_ecp5/top_wide_ffs.v
View file @
13cc6608
...
@@ -17,7 +17,7 @@ module adff
...
@@ -17,7 +17,7 @@ module adff
end
end
always
@
(
posedge
clk
,
posedge
clr
)
always
@
(
posedge
clk
,
posedge
clr
)
if
(
clr
)
if
(
clr
)
q
<=
4'b0
11
0
;
q
<=
4'b0
00
0
;
else
else
q
<=
d
;
q
<=
d
;
endmodule
endmodule
...
...
architecture/synth_gowin/synth_gowin_nobram.ys
View file @
13cc6608
...
@@ -12,14 +12,16 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
...
@@ -12,14 +12,16 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
design -load postopt
design -load postopt
cd top
cd top
stat
stat
select -assert-count 3
5
t:DFF
select -assert-count 3
6
t:DFF
select -assert-count 16 t:IBUF
select -assert-count 16 t:IBUF
select -assert-count 32 t:LUT1
select -assert-count 4 t:LUT2
select -assert-count 27 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 12 t:LUT3
select -assert-count 72 t:LUT4
select -assert-count 32 t:MUX2_LUT5
select -assert-count 64 t:MUX2_LUT5
select -assert-count 16 t:MUX2_LUT6
select -assert-count 32 t:MUX2_LUT6
select -assert-count 8 t:MUX2_LUT7
select -assert-count 16 t:MUX2_LUT7
select -assert-count 8 t:MUX2_LUT8
select -assert-count 8 t:OBUF
select -assert-count 8 t:OBUF
select -assert-count 8 t:RAM16S4
select -assert-count 8 t:RAM16S4
select -assert-none t:DFF t:IBUF t:LUT1 t:LUT2 t:LUT3 t:OBUF t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:RAM16S4 %% t:* %D
select -assert-count 1 t:VCC
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:RAM16S4 t:VCC %% t:* %D
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