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yosys-tests
Commit 0d34ab09 by SergeyDegtyar
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Remove old 'architecture' tests.

parent 73abab3b
Showing with 1 additions and 747 deletions
Makefile
SUBDIRS := architecture architecture_reviewed backends bigsim equiv frontends misc regression simple yosys SUBDIRS := architecture_reviewed backends bigsim equiv frontends misc regression simple yosys
ifeq ($(VERIFIC),1) ifeq ($(VERIFIC),1)
export VERIFIC=1 export VERIFIC=1
......
architecture/common.v deleted 100644 → 0
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
architecture/ice40_wrapcarry/testbench.v deleted 100644 → 0
module testbench;
reg [7:0] in;
wire [3:0] outA,outB;
wire [3:0] poutA,poutB;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[3:0]),
.y(in[7:4]),
.A(outA),
.B(outB)
);
assign poutB = in[3:0] / in[7:4];
check_comb div_test(in[7:4], outB, poutB);
endmodule
module check_comb(input [3:0] div, input [3:0] test, input [3:0] pat);
always @*
begin
#1;
if (div != 4'b0000)
if (test !== pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
$stop;
end
end
endmodule
architecture/ice40_wrapcarry/top.v deleted 100644 → 0
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign B = x / y;
endmodule
architecture/ice40_wrapcarry_adders/testbench.v deleted 100644 → 0
module testbench;
reg [31:0] in;
wire [15:0] outA,outB;
wire [15:0] poutA,poutB;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[15:0]),
.y(in[31:16]),
.A(outA),
.B(outB)
);
assign poutA = in[15:0] + in[31:16];
assign poutB = in[15:0] - in[31:16];
check_comb add_test(outA, poutA);
check_comb sub_test(outB, poutB);
assert_comb sub0_test(outB[2], poutB[2]);
endmodule
module check_comb(input [15:0] test, input [15:0] pat);
always @*
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
$stop;
end
end
endmodule
architecture/ice40_wrapcarry_adders/top.v deleted 100644 → 0
module top
(
input [15:0] x,
input [15:0] y,
output [15:0] A,
output [15:0] B
);
assign A = x + y;
assign B = x - y;
endmodule
architecture/run.sh deleted 100644 → 0
#!/bin/bash
set -x
test -d $1
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
# cases where 'syntax error' or other errors are expected
if echo "$1" | grep ".*_error"; then
expected_string=""
# Change checked string for check other errors
if echo "$2" | grep ".*_fully_selected"; then
expected_string="ERROR: This command only operates on fully selected designs!"
elif [ "$2" = "synth_greenpak4_invalid_part" ]; then
expected_string="ERROR: Invalid part name: "
elif [ "$2" = "synth_intel_invalid_family" ]; then
expected_string="ERROR: Invalid or no family specified:"
elif [ "$2" = "synth_xilinx_invalid_arch" ]; then
expected_string="ERROR: Invalid Xilinx -family setting: "
elif [ "$2" = "synth_xilinx_widemux_1" ]; then
expected_string="ERROR: -widemux value must be 0 or >= 2."
elif [ "$2" = "synth_xilinx_abc9_retime" ]; then
expected_string="ERROR: -retime option not currently compatible with -abc9!"
elif [ "$2" = "synth_ice40_abc9_retime" ]; then
expected_string="ERROR: -retime option not currently compatible with -abc9!"
elif [ "$2" = "synth_ice40_device_unknown" ]; then
expected_string="ERROR: Invalid or no device specified: "
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo FAIL > ${1}_${2}.status
else
if grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
fi
else
if [ -f ../run-test.sh ]; then
../run-test.sh
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
touch .stamp
exit
else
test -f scripts/$2.ys
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
fi
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
TECHLIBS_PREFIX=../../../../../techlibs
else
COMMON_PREFIX=/usr/local/share/yosys
TECHLIBS_PREFIX=/usr/local/share/yosys
fi
if [ "$1" = "synth_ecp5" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
elif [ "$1" = "synth_ecp5_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
elif [ "$1" = "synth_achronix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/achronix/speedster22i/cells_sim.v
elif [ "$1" = "synth_anlogic" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fsm" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v $TECHLIBS_PREFIX/anlogic/eagle_bb.v
elif [ "$1" = "synth_coolrunner2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
elif [ "$1" = "synth_coolrunner2_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
elif [ "$1" = "synth_gowin" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
elif [ "$1" = "synth_gowin_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
elif [ "$1" = "synth_ice40" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "ice40_wrapcarry" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v $TECHLIBS_PREFIX/ice40/abc9_model.v
elif [ "$1" = "ice40_wrapcarry_adders" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v $TECHLIBS_PREFIX/ice40/abc9_model.v
elif [ "$1" = "synth_intel" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
elif [ "$1" = "synth_intel_a10gx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/a10gx/cells_sim.v
elif [ "$1" = "synth_intel_cycloneiv" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneiv/cells_sim.v
elif [ "$1" = "synth_intel_cycloneive" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneive/cells_sim.v
elif [ "$1" = "synth_intel_cyclone10" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclone10/cells_sim.v
elif [ "$1" = "synth_intel_cyclonev" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclonev/cells_sim.v
elif [ "$1" = "synth_sf2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
elif [ "$1" = "xilinx_srl" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_greenpak4_dffs_r" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_efinix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
elif [ "$1" = "synth_efinix_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
elif [ "$1" = "xilinx_ug901_synthesis_examples" ] || \
[ "$1" = "synth_xilinx_dsp_cov" ]; then
:
else
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
fi
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if [ "$1" = "xilinx_ug901_synthesis_examples" ] || \
[ "$1" = "synth_xilinx_dsp_cov" ]; then
echo PASS > ${1}_${2}.status
else
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
fi
fi
touch .stamp
architecture/scripts/anlogic_determine_init_eqn.ys deleted 100644 → 0
read_verilog ../top.v
read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v
proc
flatten
tribuf -logic
deminout
synth -run coarse
memory_bram -rules +/anlogic/drams.txt
techmap -map +/anlogic/drams_map.v
anlogic_determine_init
opt -fast -mux_undef -undriven -fine
memory_map
opt -undriven -fine
techmap -map +/techmap.v -map +/anlogic/arith_map.v
dffsr2dff
techmap -D NO_LUT -map +/anlogic/cells_map.v
dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit
opt_expr -mux_undef
simplemap
abc -lut 5
clean
techmap -map +/anlogic/cells_map.v
clean
anlogic_eqn
write_verilog synth.v
architecture/scripts/ecp5_ffinit.ys deleted 100644 → 0
read_verilog ../top.v
read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v
proc
flatten
tribuf -logic
deminout
synth -run coarse
memory_bram -rules +/ecp5/bram.txt
techmap -map +/ecp5/brams_map.v
opt -fast -mux_undef -undriven -fine
techmap -map +/techmap.v -map +/ecp5/arith_map.v
abc -dff
opt -fast -mux_undef -undriven -fine
dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
techmap -D NO_LUT -map +/ecp5/cells_map.v
opt_expr -mux_undef
simplemap
ecp5_ffinit
write_verilog synth.v
architecture/scripts/ice40_wrapcarry.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40
ice40_wrapcarry
write_verilog synth.v
architecture/scripts/ice40_wrapcarry_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40
ice40_wrapcarry top
write_verilog synth.v
architecture/scripts/synth_achronix.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix
write_verilog synth.v
architecture/scripts/synth_achronix_fully_selected.ys deleted 100644 → 0
read_verilog ../top.v
select top2
synth_achronix
write_verilog synth.v
architecture/scripts/synth_achronix_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -noflatten
write_verilog synth.v
architecture/scripts/synth_achronix_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -retime
write_verilog synth.v
architecture/scripts/synth_achronix_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -run begin:vout
write_verilog synth.v
architecture/scripts/synth_achronix_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -top top
write_verilog synth.v
architecture/scripts/synth_achronix_vout.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -vout vout.v
write_verilog synth.v
architecture/scripts/synth_anlogic.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic
write_verilog synth.v
architecture/scripts/synth_anlogic_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_anlogic_fully_selected.ys deleted 100644 → 0
read_verilog ../top.v
select dffe
synth_anlogic
write_verilog synth.v
architecture/scripts/synth_anlogic_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -json json.json
write_verilog synth.v
architecture/scripts/synth_anlogic_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -noflatten
write_verilog synth.v
architecture/scripts/synth_anlogic_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -retime
write_verilog synth.v
architecture/scripts/synth_anlogic_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -run begin:json
write_verilog synth.v
architecture/scripts/synth_anlogic_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -top top
write_verilog synth.v
architecture/scripts/synth_coolrunner2.ys deleted 100644 → 0
read_verilog ../top.v
synth_coolrunner2
write_verilog synth.v
architecture/scripts/synth_coolrunner2_fully_selected.ys deleted 100644 → 0
read_verilog ../top.v
select dffe
synth_coolrunner2
write_verilog synth.v
architecture/scripts/synth_coolrunner2_mem.ys deleted 100644 → 0
read_verilog ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/SimDTM.v
#
synth_coolrunner2
write_verilog synth.v
architecture/scripts/synth_coolrunner2_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_coolrunner2 -noflatten
write_verilog synth.v
architecture/scripts/synth_coolrunner2_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_coolrunner2 -retime
write_verilog synth.v
architecture/scripts/synth_coolrunner2_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_coolrunner2 -run begin:json
write_verilog synth.v
architecture/scripts/synth_coolrunner2_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_coolrunner2 -top top
write_verilog synth.v
architecture/scripts/synth_coolrunner2_vlog.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic -vlog vlog.v
write_verilog synth.v
architecture/scripts/synth_coolrunner2_vout.ys deleted 100644 → 0
read_verilog ../top.v
synth_coolrunner2 -json json.json
write_verilog synth.v
architecture/scripts/synth_easic.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic
write_verilog synth.v
architecture/scripts/synth_easic_etools.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic -etools
write_verilog synth.v
architecture/scripts/synth_easic_fully_selected.ys deleted 100644 → 0
read_verilog ../top.v
select dffe
synth_easic
write_verilog synth.v
architecture/scripts/synth_easic_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic -noflatten
write_verilog synth.v
architecture/scripts/synth_easic_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic -retime
write_verilog synth.v
architecture/scripts/synth_easic_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic -run begin:vlog
write_verilog synth.v
architecture/scripts/synth_easic_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic -top top
write_verilog synth.v
architecture/scripts/synth_ecp5.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5
write_verilog synth.v
architecture/scripts/synth_ecp5_abc2.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -abc2
write_verilog synth.v
architecture/scripts/synth_ecp5_abc9.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -abc9
write_verilog synth.v
architecture/scripts/synth_ecp5_abc9_nowidelut.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -abc9 -nowidelut
write_verilog synth.v
architecture/scripts/synth_ecp5_blif.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -blif blif.blif
write_verilog synth.v
architecture/scripts/synth_ecp5_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_ecp5_flatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -flatten
write_verilog synth.v
architecture/scripts/synth_ecp5_fully_selected.ys deleted 100644 → 0
read_verilog ../top.v
select dffe
synth_ecp5
write_verilog synth.v
architecture/scripts/synth_ecp5_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -json json.json
write_verilog synth.v
architecture/scripts/synth_ecp5_nobram.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nobram
write_verilog synth.v
architecture/scripts/synth_ecp5_noccu2.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -noccu2
write_verilog synth.v
architecture/scripts/synth_ecp5_nodffe.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nodffe
write_verilog synth.v
architecture/scripts/synth_ecp5_nodram.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nodram
write_verilog synth.v
architecture/scripts/synth_ecp5_nodsp.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nodsp
write_verilog synth.v
architecture/scripts/synth_ecp5_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -noflatten
write_verilog synth.v
architecture/scripts/synth_ecp5_nomux.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nomux
write_verilog synth.v
architecture/scripts/synth_ecp5_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -retime
write_verilog synth.v
architecture/scripts/synth_ecp5_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -run begin:json
write_verilog synth.v
architecture/scripts/synth_ecp5_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -top top
write_verilog synth.v
architecture/scripts/synth_ecp5_vpr.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -vpr
write_verilog synth.v
architecture/scripts/synth_efinix.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix
write_verilog synth.v
architecture/scripts/synth_efinix_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_efinix_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -json json.json
write_verilog synth.v
architecture/scripts/synth_efinix_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -noflatten
write_verilog synth.v
architecture/scripts/synth_efinix_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -retime
write_verilog synth.v
architecture/scripts/synth_efinix_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -run begin:json
write_verilog synth.v
architecture/scripts/synth_efinix_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -top top
write_verilog synth.v
architecture/scripts/synth_gowin.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin
write_verilog synth.v
architecture/scripts/synth_gowin_fully_selected.ys deleted 100644 → 0
read_verilog ../top.v
select top2
synth_gowin
write_verilog synth.v
architecture/scripts/synth_gowin_nobram.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -nobram
write_verilog synth.v
architecture/scripts/synth_gowin_nodffe.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -nodffe
write_verilog synth.v
architecture/scripts/synth_gowin_nodram.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -nodram
write_verilog synth.v
architecture/scripts/synth_gowin_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -noflatten
write_verilog synth.v
architecture/scripts/synth_gowin_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -retime
write_verilog synth.v
architecture/scripts/synth_gowin_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -run begin:vout
write_verilog synth.v
architecture/scripts/synth_gowin_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -top top
write_verilog synth.v
architecture/scripts/synth_gowin_vout.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -vout vout.v
write_verilog synth.v
architecture/scripts/synth_greenpak4.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4
write_verilog synth.v
architecture/scripts/synth_greenpak4_fully_selected.ys deleted 100644 → 0
read_verilog ../top.v
select dffe
synth_greenpak4
write_verilog synth.v
architecture/scripts/synth_greenpak4_invalid_part.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -part ggg
write_verilog synth.v
architecture/scripts/synth_greenpak4_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -json json.json
write_verilog synth.v
architecture/scripts/synth_greenpak4_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -noflatten
write_verilog synth.v
architecture/scripts/synth_greenpak4_part140.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -part SLG46140V
write_verilog synth.v
architecture/scripts/synth_greenpak4_part620.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -part SLG46620V
write_verilog synth.v
architecture/scripts/synth_greenpak4_part621.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -part SLG46621V
write_verilog synth.v
architecture/scripts/synth_greenpak4_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -retime
write_verilog synth.v
architecture/scripts/synth_greenpak4_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -run begin:json
write_verilog synth.v
architecture/scripts/synth_greenpak4_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -top top
write_verilog synth.v
architecture/scripts/synth_ice40.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40
write_verilog synth.v
architecture/scripts/synth_ice40_abc2.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -abc2
write_verilog synth.v
architecture/scripts/synth_ice40_abc9.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -abc9
ice40_opt
write_verilog synth.v
architecture/scripts/synth_ice40_abc9_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -abc9 -retime
write_verilog synth.v
architecture/scripts/synth_ice40_blif.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -blif blif.blif
write_verilog synth.v
architecture/scripts/synth_ice40_device_hx.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -device hx
write_verilog synth.v
architecture/scripts/synth_ice40_device_lp.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -device lp
write_verilog synth.v
architecture/scripts/synth_ice40_device_u.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -device u
write_verilog synth.v
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