Merge remote-tracking branch 'origin/master' into xc7srl

architecture/Makefile

@@ -30,7 +30,7 @@ $(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top
 $(eval $(call template,synth_coolrunner2_fulladder,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
 
 #easic - issue #920
-#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
+$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
 
 #ecp5
 $(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
@@ -49,10 +49,7 @@ $(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ic
 $(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_noiopads synth_intel_nobram synth_intel_max10 ))
 $(eval $(call template,synth_intel_cycloneiv,synth_intel_cycloneiv  ))
 $(eval $(call template,synth_intel_cycloneive,synth_intel_cycloneive   ))
-
-# - issue #921
-#../../../../../techlibs/intel/cyclonev/cells_sim.v:88: error: Unable to bind wire/reg/memory `upper_mask_value' in `testbench.uut._05_.lut5'
-#$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
+$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
 $(eval $(call template,synth_intel_cyclone10,synth_intel_cyclone10 ))
 $(eval $(call template,synth_intel_a10gx ,synth_intel_a10gx ))
 

architecture/run.sh

 #!/bin/bash
 
-set -ex
+set -x
 test -d $1
 test -f scripts/$2.ys
 
@@ -8,51 +8,66 @@ rm -rf $1/work_$2
 mkdir $1/work_$2
 cd $1/work_$2
 
+touch .start
+
 if [ -f ../Makefile ]; then
     make -C ..
 else
     yosys -ql yosys.log ../../scripts/$2.ys
 fi
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
+if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+    COMMON_PREFIX=../../../../../techlibs/common
+    TECHLIBS_PREFIX=../../../../../techlibs
+else
+    COMMON_PREFIX=/usr/local/share/yosys
+    TECHLIBS_PREFIX=/usr/local/share/yosys
+fi
+
 if [ "$1" = "synth_ecp5" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
 elif [ "$1" = "synth_ecp5_wide_ffs" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
 elif [ "$1" = "synth_achronix" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/achronix/speedster22i/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/achronix/speedster22i/cells_sim.v
 elif [ "$1" = "synth_anlogic" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
 elif [ "$1" = "synth_anlogic_fulladder" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
 elif [ "$1" = "synth_anlogic_mem" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v  ../../../../../techlibs/anlogic/eagle_bb.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v  $TECHLIBS_PREFIX/anlogic/eagle_bb.v
 elif [ "$1" = "synth_coolrunner2" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
 elif [ "$1" = "synth_coolrunner2_fulladder" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
 elif [ "$1" = "synth_gowin" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
 elif [ "$1" = "synth_gowin_mem" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
 elif [ "$1" = "synth_ice40" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 elif [ "$1" = "synth_ice40_mem" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 elif [ "$1" = "synth_ice40_wide_ffs" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 elif [ "$1" = "synth_intel" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/max10/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
 elif [ "$1" = "synth_intel_a10gx" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/a10gx/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/a10gx/cells_sim.v
 elif [ "$1" = "synth_intel_cycloneiv" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneiv/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneiv/cells_sim.v
 elif [ "$1" = "synth_intel_cycloneive" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneive/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneive/cells_sim.v
 elif [ "$1" = "synth_intel_cyclone10" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclone10/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclone10/cells_sim.v
 elif [ "$1" = "synth_intel_cyclonev" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclonev/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclonev/cells_sim.v
 elif [ "$1" = "synth_sf2" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/sf2/cells_sim.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
 elif [ "$1" = "synth_xilinx" ]; then
     iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
 elif [ "$1" = "synth_xilinx_srl" ]; then
@@ -62,21 +77,27 @@ elif [ "$1" = "synth_xilinx_srl" ]; then
         echo pass > ${1}_${2}.status
     fi
     exit
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
 elif [ "$1" = "synth_greenpak4" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
 elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
 else
-    iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
+    iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
+fi
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
 fi
 
 if ! vvp -N testbench > testbench.log 2>&1; then
 	grep 'ERROR' testbench.log
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 else
-	echo pass > ${1}_${2}.status
+	echo PASS > ${1}_${2}.status
 fi
 
 touch .stamp

architecture/synth_anlogic/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
 

architecture/synth_anlogic/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG
 			q <= d;

architecture/synth_ecp5/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ecp5/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_gowin_mem/testbench.v

@@ -22,30 +22,11 @@ module testbench;
 	reg mem_init = 0;
 
     top uut (
-    data_a[0],
-    data_a[1],
-    data_a[2],
-    data_a[3],
-    data_a[4],
-    data_a[5],
-    data_a[6],
-    data_a[7],
-	addr_a[0],
-	addr_a[1],
-	addr_a[2],
-	addr_a[3],
-	addr_a[4],
-	addr_a[5],
+        data_a,
+	addr_a,
 	we_a,
 	clk,
-	q_a[0],
-	q_a[1],
-	q_a[2],
-	q_a[3],
-	q_a[4],
-	q_a[5],
-	q_a[6],
-	q_a[7]
+	q_a
     );
 
     always @(posedge clk) begin

architecture/synth_greenpak4/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_greenpak4/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_ice40/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ice40/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_xilinx/testbench.v

@@ -64,7 +64,7 @@ module testbench;
 		else
             adffn <= dinA[0];
 
-    always @( posedge clk, posedge dinA[2] )
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_xilinx/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

backends/Makefile

@@ -38,7 +38,7 @@ $(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
 $(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
 
 #write_firrtl
-$(eval $(call template,write_firrtl,write_firrtl write_firrtl))
+$(eval $(call template,write_firrtl,write_firrtl))
 #write_firrtl_mem_wr - issue #938
 #terminate called after throwing an instance of 'std::out_of_range'
 #  what():  dict::at()
@@ -48,6 +48,7 @@ $(eval $(call template,write_firrtl_logic,write_firrtl ))
 $(eval $(call template,write_firrtl_reduce,write_firrtl ))
 $(eval $(call template,write_firrtl_shift,write_firrtl ))
 $(eval $(call template,write_firrtl_shiftx,write_firrtl ))
+$(eval $(call template,write_firrtl_paramod,write_firrtl))
 
 #write_ilang
 $(eval $(call template,write_ilang,write_ilang write_ilang_selected))

backends/run.sh

 #!/bin/bash
 
-set -ex
+set -x
 test -d $1
 test -f scripts/$2.ys
 
@@ -8,17 +8,36 @@ rm -rf $1/work_$2
 mkdir $1/work_$2
 cd $1/work_$2
 
+touch .start
+
 yosys -ql yosys.log ../../scripts/$2.ys
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 sed -i 's/reg =/dummy =/' ./synth.v
-iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
+
+if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+    COMMON_PREFIX=../../../../../techlibs/common
+else
+    COMMON_PREFIX=/usr/local/share/yosys
+fi
+
+iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 
 if ! vvp -N testbench > testbench.log 2>&1; then
 	grep 'ERROR' testbench.log
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 else
-	echo pass > ${1}_${2}.status
+	echo PASS > ${1}_${2}.status
 fi
 
 touch .stamp

backends/scripts/write_firrtl.ys

 read_verilog ../top.v
 proc
 write_firrtl firrtl.firrtl
+synth
+write_firrtl firrtl2.firrtl
 write_verilog synth.v

backends/write_blif/top.v

@@ -45,4 +45,7 @@ endmodule
  input clk;
 
  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
 endmodule

backends/write_edif/top.v

@@ -8,6 +8,8 @@ module top
  output reg cout
  );
 
+ wire bb_out;
+
  initial begin
     A = 0;
     cout = 0;
@@ -24,12 +26,16 @@ end
 assign {cout,A} =  cin - y * x;
 `endif
 
-bb ubb (cin,y,x);
+bb ubb (cin,y,x,bb_out);
 
 endmodule
 
-(* black_box *) module bb(in1, in2, clk);
+(* black_box *) module bb(in1, in2, clk, out1);
  input in1;
  input in2;
  input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
 endmodule

backends/write_firrtl_paramod/testbench.v

+module middle_tb
+(
+	input x,
+	input y,
+	output o
+);
+
+parameter Y = 1'b1;
+
+urtl_tb u_urtl (.x(x),.o(o),.y(Y));
+endmodule
+
+module urtl_tb
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module testbench;
+    reg [0:2] in;
+
+	reg patt_A = 1'bX;
+	wire patt_cout;
+	wire cout,o;
+    wire A;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(A),
+	.cout(cout)
+	);
+
+	always @(posedge in[2])
+	patt_A <= o;
+
+assign pattcout =  in[2]? in[1] : in[0];
+
+middle_tb #(1'b0) u_mid1 (.x(in[0]),.o(o),.y(1'b0));
+middle_tb #(1'b0) u_mid2 (.x(in[0]),.o(o),.y(1'b1));
+middle_tb #(1'b0) u_mid3 (.x(in[0]),.o(o),.y(1'bX));
+middle_tb #(1'b0) u_mid4 (.x(in[0]),.o(o),.y(1'bX));
+
+	assert_comb out_test(.A(patt_A), .B(A));
+
+endmodule

backends/write_firrtl_paramod/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle #(1'b0) u_mid1 (.x(x),.o(o),.y(1'b0));
+middle #(1'b0) u_mid2 (.x(x),.o(o),.y(1'b1));
+middle #(1'b0) u_mid3 (.x(x),.o(o),.y(1'bX));
+middle #(1'b0) u_mid4 (.x(x),.o(o),.y(1'bX));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+parameter Y = 1'b1;
+
+urtl u_urtl (.x(x),.o(o),.y(Y));
+endmodule
+
+module urtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

bigsim/run.sh

 #!/bin/bash
 
-set -ex
+set -x
 source $1/config
 mkdir $1/work_$2
 cd $1/work_$2
 
+touch .start
+
 iverilog_cmd="iverilog -o sim -s testbench -I../rtl -I../sim"
 
 rtl_files=""
@@ -14,6 +16,7 @@ done
 
 case "$2" in
 	sim)
+		touch ../../.start
 		iverilog_cmd="$iverilog_cmd $rtl_files"
 		;;
 	falsify)
@@ -36,18 +39,28 @@ for fn in $SIM; do
 	iverilog_cmd="$iverilog_cmd ../sim/$fn"
 done
 $iverilog_cmd
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 
 vvp -N sim | pv -l > output.txt
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 
 if [ "$2" = "falsify" ]; then
 	if cmp output.txt ../work_sim/output.txt; then
 		echo FAIL > ../../${1}_${2}.status
 	else
-		echo pass > ../../${1}_${2}.status
+		echo PASS > ../../${1}_${2}.status
 	fi
 elif [ "$2" != "sim" ]; then
 	if cmp output.txt ../work_sim/output.txt; then
-		echo pass > ../../${1}_${2}.status
+		echo PASS > ../../${1}_${2}.status
 	else
 		echo FAIL > ../../${1}_${2}.status
 	fi

equiv/Makefile

@@ -47,7 +47,7 @@ $(eval $(call template,equiv_mark,equiv_mark ))
 $(eval $(call template,equiv_induct,equiv_induct equiv_induct_undef equiv_induct_seq ))
 
 #equiv_add
-#$(eval $(call template,equiv_add,equiv_add equiv_add_try ))
+$(eval $(call template,equiv_add,equiv_add equiv_add_try ))
 
 #equiv_opt
 $(eval $(call template,equiv_opt,equiv_opt equiv_opt_run equiv_opt_map))

equiv/run.sh

 #!/bin/bash
 
-set -ex
+set -x
 test -d $1
 test -f scripts/$2.ys
 
@@ -8,17 +8,36 @@ rm -rf $1/work_$2
 mkdir $1/work_$2
 cd $1/work_$2
 
+touch .start
+
 yosys -ql yosys.log ../../scripts/$2.ys
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 sed -i 's/reg =/dummy =/' ./synth.v
-iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
+
+if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+    COMMON_PREFIX=../../../../../techlibs/common
+else
+    COMMON_PREFIX=/usr/local/share/yosys
+fi
+
+iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 
 if ! vvp -N testbench > testbench.log 2>&1; then
 	grep 'ERROR' testbench.log
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 else
-	echo pass > ${1}_${2}.status
+	echo PASS > ${1}_${2}.status
 fi
 
 touch .stamp

frontends/Makefile

@@ -76,4 +76,18 @@ $(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push v
 #verilog_defines
 $(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
 
+#verilog_lexer
+$(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))
+$(eval $(call template,verilog_lexer_package,verilog_lexer))
+$(eval $(call template,verilog_lexer_interface_logic,verilog_lexer))
+$(eval $(call template,verilog_lexer_casez,verilog_lexer))
+$(eval $(call template,verilog_lexer_automatic_task,verilog_lexer))
+$(eval $(call template,verilog_lexer_unique_priority,verilog_lexer))
+$(eval $(call template,verilog_lexer_always_ff_latch,verilog_lexer))
+$(eval $(call template,verilog_lexer_assert_assume_restrict,verilog_lexer_assert))
+#../top.v:88: ERROR: syntax error, unexpected TOK_TYPEDEF
+#$(eval $(call template,verilog_lexer_enum_typedef,verilog_lexer))
+#../top.v:90: ERROR: syntax error, unexpected TOK_SUPPLY1
+#$(eval $(call template,verilog_lexer_supply,verilog_lexer))
+
 .PHONY: all clean

frontends/run.sh

 #!/bin/bash
 
-set -ex
+set -x
 test -d $1
 test -f scripts/$2.ys
 
@@ -8,17 +8,36 @@ rm -rf $1/work_$2
 mkdir $1/work_$2
 cd $1/work_$2
 
+touch .start
+
 yosys -ql yosys.log ../../scripts/$2.ys
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 sed -i 's/reg =/dummy =/' ./synth.v
-iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
+
+if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+    COMMON_PREFIX=../../../../../techlibs/common
+else
+    COMMON_PREFIX=/usr/local/share/yosys
+fi
+
+iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 
 if ! vvp -N testbench > testbench.log 2>&1; then
 	grep 'ERROR' testbench.log
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 else
-	echo pass > ${1}_${2}.status
+	echo PASS > ${1}_${2}.status
 fi
 
 touch .stamp

frontends/scripts/verilog_lexer.ys

+read_verilog -sv ../top.v
+proc
+write_verilog synth.v

frontends/scripts/verilog_lexer_assert.ys

+read_verilog -sv ../top2.v
+design -reset
+read_verilog -sv ../top.v
+proc
+write_verilog synth.v

frontends/scripts/verilog_lexer_sv.ys

+read -sv ../top.sv
+proc
+write_verilog synth.v

frontends/verilog_lexer_always_ff_latch/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_always_ff_latch/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always_ff @(*)
+		Y = (S)? B : A;
+`else
+
+    always_latch @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_lexer_assert_assume_restrict/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out = 0;
+	wire patt_carry_out = 0;
+	wire out = 0;
+    wire carryout = 0;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+    assign    patt_out =  in[1] + in[2];
+    assign    patt_carry_out =  in[1] + patt_out;
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

frontends/verilog_lexer_assert_assume_restrict/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+ input clk,
+
+ output A,
+ output cout
+ );
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+`ifndef BUG
+ assign    A =  y + cin;
+ assign   cout =  y + A;
+
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

frontends/verilog_lexer_assert_assume_restrict/top2.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+ const integer Gsize = 10e2;
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(eventually ASSERT);
+
+//checker request_granted(y,cin);
+	r1: restrict property (y == cin);
+//endchecker : request_granted
+end
+`else
+assign {cout,A} =  cin - y * x;
+
+`endif
+
+endmodule

frontends/verilog_lexer_automatic_task/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_automatic_task/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+task automatic do_things;
+  input [31:0] number_of_things;
+  reg [31:0] tmp_thing;
+endtask
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_lexer_casez/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_casez/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    casez( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   casex( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_lexer_enum_typedef/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_enum_typedef/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+typedef enum {red,blue,green} e_color;
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule
+endmodule

frontends/verilog_lexer_interface_logic/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_interface_logic/top.v

+interface apb_if (input pclk);
+  logic [31:0]    paddr;
+  logic [31:0]    pwdata;
+  logic [31:0]    prdata;
+  logic           penable;
+  logic           pwrite;
+  logic           psel;
+
+  modport TB  (input penable, output psel);
+endinterface
+
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_lexer_package/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_package/top.v

+`resetall
+
+package my_pkg;
+ // typedef enum bit [1:0] { RED, YELLOW, GREEN, RSVD } e_signal;
+/*  typedef struct { bit [3:0] signal_id;
+                     bit       active;
+                     bit [1:0] timeout;
+                   } e_sig_param;
+
+  function common ();
+      $display ("Called from somewhere");
+     endfunction
+
+    task run ();
+    endtask */
+endpackage
+
+{* AAA *}
+//
+
+\
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+    reg a_vect[ 0 +: 8];
+    reg b_vect[ 0 -: 8];
+	//import my_pkg::*;
+`ifndef BUG
+
+     always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_lexer_specify_specparam/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_specify_specparam/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    parameter X = 1;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+specify
+  specparam TRise = 10,
+  TFall = 15;
+  (S => M2) = (TRise, TFall) ;
+endspecify
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_lexer_supply/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_supply/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    casez( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   casex( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+wire y,a,b;
+
+buf (supply1) g1 (y, a);
+buf (supply0) g2 (y, b);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends/verilog_lexer_unique_priority/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [15:0] D = 1;
+    reg [3:0] S = 0;
+    wire M2,M4,M8,M16;
+
+    top uut (
+        .S (S ),
+        .D (D ),
+        .M2 (M2 ),
+        .M4 (M4 ),
+        .M8 (M8 ),
+        .M16 (M16 )
+    );
+    
+    always @(posedge clk) begin
+    //#3;
+	D <= {D[14:0],D[15]};
+    //D <= D <<< 1;
+    S <= S + 1;
+    end
+	
+	assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
+	assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
+	assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
+	assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
+  
+endmodule

frontends/verilog_lexer_unique_priority/top.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+`ifndef BUG
+
+    always @(*)
+		Y = (S)? B : A;
+`else
+
+    always @(*)
+		Y = (~S)? B : A;
+`endif
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+`ifndef BUG
+       2 : Y = D[2];
+`else
+       2 : Y = D[3];
+`endif
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+`ifndef BUG
+       4 : Y = D[4];
+`else
+       4 : Y = D[7];
+`endif
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+wire a,b,c,d,e,f,g,h;
+
+always @(*)
+begin
+	unique case (a)
+	0: b = c;
+	1: b = d;
+	endcase
+
+
+	unique case (g)
+	0: h = c;
+	1: h = d;
+	endcase
+
+	priority case (e)
+	0: f = c;
+	1: f = d;
+	endcase
+end
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

misc/Makefile

@@ -52,13 +52,13 @@ $(eval $(call template,scc_hier_feedback, scc scc_all_cell_types scc_expect scc_
 $(eval $(call template,scatter, scatter ))
 
 #rename
-$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire))
+$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire rename_top_top rename_low))
 
 #qwp
 #qwp_v - exception (issue #923)
 #+ yosys -ql yosys.log ../../scripts/qwp_v.ys
 #run.sh: line 11: 28262 Floating point exception(core dumped) yosys -ql yosys.log ../../scripts/$2.ys
-$(eval $(call template,qwp, qwp qwp_ltr qwp_grid qwp_dump qwp_alpha))
+$(eval $(call template,qwp, qwp qwp_v qwp_ltr qwp_grid qwp_dump qwp_alpha))
 
 #ltp
 $(eval $(call template,ltp, ltp ltp_noff ))
@@ -84,7 +84,7 @@ $(eval $(call template,blackbox, blackbox ))
 
 # - issue #925
 #bugpoint ERROR: No such command: autoidx (type 'help' for a command overview)
-#$(eval $(call template,bugpoint,bugpoint_yosys bugpoint_script bugpoint_grep bugpoint_fast bugpoint_clean bugpoint_modules bugpoint_ports bugpoint_cells bugpoint_connections  ))
+$(eval $(call template,bugpoint,bugpoint_yosys bugpoint_script bugpoint_grep bugpoint_fast bugpoint_clean bugpoint_modules bugpoint_ports bugpoint_cells bugpoint_connections  ))
 
 #chformal
 $(eval $(call template,chformal, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
@@ -100,7 +100,7 @@ $(eval $(call template,connect, connect_nomap_set connect_nomap_unset connect_no
 $(eval $(call template,connwrappers, connwrappers connwrappers_signed connwrappers_unsigned connwrappers_port ))
 
 #plugin
-#$(eval $(call template,plugin, plugin plugin_i plugin_a plugin_l ))
+$(eval $(call template,plugin, plugin plugin_i plugin_a plugin_l ))
 
 #select
 $(eval $(call template,select, select select_all select_add select_add_all select_assert_any select_assert_count select_assert_max select_assert_min select_assert_none select_clear select_count select_del select_list select_module select_none select_read select_set select_write select_add_A_eq select_add_a_eq select_add_A_lesseq select_add_a_lesseq select_add_A_less select_add_a_less select_add_A_moreeq select_add_a_moreeq select_add_A_more select_add_a_more select_add_A select_add_a select_add_c select_add_i select_add_mid select_add_m select_add_n select_add_obj select_add_o select_add_p select_add_r_eq select_add_r_lesseq select_add_r_less select_add_r_moreeq select_add_r_more select_add_r select_add_ss select_add_s select_add_t select_add_w select_add_x ))
@@ -182,5 +182,18 @@ $(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux
 #hilomap
 $(eval $(call template,hilomap, hilomap hilomap_hicell hilomap_locell hilomap_singleton hilomap_hicell_singleton hilomap_locell_singleton hilomap_hicell_locell_singleton))
 
+#cutpoint
+$(eval $(call template,cutpoint, cutpoint cutpoint_undef))
+
+#mutate
+$(eval $(call template,mutate, mutate_list mutate_cnot1 mutate_cnot0 mutate_const1 mutate_const0 mutate_inv mutate_all mutate_list_cfg mutate_list_ctrl mutate_list_none mutate_list_o mutate_list_seed mutate_list_s))
+$(eval $(call template,mutate_mem, mutate_list mutate_all))
+
+#fmconbine
+$(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd))
+
+#pmuxtree
+$(eval $(call template,pmuxtree, pmuxtree))
+
 
 .PHONY: all clean

misc/cutpoint/top.v

+module bb
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+bb u_bb (x,y,cin,A,cout);
+
+endmodule

misc/fmcombine/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid1 (.x(x),.o(o),.y(1'b0));
+middle u_mid2 (.x(x),.o(o),.y(1'b1));
+middle u_mid3 (.x(x),.o(o),.y(1'bX));
+middle u_mid4 (.x(x),.o(o),.y(1'bX));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+urtl u_urtl (.x(x),.o(o),.y(y));
+endmodule
+
+module urtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc/mutate/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+

misc/mutate_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

misc/pmuxtree/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

misc/rename/top.v

@@ -28,6 +28,10 @@ module middle
 	input y,
 	output o
 );
+wire dd;
 
 assign o = x + y;
 endmodule
+
+module low ();
+endmodule

misc/run.sh

 #!/bin/bash
 
-set -ex
+set -x
 test -d $1
 test -f scripts/$2.ys
 
@@ -8,12 +8,19 @@ rm -rf $1/work_$2
 mkdir $1/work_$2
 cd $1/work_$2
 
+touch .start
+
 yosys -ql yosys.log ../../scripts/$2.ys
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 
 if grep 'Assert' result.log || grep 'failed in' result.log || grep 'fail' result.log || grep 'ERROR' result.log; then
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 else
-	echo pass > ${1}_${2}.status
+	echo PASS > ${1}_${2}.status
 fi
 
 touch .stamp

misc/scripts/cutpoint.ys

+read_verilog ../top.v
+tee -o result.log cutpoint top/y top/x top/cout top/A top/cin
+tee -o result.log cutpoint top
+

misc/scripts/cutpoint_undef.ys

+read_verilog ../top.v
+tee -o result.log cutpoint top/y top/x top/cout top/A
+tee -o result.log cutpoint -undef top/cin
+tee -o result.log cutpoint -undef top

misc/scripts/fmcombine.ys

+read_verilog ../top.v
+tee -o result.log fmcombine top u_mid1 u_mid3
+tee -o result.log fmcombine top u_mid2 u_mid4
+tee -o result.log fmcombine top u_mid1_u_mid3 u_mid2_u_mid4
+

misc/scripts/fmcombine_bwd.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -bwd top u_mid1 u_mid2
+

misc/scripts/fmcombine_bwd_fwd.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -bwd -fwd top u_mid1 u_mid2
+

misc/scripts/fmcombine_fwd.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -fwd top u_mid1 u_mid2
+

misc/scripts/fmcombine_nop.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -nop top u_mid1 u_mid2
+

misc/scripts/mutate_all.ys

+read_verilog ../top.v
+mutate -list 512 -o mutate.ys
+script mutate.ys
+
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -ctrlbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
+

misc/scripts/mutate_cnot0.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+
+

misc/scripts/mutate_cnot1.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src top.v:12
+
+
+

misc/scripts/mutate_const0.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+

misc/scripts/mutate_const1.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+
+

misc/scripts/mutate_inv.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+

misc/scripts/mutate_list.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32
+

misc/scripts/mutate_list_cfg.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -cfg weight_cover 1
+
+

misc/scripts/mutate_list_ctrl.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -ctrl A 1 1
+

misc/scripts/mutate_list_none.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -none
+

misc/scripts/mutate_list_o.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -o o.txt
+

misc/scripts/mutate_list_s.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -s s.txt
+

misc/scripts/mutate_list_seed.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -seed 5
+

misc/scripts/pmuxtree.ys

+read_verilog ../top.v
+proc
+tee -o result.log pmuxtree

misc/scripts/rename_low.ys

+read_verilog ../top.v
+synth
+tee -o result.log rename low newlow

misc/scripts/rename_top_top.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log rename top new_top

regression/Makefile

@@ -30,7 +30,8 @@ $(eval $(call template,issue_00041,issue_00041))
 $(eval $(call template,issue_00059,issue_00059))
 
 #issue_00065
-$(eval $(call template,issue_00065,issue_00065))
+# Takes too long
+#$(eval $(call template,issue_00065,issue_00065))
 
 #issue_00067
 $(eval $(call template,issue_00067,issue_00067))
@@ -50,7 +51,7 @@ $(eval $(call template,issue_00081,issue_00081))
 #Parsing Verilog input from `top_fault.v' to AST representation.
 #top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
 #
-#$(eval $(call template,issue_00082,issue_00082))
+$(eval $(call template,issue_00082,issue_00082))
 
 #issue_00083
 #Warning: Deep recursion in AST simplifier.
@@ -58,7 +59,7 @@ $(eval $(call template,issue_00081,issue_00081))
 #run.sh: line 21: 17264 Segmentation fault      (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
 #make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
 #
-#$(eval $(call template,issue_00083,issue_00083))
+$(eval $(call template,issue_00083,issue_00083))
 
 #issue_00084
 $(eval $(call template,issue_00084,issue_00084))
@@ -298,6 +299,7 @@ $(eval $(call template,issue_00763,issue_00763))
 $(eval $(call template,issue_00767,issue_00767))
 
 #issue_00774
+# Takes too long
 #$(eval $(call template,issue_00774,issue_00774))
 
 #issue_00781
@@ -339,7 +341,26 @@ $(eval $(call template,issue_00862,issue_00862))
 #issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
 $(eval $(call template,issue_00865,issue_00865))
 
+#issue_00867
+$(eval $(call template,issue_00867,issue_00867))
+
+#issue_00870
+$(eval $(call template,issue_00870,issue_00870))
+
+#issue_00873
+$(eval $(call template,issue_00873,issue_00873))
+
+#issue_00888
+$(eval $(call template,issue_00888,issue_00888))
+
+#pr_00896
 $(eval $(call template,pr_00896,pr_00896))
 
+#issue_00922
+$(eval $(call template,issue_00922,issue_00922))
+
+#issue_00931
+$(eval $(call template,issue_00931,issue_00931))
+
 
 .PHONY: all clean

regression/issue_00059/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00059/top.v

-module top(b);
+module top(b,c);
 input b;
+output c;
+
+assign c = b;
 endmodule

regression/issue_00067/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00067/top.v

-module top(b);
+module top(b,c);
 input b;
+output c;
+
+assign c = b;
 endmodule

regression/issue_00071/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00071/top.v

-module top(b);
+module top(b,c);
 input b;
+output c;
+
+assign c = b;
 endmodule

regression/issue_00078/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00078/top.v

-module top(b);
+module top(b,c);
 input b;
+output c;
+
+assign c = b;
 endmodule

regression/issue_00081/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00081/top.v

-module top(b);
+module top(b,c);
 input b;
+output c;
+
+assign c = b;
 endmodule

regression/issue_00085/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00085/top.v

-module top(b);
+module top(b,c);
 input b;
+output c;
+
+assign c = b;
 endmodule

regression/issue_00086/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00086/top.v

-module top(b);
+module top(b,c);
 input b;
+output c;
+
+assign c = b;
 endmodule

regression/issue_00088/testbench.v

@@ -13,10 +13,11 @@ module testbench;
 
         $display("OKAY");
     end
-
+	wire c;
 
     top uut (
-        .b (clk )
+        .b (clk ),
+        .c (c)
     );
 
 endmodule

regression/issue_00088/top.v

 parameter X = 2;
 
-module top(b);
+module top(b,c);
 input b;
+output c;
+
 parameter Y = 3;
+
+assign c = b;
 endmodule
 

regression/issue_00870/top.v

+module mux1( select, d, q );
+
+input select;
+input[1:0] d;
+output     q;
+
+wire      q;
+wire      select;
+wire[1:0] d;
+
+assign q = d[select];
+
+endmodule
+
+module top(select, d, q);
+
+input[1:0] select;
+input[1:0] d;
+output     q;
+
+wire      q;
+wire[1:0] select;
+wire[1:0] d;
+
+wire[1:0] q_tmp;
+
+mux1 m1(
+		.select(select[0]),
+		.d(d),
+		.q(q_tmp[0])
+);
+
+mux1 m2(
+		.select(select[1]),
+		.d(d),
+		.q(q_tmp[1])
+);
+
+mux1 m3(
+		.select(select[0]),
+		.d(q_tmp),
+		.q(q)
+);
+
+
+
+endmodule

regression/issue_00873/top.v

+module template (input clk, input d, output reg q);
+parameter neg_clk = 0;
+
+initial q = 1'b1;
+
+generate
+    if (neg_clk) begin
+        always @(negedge clk) q <= d;
+    end
+    else begin
+        always @(posedge clk) q <= d;
+    end
+endgenerate
+endmodule
+
+module top(input clk, input d, output [1:0] q);
+    template #(.neg_clk(1)) neg_clk(clk, d, q[0]);
+    template #(.neg_clk(0)) pos_clk(clk, d, q[1]);
+endmodule