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yosys-tests
Commit 0b74e604 by Eddie Hung
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Merge remote-tracking branch 'origin/master' into xc7srl

parents 3ca96b9a c5f1e079
Showing with 3546 additions and 195 deletions
architecture/Makefile
......@@ -30,7 +30,7 @@ $(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top
$(eval $(call template,synth_coolrunner2_fulladder,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
#easic - issue #920
#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
#ecp5
$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
......@@ -49,10 +49,7 @@ $(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ic
$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_noiopads synth_intel_nobram synth_intel_max10 ))
$(eval $(call template,synth_intel_cycloneiv,synth_intel_cycloneiv ))
$(eval $(call template,synth_intel_cycloneive,synth_intel_cycloneive ))
# - issue #921
#../../../../../techlibs/intel/cyclonev/cells_sim.v:88: error: Unable to bind wire/reg/memory `upper_mask_value' in `testbench.uut._05_.lut5'
#$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
$(eval $(call template,synth_intel_cyclone10,synth_intel_cyclone10 ))
$(eval $(call template,synth_intel_a10gx ,synth_intel_a10gx ))
......
architecture/run.sh
#!/bin/bash
set -ex
set -x
test -d $1
test -f scripts/$2.ys
......@@ -8,51 +8,66 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
if [ -f ../Makefile ]; then
make -C ..
else
yosys -ql yosys.log ../../scripts/$2.ys
fi
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
TECHLIBS_PREFIX=../../../../../techlibs
else
COMMON_PREFIX=/usr/local/share/yosys
TECHLIBS_PREFIX=/usr/local/share/yosys
fi
if [ "$1" = "synth_ecp5" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
elif [ "$1" = "synth_ecp5_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
elif [ "$1" = "synth_achronix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/achronix/speedster22i/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/achronix/speedster22i/cells_sim.v
elif [ "$1" = "synth_anlogic" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/anlogic/cells_sim.v ../../../../../techlibs/anlogic/eagle_bb.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v $TECHLIBS_PREFIX/anlogic/eagle_bb.v
elif [ "$1" = "synth_coolrunner2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
elif [ "$1" = "synth_coolrunner2_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/coolrunner2/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
elif [ "$1" = "synth_gowin" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
elif [ "$1" = "synth_gowin_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/gowin/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
elif [ "$1" = "synth_ice40" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ice40/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_intel" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/max10/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
elif [ "$1" = "synth_intel_a10gx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/a10gx/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/a10gx/cells_sim.v
elif [ "$1" = "synth_intel_cycloneiv" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneiv/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneiv/cells_sim.v
elif [ "$1" = "synth_intel_cycloneive" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cycloneive/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneive/cells_sim.v
elif [ "$1" = "synth_intel_cyclone10" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclone10/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclone10/cells_sim.v
elif [ "$1" = "synth_intel_cyclonev" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/intel/cyclonev/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclonev/cells_sim.v
elif [ "$1" = "synth_sf2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/sf2/cells_sim.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
elif [ "$1" = "synth_xilinx_srl" ]; then
......@@ -62,21 +77,27 @@ elif [ "$1" = "synth_xilinx_srl" ]; then
echo pass > ${1}_${2}.status
fi
exit
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
else
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
fi
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
touch .stamp
architecture/synth_anlogic/testbench.v
......@@ -11,10 +11,10 @@ module testbench;
#5 clk = 0;
end
$display("OKAY");
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
......@@ -30,12 +30,12 @@ module testbench;
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
......@@ -43,7 +43,7 @@ module testbench;
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
......@@ -51,27 +51,27 @@ module testbench;
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_anlogic/top.v
......@@ -5,9 +5,9 @@ module adff
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
`ifndef BUG
q <= 1'b0;
`else
`else
q <= d;
`endif
else
......@@ -21,9 +21,9 @@ module adffn
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
`ifndef BUG
q <= 1'b0;
`else
`else
q <= d;
`endif
else
......@@ -35,11 +35,11 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk)
if ( en )
`ifndef BUG
`ifndef BUG
q <= d;
`else
`else
q <= 1'b0;
`endif
endmodule
......
architecture/synth_ecp5/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
architecture/synth_ecp5/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
......
architecture/synth_gowin_mem/testbench.v
......@@ -22,30 +22,11 @@ module testbench;
reg mem_init = 0;
top uut (
data_a[0],
data_a[1],
data_a[2],
data_a[3],
data_a[4],
data_a[5],
data_a[6],
data_a[7],
addr_a[0],
addr_a[1],
addr_a[2],
addr_a[3],
addr_a[4],
addr_a[5],
data_a,
addr_a,
we_a,
clk,
q_a[0],
q_a[1],
q_a[2],
q_a[3],
q_a[4],
q_a[5],
q_a[6],
q_a[7]
q_a
);
always @(posedge clk) begin
......
architecture/synth_greenpak4/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
......
architecture/synth_greenpak4/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
......
architecture/synth_ice40/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
architecture/synth_ice40/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
architecture/synth_xilinx/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
architecture/synth_xilinx/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
backends/Makefile
......@@ -38,7 +38,7 @@ $(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
#write_firrtl
$(eval $(call template,write_firrtl,write_firrtl write_firrtl))
$(eval $(call template,write_firrtl,write_firrtl))
#write_firrtl_mem_wr - issue #938
#terminate called after throwing an instance of 'std::out_of_range'
# what(): dict::at()
......@@ -48,6 +48,7 @@ $(eval $(call template,write_firrtl_logic,write_firrtl ))
$(eval $(call template,write_firrtl_reduce,write_firrtl ))
$(eval $(call template,write_firrtl_shift,write_firrtl ))
$(eval $(call template,write_firrtl_shiftx,write_firrtl ))
$(eval $(call template,write_firrtl_paramod,write_firrtl))
#write_ilang
$(eval $(call template,write_ilang,write_ilang write_ilang_selected))
......
backends/run.sh
#!/bin/bash
set -ex
set -x
test -d $1
test -f scripts/$2.ys
......@@ -8,17 +8,36 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
sed -i 's/reg =/dummy =/' ./synth.v
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
else
COMMON_PREFIX=/usr/local/share/yosys
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
touch .stamp
backends/scripts/write_firrtl.ys
read_verilog ../top.v
proc
write_firrtl firrtl.firrtl
write_verilog synth.v
synth
write_firrtl firrtl2.firrtl
write_verilog synth.v
backends/write_blif/top.v
......@@ -45,4 +45,7 @@ endmodule
input clk;
output reg out1;
always @(posedge clk)
out1 <= in1 & in2;
endmodule
backends/write_edif/top.v
......@@ -7,7 +7,9 @@ module top
output reg A,
output reg cout
);
wire bb_out;
initial begin
A = 0;
cout = 0;
......@@ -24,12 +26,16 @@ end
assign {cout,A} = cin - y * x;
`endif
bb ubb (cin,y,x);
bb ubb (cin,y,x,bb_out);
endmodule
(* black_box *) module bb(in1, in2, clk);
(* black_box *) module bb(in1, in2, clk, out1);
input in1;
input in2;
input clk;
output reg out1;
always @(posedge clk)
out1 <= in1 & in2;
endmodule
backends/write_firrtl_paramod/testbench.v 0 → 100644
module middle_tb
(
input x,
input y,
output o
);
parameter Y = 1'b1;
urtl_tb u_urtl (.x(x),.o(o),.y(Y));
endmodule
module urtl_tb
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module testbench;
reg [0:2] in;
reg patt_A = 1'bX;
wire patt_cout;
wire cout,o;
wire A;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(A),
.cout(cout)
);
always @(posedge in[2])
patt_A <= o;
assign pattcout = in[2]? in[1] : in[0];
middle_tb #(1'b0) u_mid1 (.x(in[0]),.o(o),.y(1'b0));
middle_tb #(1'b0) u_mid2 (.x(in[0]),.o(o),.y(1'b1));
middle_tb #(1'b0) u_mid3 (.x(in[0]),.o(o),.y(1'bX));
middle_tb #(1'b0) u_mid4 (.x(in[0]),.o(o),.y(1'bX));
assert_comb out_test(.A(patt_A), .B(A));
endmodule
backends/write_firrtl_paramod/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle #(1'b0) u_mid1 (.x(x),.o(o),.y(1'b0));
middle #(1'b0) u_mid2 (.x(x),.o(o),.y(1'b1));
middle #(1'b0) u_mid3 (.x(x),.o(o),.y(1'bX));
middle #(1'b0) u_mid4 (.x(x),.o(o),.y(1'bX));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
parameter Y = 1'b1;
urtl u_urtl (.x(x),.o(o),.y(Y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
bigsim/run.sh
#!/bin/bash
set -ex
set -x
source $1/config
mkdir $1/work_$2
cd $1/work_$2
touch .start
iverilog_cmd="iverilog -o sim -s testbench -I../rtl -I../sim"
rtl_files=""
......@@ -14,6 +16,7 @@ done
case "$2" in
sim)
touch ../../.start
iverilog_cmd="$iverilog_cmd $rtl_files"
;;
falsify)
......@@ -36,18 +39,28 @@ for fn in $SIM; do
iverilog_cmd="$iverilog_cmd ../sim/$fn"
done
$iverilog_cmd
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
vvp -N sim | pv -l > output.txt
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if [ "$2" = "falsify" ]; then
if cmp output.txt ../work_sim/output.txt; then
echo FAIL > ../../${1}_${2}.status
else
echo pass > ../../${1}_${2}.status
echo PASS > ../../${1}_${2}.status
fi
elif [ "$2" != "sim" ]; then
if cmp output.txt ../work_sim/output.txt; then
echo pass > ../../${1}_${2}.status
echo PASS > ../../${1}_${2}.status
else
echo FAIL > ../../${1}_${2}.status
fi
......
equiv/Makefile
......@@ -47,7 +47,7 @@ $(eval $(call template,equiv_mark,equiv_mark ))
$(eval $(call template,equiv_induct,equiv_induct equiv_induct_undef equiv_induct_seq ))
#equiv_add
#$(eval $(call template,equiv_add,equiv_add equiv_add_try ))
$(eval $(call template,equiv_add,equiv_add equiv_add_try ))
#equiv_opt
$(eval $(call template,equiv_opt,equiv_opt equiv_opt_run equiv_opt_map))
......
equiv/run.sh
#!/bin/bash
set -ex
set -x
test -d $1
test -f scripts/$2.ys
......@@ -8,17 +8,36 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
sed -i 's/reg =/dummy =/' ./synth.v
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
else
COMMON_PREFIX=/usr/local/share/yosys
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
touch .stamp
frontends/Makefile
......@@ -76,4 +76,18 @@ $(eval $(call template,verilog_defaults,verilog_defaults verilog_defaults_push v
#verilog_defines
$(eval $(call template,verilog_defines,verilog_defines verilog_defines_val verilog_defines_u verilog_defines_d verilog_defines_u_val))
#verilog_lexer
$(eval $(call template,verilog_lexer_specify_specparam,verilog_lexer))
$(eval $(call template,verilog_lexer_package,verilog_lexer))
$(eval $(call template,verilog_lexer_interface_logic,verilog_lexer))
$(eval $(call template,verilog_lexer_casez,verilog_lexer))
$(eval $(call template,verilog_lexer_automatic_task,verilog_lexer))
$(eval $(call template,verilog_lexer_unique_priority,verilog_lexer))
$(eval $(call template,verilog_lexer_always_ff_latch,verilog_lexer))
$(eval $(call template,verilog_lexer_assert_assume_restrict,verilog_lexer_assert))
#../top.v:88: ERROR: syntax error, unexpected TOK_TYPEDEF
#$(eval $(call template,verilog_lexer_enum_typedef,verilog_lexer))
#../top.v:90: ERROR: syntax error, unexpected TOK_SUPPLY1
#$(eval $(call template,verilog_lexer_supply,verilog_lexer))
.PHONY: all clean
frontends/run.sh
#!/bin/bash
set -ex
set -x
test -d $1
test -f scripts/$2.ys
......@@ -8,17 +8,36 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
sed -i 's/reg =/dummy =/' ./synth.v
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
else
COMMON_PREFIX=/usr/local/share/yosys
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
touch .stamp
frontends/scripts/verilog_lexer.ys 0 → 100644
read_verilog -sv ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_lexer_assert.ys 0 → 100644
read_verilog -sv ../top2.v
design -reset
read_verilog -sv ../top.v
proc
write_verilog synth.v
frontends/scripts/verilog_lexer_sv.ys 0 → 100644
read -sv ../top.sv
proc
write_verilog synth.v
frontends/verilog_lexer_always_ff_latch/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_always_ff_latch/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always_ff @(*)
Y = (S)? B : A;
`else
always_latch @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_assert_assume_restrict/testbench.v 0 → 100644
module testbench;
reg [2:0] in;
wire patt_out = 0;
wire patt_carry_out = 0;
wire out = 0;
wire carryout = 0;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign patt_out = in[1] + in[2];
assign patt_carry_out = in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
frontends/verilog_lexer_assert_assume_restrict/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
input clk,
output A,
output cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/verilog_lexer_assert_assume_restrict/top2.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
const integer Gsize = 10e2;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(eventually ASSERT);
//checker request_granted(y,cin);
r1: restrict property (y == cin);
//endchecker : request_granted
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
frontends/verilog_lexer_automatic_task/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_automatic_task/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
task automatic do_things;
input [31:0] number_of_things;
reg [31:0] tmp_thing;
endtask
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_casez/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_casez/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
casez( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
casex( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_enum_typedef/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_enum_typedef/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
typedef enum {red,blue,green} e_color;
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
endmodule
frontends/verilog_lexer_interface_logic/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_interface_logic/top.v 0 → 100644
interface apb_if (input pclk);
logic [31:0] paddr;
logic [31:0] pwdata;
logic [31:0] prdata;
logic penable;
logic pwrite;
logic psel;
modport TB (input penable, output psel);
endinterface
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_package/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_package/top.v 0 → 100644
`resetall
package my_pkg;
// typedef enum bit [1:0] { RED, YELLOW, GREEN, RSVD } e_signal;
/* typedef struct { bit [3:0] signal_id;
bit active;
bit [1:0] timeout;
} e_sig_param;
function common ();
$display ("Called from somewhere");
endfunction
task run ();
endtask */
endpackage
{* AAA *}
//
\
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
reg a_vect[ 0 +: 8];
reg b_vect[ 0 -: 8];
//import my_pkg::*;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_specify_specparam/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_specify_specparam/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
parameter X = 1;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
specify
specparam TRise = 10,
TFall = 15;
(S => M2) = (TRise, TFall) ;
endspecify
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_supply/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_supply/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
casez( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
casex( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire y,a,b;
buf (supply1) g1 (y, a);
buf (supply0) g2 (y, b);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
frontends/verilog_lexer_unique_priority/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
frontends/verilog_lexer_unique_priority/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire a,b,c,d,e,f,g,h;
always @(*)
begin
unique case (a)
0: b = c;
1: b = d;
endcase
unique case (g)
0: h = c;
1: h = d;
endcase
priority case (e)
0: f = c;
1: f = d;
endcase
end
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
misc/Makefile
......@@ -52,13 +52,13 @@ $(eval $(call template,scc_hier_feedback, scc scc_all_cell_types scc_expect scc_
$(eval $(call template,scatter, scatter ))
#rename
$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire))
$(eval $(call template,rename, rename rename_top rename_src rename_hide rename_enumerate rename_enumerate_pat rename_wire rename_top_top rename_low))
#qwp
#qwp_v - exception (issue #923)
#+ yosys -ql yosys.log ../../scripts/qwp_v.ys
#run.sh: line 11: 28262 Floating point exception(core dumped) yosys -ql yosys.log ../../scripts/$2.ys
$(eval $(call template,qwp, qwp qwp_ltr qwp_grid qwp_dump qwp_alpha))
$(eval $(call template,qwp, qwp qwp_v qwp_ltr qwp_grid qwp_dump qwp_alpha))
#ltp
$(eval $(call template,ltp, ltp ltp_noff ))
......@@ -84,7 +84,7 @@ $(eval $(call template,blackbox, blackbox ))
# - issue #925
#bugpoint ERROR: No such command: autoidx (type 'help' for a command overview)
#$(eval $(call template,bugpoint,bugpoint_yosys bugpoint_script bugpoint_grep bugpoint_fast bugpoint_clean bugpoint_modules bugpoint_ports bugpoint_cells bugpoint_connections ))
$(eval $(call template,bugpoint,bugpoint_yosys bugpoint_script bugpoint_grep bugpoint_fast bugpoint_clean bugpoint_modules bugpoint_ports bugpoint_cells bugpoint_connections ))
#chformal
$(eval $(call template,chformal, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
......@@ -100,7 +100,7 @@ $(eval $(call template,connect, connect_nomap_set connect_nomap_unset connect_no
$(eval $(call template,connwrappers, connwrappers connwrappers_signed connwrappers_unsigned connwrappers_port ))
#plugin
#$(eval $(call template,plugin, plugin plugin_i plugin_a plugin_l ))
$(eval $(call template,plugin, plugin plugin_i plugin_a plugin_l ))
#select
$(eval $(call template,select, select select_all select_add select_add_all select_assert_any select_assert_count select_assert_max select_assert_min select_assert_none select_clear select_count select_del select_list select_module select_none select_read select_set select_write select_add_A_eq select_add_a_eq select_add_A_lesseq select_add_a_lesseq select_add_A_less select_add_a_less select_add_A_moreeq select_add_a_moreeq select_add_A_more select_add_a_more select_add_A select_add_a select_add_c select_add_i select_add_mid select_add_m select_add_n select_add_obj select_add_o select_add_p select_add_r_eq select_add_r_lesseq select_add_r_less select_add_r_moreeq select_add_r_more select_add_r select_add_ss select_add_s select_add_t select_add_w select_add_x ))
......@@ -182,5 +182,18 @@ $(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux
#hilomap
$(eval $(call template,hilomap, hilomap hilomap_hicell hilomap_locell hilomap_singleton hilomap_hicell_singleton hilomap_locell_singleton hilomap_hicell_locell_singleton))
#cutpoint
$(eval $(call template,cutpoint, cutpoint cutpoint_undef))
#mutate
$(eval $(call template,mutate, mutate_list mutate_cnot1 mutate_cnot0 mutate_const1 mutate_const0 mutate_inv mutate_all mutate_list_cfg mutate_list_ctrl mutate_list_none mutate_list_o mutate_list_seed mutate_list_s))
$(eval $(call template,mutate_mem, mutate_list mutate_all))
#fmconbine
$(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd))
#pmuxtree
$(eval $(call template,pmuxtree, pmuxtree))
.PHONY: all clean
misc/cutpoint/top.v 0 → 100644
module bb
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top
(
input x,
input y,
input cin,
output A,
output cout
);
bb u_bb (x,y,cin,A,cout);
endmodule
misc/fmcombine/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.o(o),.y(1'b0));
middle u_mid2 (.x(x),.o(o),.y(1'b1));
middle u_mid3 (.x(x),.o(o),.y(1'bX));
middle u_mid4 (.x(x),.o(o),.y(1'bX));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
urtl u_urtl (.x(x),.o(o),.y(y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
misc/mutate/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/mutate_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
misc/pmuxtree/top.v 0 → 100644
module top(C, S, Y);
input C;
input [1:0] S;
output reg [3:0] Y;
initial Y = 0;
always @(posedge C) begin
case (S)
2'b00: Y <= 4'b0001;
2'b01: Y <= 4'b0010;
2'b10: Y <= 4'b0100;
2'b11: Y <= 4'b1000;
endcase
end
endmodule
misc/rename/top.v
......@@ -28,6 +28,10 @@ module middle
input y,
output o
);
wire dd;
assign o = x + y;
endmodule
module low ();
endmodule
misc/run.sh
#!/bin/bash
set -ex
set -x
test -d $1
test -f scripts/$2.ys
......@@ -8,12 +8,19 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if grep 'Assert' result.log || grep 'failed in' result.log || grep 'fail' result.log || grep 'ERROR' result.log; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
touch .stamp
misc/scripts/cutpoint.ys 0 → 100644
read_verilog ../top.v
tee -o result.log cutpoint top/y top/x top/cout top/A top/cin
tee -o result.log cutpoint top
misc/scripts/cutpoint_undef.ys 0 → 100644
read_verilog ../top.v
tee -o result.log cutpoint top/y top/x top/cout top/A
tee -o result.log cutpoint -undef top/cin
tee -o result.log cutpoint -undef top
misc/scripts/fmcombine.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine top u_mid1 u_mid3
tee -o result.log fmcombine top u_mid2 u_mid4
tee -o result.log fmcombine top u_mid1_u_mid3 u_mid2_u_mid4
misc/scripts/fmcombine_bwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_bwd_fwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -bwd -fwd top u_mid1 u_mid2
misc/scripts/fmcombine_fwd.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -fwd top u_mid1 u_mid2
misc/scripts/fmcombine_nop.ys 0 → 100644
read_verilog ../top.v
tee -o result.log fmcombine -nop top u_mid1 u_mid2
misc/scripts/mutate_all.ys 0 → 100644
read_verilog ../top.v
mutate -list 512 -o mutate.ys
script mutate.ys
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
#tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -ctrlbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
misc/scripts/mutate_cnot0.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
misc/scripts/mutate_cnot1.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src top.v:12
misc/scripts/mutate_const0.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
misc/scripts/mutate_const1.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
misc/scripts/mutate_inv.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
misc/scripts/mutate_list.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -list 32
misc/scripts/mutate_list_cfg.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -list 32 -cfg weight_cover 1
misc/scripts/mutate_list_ctrl.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -list 32 -ctrl A 1 1
misc/scripts/mutate_list_none.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -list 32 -none
misc/scripts/mutate_list_o.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -list 32 -o o.txt
misc/scripts/mutate_list_s.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -list 32 -s s.txt
misc/scripts/mutate_list_seed.ys 0 → 100644
read_verilog ../top.v
tee -o result.log mutate -list 32 -seed 5
misc/scripts/pmuxtree.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log pmuxtree
misc/scripts/rename_low.ys 0 → 100644
read_verilog ../top.v
synth
tee -o result.log rename low newlow
misc/scripts/rename_top_top.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log rename top new_top
regression/Makefile
......@@ -30,7 +30,8 @@ $(eval $(call template,issue_00041,issue_00041))
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
$(eval $(call template,issue_00065,issue_00065))
# Takes too long
#$(eval $(call template,issue_00065,issue_00065))
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
......@@ -50,7 +51,7 @@ $(eval $(call template,issue_00081,issue_00081))
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
#$(eval $(call template,issue_00082,issue_00082))
$(eval $(call template,issue_00082,issue_00082))
#issue_00083
#Warning: Deep recursion in AST simplifier.
......@@ -58,7 +59,7 @@ $(eval $(call template,issue_00081,issue_00081))
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
#$(eval $(call template,issue_00083,issue_00083))
$(eval $(call template,issue_00083,issue_00083))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
......@@ -298,6 +299,7 @@ $(eval $(call template,issue_00763,issue_00763))
$(eval $(call template,issue_00767,issue_00767))
#issue_00774
# Takes too long
#$(eval $(call template,issue_00774,issue_00774))
#issue_00781
......@@ -339,7 +341,26 @@ $(eval $(call template,issue_00862,issue_00862))
#issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
$(eval $(call template,issue_00865,issue_00865))
#issue_00867
$(eval $(call template,issue_00867,issue_00867))
#issue_00870
$(eval $(call template,issue_00870,issue_00870))
#issue_00873
$(eval $(call template,issue_00873,issue_00873))
#issue_00888
$(eval $(call template,issue_00888,issue_00888))
#pr_00896
$(eval $(call template,pr_00896,pr_00896))
#issue_00922
$(eval $(call template,issue_00922,issue_00922))
#issue_00931
$(eval $(call template,issue_00931,issue_00931))
.PHONY: all clean
regression/issue_00059/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00059/top.v
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00067/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00067/top.v
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00071/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00071/top.v
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00078/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00078/top.v
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00081/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00081/top.v
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00085/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00085/top.v
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00086/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00086/top.v
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00088/testbench.v
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
regression/issue_00088/top.v
parameter X = 2;
module top(b);
module top(b,c);
input b;
output c;
parameter Y = 3;
assign c = b;
endmodule
regression/issue_00867/top.v 0 → 100644
module top
(
// Closk & reset
input wire clk,
input wire rstn,
// PicoRV32 bus interface
input wire valid,
output wire ready,
input wire [31:0] addr,
output wire [31:0] rdata
);
// ============================================================================
localparam MEM_SIZE_BITS = 10; // In 32-bit words
localparam MEM_SIZE = 1 << MEM_SIZE_BITS;
localparam MEM_ADDR_MASK = 32'h0010_0000;
// ============================================================================
wire [MEM_SIZE_BITS-1:0] mem_addr;
reg [31:0] mem_data;
reg [31:0] mem[0:MEM_SIZE];
initial begin
mem['h0000] <= 32'h00000093;
mem['h0001] <= 32'h00000193;
mem['h0002] <= 32'h00000213;
mem['h0003] <= 32'h00000293;
mem['h0004] <= 32'h00000313;
mem['h0005] <= 32'h00000393;
mem['h0006] <= 32'h00000413;
mem['h0007] <= 32'h00000493;
mem['h0008] <= 32'h00000513;
mem['h0009] <= 32'h00000593;
mem['h000A] <= 32'h00000613;
mem['h000B] <= 32'h00000693;
mem['h000C] <= 32'h00000713;
mem['h000D] <= 32'h00000793;
mem['h000E] <= 32'h00000813;
mem['h000F] <= 32'h00000893;
mem['h0010] <= 32'h00000913;
mem['h0011] <= 32'h00000993;
mem['h0012] <= 32'h00000A13;
mem['h0013] <= 32'h00000A93;
mem['h0014] <= 32'h00000B13;
mem['h0015] <= 32'h00000B93;
mem['h0016] <= 32'h00000C13;
mem['h0017] <= 32'h00000C93;
mem['h0018] <= 32'h00000D13;
mem['h0019] <= 32'h00000D93;
mem['h001A] <= 32'h00000E13;
mem['h001B] <= 32'h00000E93;
mem['h001C] <= 32'h00000F13;
mem['h001D] <= 32'h00000F93;
mem['h001E] <= 32'h03000537;
mem['h001F] <= 32'h00100593;
mem['h0020] <= 32'h00B52023;
mem['h0021] <= 32'h00000513;
mem['h0022] <= 32'h00A52023;
mem['h0023] <= 32'h00450513;
mem['h0024] <= 32'hFE254CE3;
mem['h0025] <= 32'h03000537;
mem['h0026] <= 32'h00300593;
mem['h0027] <= 32'h00B52023;
mem['h0028] <= 32'h00001517;
mem['h0029] <= 32'hB4050513;
mem['h002A] <= 32'h00000593;
mem['h002B] <= 32'h00000613;
mem['h002C] <= 32'h00C5DC63;
mem['h002D] <= 32'h00052683;
mem['h002E] <= 32'h00D5A023;
mem['h002F] <= 32'h00450513;
mem['h0030] <= 32'h00458593;
mem['h0031] <= 32'hFEC5C8E3;
mem['h0032] <= 32'h03000537;
mem['h0033] <= 32'h00700593;
mem['h0034] <= 32'h00B52023;
mem['h0035] <= 32'h00000513;
mem['h0036] <= 32'h00000593;
mem['h0037] <= 32'h00B55863;
mem['h0038] <= 32'h00052023;
mem['h0039] <= 32'h00450513;
mem['h003A] <= 32'hFEB54CE3;
mem['h003B] <= 32'h03000537;
mem['h003C] <= 32'h00F00593;
mem['h003D] <= 32'h00B52023;
mem['h003E] <= 32'h015000EF;
mem['h003F] <= 32'h0000006F;
mem['h0040] <= 32'h020002B7;
mem['h0041] <= 32'h12000313;
mem['h0042] <= 32'h00629023;
mem['h0043] <= 32'h000281A3;
mem['h0044] <= 32'h02060863;
mem['h0045] <= 32'h00800F13;
mem['h0046] <= 32'h0FF67393;
mem['h0047] <= 32'h0073DE93;
mem['h0048] <= 32'h01D28023;
mem['h0049] <= 32'h010EEE93;
mem['h004A] <= 32'h01D28023;
mem['h004B] <= 32'h00139393;
mem['h004C] <= 32'h0FF3F393;
mem['h004D] <= 32'hFFFF0F13;
mem['h004E] <= 32'hFE0F12E3;
mem['h004F] <= 32'h00628023;
mem['h0050] <= 32'h04058663;
mem['h0051] <= 32'h00800F13;
mem['h0052] <= 32'h00054383;
mem['h0053] <= 32'h0073DE93;
mem['h0054] <= 32'h01D28023;
mem['h0055] <= 32'h010EEE93;
mem['h0056] <= 32'h01D28023;
mem['h0057] <= 32'h0002CE83;
mem['h0058] <= 32'h002EFE93;
mem['h0059] <= 32'h001EDE93;
mem['h005A] <= 32'h00139393;
mem['h005B] <= 32'h01D3E3B3;
mem['h005C] <= 32'h0FF3F393;
mem['h005D] <= 32'hFFFF0F13;
mem['h005E] <= 32'hFC0F1AE3;
mem['h005F] <= 32'h00750023;
mem['h0060] <= 32'h00150513;
mem['h0061] <= 32'hFFF58593;
mem['h0062] <= 32'hFB9FF06F;
mem['h0063] <= 32'h08000313;
mem['h0064] <= 32'h006281A3;
mem['h0065] <= 32'h00008067;
mem['h0066] <= 32'hFE010113;
mem['h0067] <= 32'h00112E23;
mem['h0068] <= 32'h00812C23;
mem['h0069] <= 32'h02010413;
mem['h006A] <= 32'h00050793;
mem['h006B] <= 32'hFEF407A3;
mem['h006C] <= 32'hFEF44703;
mem['h006D] <= 32'h00A00793;
mem['h006E] <= 32'h00F71663;
mem['h006F] <= 32'h00D00513;
mem['h0070] <= 32'hFD9FF0EF;
mem['h0071] <= 32'h020007B7;
mem['h0072] <= 32'h00878793;
mem['h0073] <= 32'hFEF44703;
mem['h0074] <= 32'h00E7A023;
mem['h0075] <= 32'h00000013;
mem['h0076] <= 32'h01C12083;
mem['h0077] <= 32'h01812403;
mem['h0078] <= 32'h02010113;
mem['h0079] <= 32'h00008067;
mem['h007A] <= 32'hFE010113;
mem['h007B] <= 32'h00112E23;
mem['h007C] <= 32'h00812C23;
mem['h007D] <= 32'h02010413;
mem['h007E] <= 32'hFEA42623;
mem['h007F] <= 32'h01C0006F;
mem['h0080] <= 32'hFEC42783;
mem['h0081] <= 32'h00178713;
mem['h0082] <= 32'hFEE42623;
mem['h0083] <= 32'h0007C783;
mem['h0084] <= 32'h00078513;
mem['h0085] <= 32'hF85FF0EF;
mem['h0086] <= 32'hFEC42783;
mem['h0087] <= 32'h0007C783;
mem['h0088] <= 32'hFE0790E3;
mem['h0089] <= 32'h00000013;
mem['h008A] <= 32'h01C12083;
mem['h008B] <= 32'h01812403;
mem['h008C] <= 32'h02010113;
mem['h008D] <= 32'h00008067;
mem['h008E] <= 32'hFD010113;
mem['h008F] <= 32'h02112623;
mem['h0090] <= 32'h02812423;
mem['h0091] <= 32'h03010413;
mem['h0092] <= 32'hFCA42E23;
mem['h0093] <= 32'hFCB42C23;
mem['h0094] <= 32'h00700793;
mem['h0095] <= 32'hFEF42623;
mem['h0096] <= 32'h06C0006F;
mem['h0097] <= 32'hFEC42783;
mem['h0098] <= 32'h00279793;
mem['h0099] <= 32'hFDC42703;
mem['h009A] <= 32'h00F757B3;
mem['h009B] <= 32'h00F7F713;
mem['h009C] <= 32'h001017B7;
mem['h009D] <= 32'hA8078793;
mem['h009E] <= 32'h00F707B3;
mem['h009F] <= 32'h0007C783;
mem['h00A0] <= 32'hFEF405A3;
mem['h00A1] <= 32'hFEB44703;
mem['h00A2] <= 32'h03000793;
mem['h00A3] <= 32'h00F71863;
mem['h00A4] <= 32'hFEC42703;
mem['h00A5] <= 32'hFD842783;
mem['h00A6] <= 32'h00F75E63;
mem['h00A7] <= 32'hFEB44783;
mem['h00A8] <= 32'h00078513;
mem['h00A9] <= 32'hEF5FF0EF;
mem['h00AA] <= 32'hFEC42783;
mem['h00AB] <= 32'hFCF42C23;
mem['h00AC] <= 32'h0080006F;
mem['h00AD] <= 32'h00000013;
mem['h00AE] <= 32'hFEC42783;
mem['h00AF] <= 32'hFFF78793;
mem['h00B0] <= 32'hFEF42623;
mem['h00B1] <= 32'hFEC42783;
mem['h00B2] <= 32'hF807DAE3;
mem['h00B3] <= 32'h00000013;
mem['h00B4] <= 32'h02C12083;
mem['h00B5] <= 32'h02812403;
mem['h00B6] <= 32'h03010113;
mem['h00B7] <= 32'h00008067;
mem['h00B8] <= 32'hFE010113;
mem['h00B9] <= 32'h00112E23;
mem['h00BA] <= 32'h00812C23;
mem['h00BB] <= 32'h02010413;
mem['h00BC] <= 32'hFEA42623;
mem['h00BD] <= 32'hFEC42703;
mem['h00BE] <= 32'h06300793;
mem['h00BF] <= 32'h00E7FA63;
mem['h00C0] <= 32'h001017B7;
mem['h00C1] <= 32'hA9478513;
mem['h00C2] <= 32'hEE1FF0EF;
mem['h00C3] <= 32'h28C0006F;
mem['h00C4] <= 32'hFEC42703;
mem['h00C5] <= 32'h05900793;
mem['h00C6] <= 32'h00E7FE63;
mem['h00C7] <= 32'h03900513;
mem['h00C8] <= 32'hE79FF0EF;
mem['h00C9] <= 32'hFEC42783;
mem['h00CA] <= 32'hFA678793;
mem['h00CB] <= 32'hFEF42623;
mem['h00CC] <= 32'h1200006F;
mem['h00CD] <= 32'hFEC42703;
mem['h00CE] <= 32'h04F00793;
mem['h00CF] <= 32'h00E7FE63;
mem['h00D0] <= 32'h03800513;
mem['h00D1] <= 32'hE55FF0EF;
mem['h00D2] <= 32'hFEC42783;
mem['h00D3] <= 32'hFB078793;
mem['h00D4] <= 32'hFEF42623;
mem['h00D5] <= 32'h0FC0006F;
mem['h00D6] <= 32'hFEC42703;
mem['h00D7] <= 32'h04500793;
mem['h00D8] <= 32'h00E7FE63;
mem['h00D9] <= 32'h03700513;
mem['h00DA] <= 32'hE31FF0EF;
mem['h00DB] <= 32'hFEC42783;
mem['h00DC] <= 32'hFBA78793;
mem['h00DD] <= 32'hFEF42623;
mem['h00DE] <= 32'h0D80006F;
mem['h00DF] <= 32'hFEC42703;
mem['h00E0] <= 32'h03B00793;
mem['h00E1] <= 32'h00E7FE63;
mem['h00E2] <= 32'h03600513;
mem['h00E3] <= 32'hE0DFF0EF;
mem['h00E4] <= 32'hFEC42783;
mem['h00E5] <= 32'hFC478793;
mem['h00E6] <= 32'hFEF42623;
mem['h00E7] <= 32'h0B40006F;
mem['h00E8] <= 32'hFEC42703;
mem['h00E9] <= 32'h03100793;
mem['h00EA] <= 32'h00E7FE63;
mem['h00EB] <= 32'h03500513;
mem['h00EC] <= 32'hDE9FF0EF;
mem['h00ED] <= 32'hFEC42783;
mem['h00EE] <= 32'hFCE78793;
mem['h00EF] <= 32'hFEF42623;
mem['h00F0] <= 32'h0900006F;
mem['h00F1] <= 32'hFEC42703;
mem['h00F2] <= 32'h02700793;
mem['h00F3] <= 32'h00E7FE63;
mem['h00F4] <= 32'h03400513;
mem['h00F5] <= 32'hDC5FF0EF;
mem['h00F6] <= 32'hFEC42783;
mem['h00F7] <= 32'hFD878793;
mem['h00F8] <= 32'hFEF42623;
mem['h00F9] <= 32'h06C0006F;
mem['h00FA] <= 32'hFEC42703;
mem['h00FB] <= 32'h01D00793;
mem['h00FC] <= 32'h00E7FE63;
mem['h00FD] <= 32'h03300513;
mem['h00FE] <= 32'hDA1FF0EF;
mem['h00FF] <= 32'hFEC42783;
mem['h0100] <= 32'hFE278793;
mem['h0101] <= 32'hFEF42623;
mem['h0102] <= 32'h0480006F;
mem['h0103] <= 32'hFEC42703;
mem['h0104] <= 32'h01300793;
mem['h0105] <= 32'h00E7FE63;
mem['h0106] <= 32'h03200513;
mem['h0107] <= 32'hD7DFF0EF;
mem['h0108] <= 32'hFEC42783;
mem['h0109] <= 32'hFEC78793;
mem['h010A] <= 32'hFEF42623;
mem['h010B] <= 32'h0240006F;
mem['h010C] <= 32'hFEC42703;
mem['h010D] <= 32'h00900793;
mem['h010E] <= 32'h00E7FC63;
mem['h010F] <= 32'h03100513;
mem['h0110] <= 32'hD59FF0EF;
mem['h0111] <= 32'hFEC42783;
mem['h0112] <= 32'hFF678793;
mem['h0113] <= 32'hFEF42623;
mem['h0114] <= 32'hFEC42703;
mem['h0115] <= 32'h00800793;
mem['h0116] <= 32'h00E7FE63;
mem['h0117] <= 32'h03900513;
mem['h0118] <= 32'hD39FF0EF;
mem['h0119] <= 32'hFEC42783;
mem['h011A] <= 32'hFF778793;
mem['h011B] <= 32'hFEF42623;
mem['h011C] <= 32'h1280006F;
mem['h011D] <= 32'hFEC42703;
mem['h011E] <= 32'h00700793;
mem['h011F] <= 32'h00E7FE63;
mem['h0120] <= 32'h03800513;
mem['h0121] <= 32'hD15FF0EF;
mem['h0122] <= 32'hFEC42783;
mem['h0123] <= 32'hFF878793;
mem['h0124] <= 32'hFEF42623;
mem['h0125] <= 32'h1040006F;
mem['h0126] <= 32'hFEC42703;
mem['h0127] <= 32'h00600793;
mem['h0128] <= 32'h00E7FE63;
mem['h0129] <= 32'h03700513;
mem['h012A] <= 32'hCF1FF0EF;
mem['h012B] <= 32'hFEC42783;
mem['h012C] <= 32'hFF978793;
mem['h012D] <= 32'hFEF42623;
mem['h012E] <= 32'h0E00006F;
mem['h012F] <= 32'hFEC42703;
mem['h0130] <= 32'h00500793;
mem['h0131] <= 32'h00E7FE63;
mem['h0132] <= 32'h03600513;
mem['h0133] <= 32'hCCDFF0EF;
mem['h0134] <= 32'hFEC42783;
mem['h0135] <= 32'hFFA78793;
mem['h0136] <= 32'hFEF42623;
mem['h0137] <= 32'h0BC0006F;
mem['h0138] <= 32'hFEC42703;
mem['h0139] <= 32'h00400793;
mem['h013A] <= 32'h00E7FE63;
mem['h013B] <= 32'h03500513;
mem['h013C] <= 32'hCA9FF0EF;
mem['h013D] <= 32'hFEC42783;
mem['h013E] <= 32'hFFB78793;
mem['h013F] <= 32'hFEF42623;
mem['h0140] <= 32'h0980006F;
mem['h0141] <= 32'hFEC42703;
mem['h0142] <= 32'h00300793;
mem['h0143] <= 32'h00E7FE63;
mem['h0144] <= 32'h03400513;
mem['h0145] <= 32'hC85FF0EF;
mem['h0146] <= 32'hFEC42783;
mem['h0147] <= 32'hFFC78793;
mem['h0148] <= 32'hFEF42623;
mem['h0149] <= 32'h0740006F;
mem['h014A] <= 32'hFEC42703;
mem['h014B] <= 32'h00200793;
mem['h014C] <= 32'h00E7FE63;
mem['h014D] <= 32'h03300513;
mem['h014E] <= 32'hC61FF0EF;
mem['h014F] <= 32'hFEC42783;
mem['h0150] <= 32'hFFD78793;
mem['h0151] <= 32'hFEF42623;
mem['h0152] <= 32'h0500006F;
mem['h0153] <= 32'hFEC42703;
mem['h0154] <= 32'h00100793;
mem['h0155] <= 32'h00E7FE63;
mem['h0156] <= 32'h03200513;
mem['h0157] <= 32'hC3DFF0EF;
mem['h0158] <= 32'hFEC42783;
mem['h0159] <= 32'hFFE78793;
mem['h015A] <= 32'hFEF42623;
mem['h015B] <= 32'h02C0006F;
mem['h015C] <= 32'hFEC42783;
mem['h015D] <= 32'h00078E63;
mem['h015E] <= 32'h03100513;
mem['h015F] <= 32'hC1DFF0EF;
mem['h0160] <= 32'hFEC42783;
mem['h0161] <= 32'hFFF78793;
mem['h0162] <= 32'hFEF42623;
mem['h0163] <= 32'h00C0006F;
mem['h0164] <= 32'h03000513;
mem['h0165] <= 32'hC05FF0EF;
mem['h0166] <= 32'h01C12083;
mem['h0167] <= 32'h01812403;
mem['h0168] <= 32'h02010113;
mem['h0169] <= 32'h00008067;
mem['h016A] <= 32'hFD010113;
mem['h016B] <= 32'h02112623;
mem['h016C] <= 32'h02812423;
mem['h016D] <= 32'h03010413;
mem['h016E] <= 32'hFCA42E23;
mem['h016F] <= 32'hFFF00793;
mem['h0170] <= 32'hFEF42623;
mem['h0171] <= 32'hC00027F3;
mem['h0172] <= 32'hFEF42423;
mem['h0173] <= 32'h030007B7;
mem['h0174] <= 32'hFFF00713;
mem['h0175] <= 32'h00E7A023;
mem['h0176] <= 32'hFDC42783;
mem['h0177] <= 32'h08078A63;
mem['h0178] <= 32'hFDC42503;
mem['h0179] <= 32'hC05FF0EF;
mem['h017A] <= 32'h0880006F;
mem['h017B] <= 32'hC00027F3;
mem['h017C] <= 32'hFEF42223;
mem['h017D] <= 32'hFE442703;
mem['h017E] <= 32'hFE842783;
mem['h017F] <= 32'h40F707B3;
mem['h0180] <= 32'hFEF42023;
mem['h0181] <= 32'hFE042703;
mem['h0182] <= 32'h00B727B7;
mem['h0183] <= 32'hB0078793;
mem['h0184] <= 32'h04E7F863;
mem['h0185] <= 32'hFDC42783;
mem['h0186] <= 32'h00078663;
mem['h0187] <= 32'hFDC42503;
mem['h0188] <= 32'hBC9FF0EF;
mem['h0189] <= 32'hFE442783;
mem['h018A] <= 32'hFEF42423;
mem['h018B] <= 32'h030007B7;
mem['h018C] <= 32'h0007A783;
mem['h018D] <= 32'h00179713;
mem['h018E] <= 32'h030007B7;
mem['h018F] <= 32'h0007A783;
mem['h0190] <= 32'h0017D793;
mem['h0191] <= 32'h0017F793;
mem['h0192] <= 32'h0017B793;
mem['h0193] <= 32'h0FF7F793;
mem['h0194] <= 32'h00078693;
mem['h0195] <= 32'h030007B7;
mem['h0196] <= 32'h00D76733;
mem['h0197] <= 32'h00E7A023;
mem['h0198] <= 32'h020007B7;
mem['h0199] <= 32'h00878793;
mem['h019A] <= 32'h0007A783;
mem['h019B] <= 32'hFEF42623;
mem['h019C] <= 32'hFEC42703;
mem['h019D] <= 32'hFFF00793;
mem['h019E] <= 32'hF6F70AE3;
mem['h019F] <= 32'h030007B7;
mem['h01A0] <= 32'h0007A023;
mem['h01A1] <= 32'hFEC42783;
mem['h01A2] <= 32'h0FF7F793;
mem['h01A3] <= 32'h00078513;
mem['h01A4] <= 32'h02C12083;
mem['h01A5] <= 32'h02812403;
mem['h01A6] <= 32'h03010113;
mem['h01A7] <= 32'h00008067;
mem['h01A8] <= 32'hFF010113;
mem['h01A9] <= 32'h00112623;
mem['h01AA] <= 32'h00812423;
mem['h01AB] <= 32'h01010413;
mem['h01AC] <= 32'h00000513;
mem['h01AD] <= 32'hEF5FF0EF;
mem['h01AE] <= 32'h00050793;
mem['h01AF] <= 32'h00078513;
mem['h01B0] <= 32'h00C12083;
mem['h01B1] <= 32'h00812403;
mem['h01B2] <= 32'h01010113;
mem['h01B3] <= 32'h00008067;
mem['h01B4] <= 32'hEB010113;
mem['h01B5] <= 32'h14112623;
mem['h01B6] <= 32'h14812423;
mem['h01B7] <= 32'h15010413;
mem['h01B8] <= 32'h00050793;
mem['h01B9] <= 32'hEAB42C23;
mem['h01BA] <= 32'hEAF40FA3;
mem['h01BB] <= 32'hEC040793;
mem['h01BC] <= 32'hFCF42A23;
mem['h01BD] <= 32'h12B9B7B7;
mem['h01BE] <= 32'h0A178793;
mem['h01BF] <= 32'hFEF42623;
mem['h01C0] <= 32'hC00027F3;
mem['h01C1] <= 32'hFCF42823;
mem['h01C2] <= 32'hC02027F3;
mem['h01C3] <= 32'hFCF42623;
mem['h01C4] <= 32'hFE042423;
mem['h01C5] <= 32'h1200006F;
mem['h01C6] <= 32'hFE042223;
mem['h01C7] <= 32'h0640006F;
mem['h01C8] <= 32'hFEC42783;
mem['h01C9] <= 32'h00D79793;
mem['h01CA] <= 32'hFEC42703;
mem['h01CB] <= 32'h00F747B3;
mem['h01CC] <= 32'hFEF42623;
mem['h01CD] <= 32'hFEC42783;
mem['h01CE] <= 32'h0117D793;
mem['h01CF] <= 32'hFEC42703;
mem['h01D0] <= 32'h00F747B3;
mem['h01D1] <= 32'hFEF42623;
mem['h01D2] <= 32'hFEC42783;
mem['h01D3] <= 32'h00579793;
mem['h01D4] <= 32'hFEC42703;
mem['h01D5] <= 32'h00F747B3;
mem['h01D6] <= 32'hFEF42623;
mem['h01D7] <= 32'hFEC42783;
mem['h01D8] <= 32'h0FF7F713;
mem['h01D9] <= 32'hFE442783;
mem['h01DA] <= 32'hFF040693;
mem['h01DB] <= 32'h00F687B3;
mem['h01DC] <= 32'hECE78823;
mem['h01DD] <= 32'hFE442783;
mem['h01DE] <= 32'h00178793;
mem['h01DF] <= 32'hFEF42223;
mem['h01E0] <= 32'hFE442703;
mem['h01E1] <= 32'h0FF00793;
mem['h01E2] <= 32'hF8E7DCE3;
mem['h01E3] <= 32'hFE042023;
mem['h01E4] <= 32'hFC042E23;
mem['h01E5] <= 32'h0440006F;
mem['h01E6] <= 32'hFE042783;
mem['h01E7] <= 32'hFF040713;
mem['h01E8] <= 32'h00F707B3;
mem['h01E9] <= 32'hED07C783;
mem['h01EA] <= 32'h02078263;
mem['h01EB] <= 32'hFDC42783;
mem['h01EC] <= 32'h00178713;
mem['h01ED] <= 32'hFCE42E23;
mem['h01EE] <= 32'hFE042703;
mem['h01EF] <= 32'h0FF77713;
mem['h01F0] <= 32'hFF040693;
mem['h01F1] <= 32'h00F687B3;
mem['h01F2] <= 32'hECE78823;
mem['h01F3] <= 32'hFE042783;
mem['h01F4] <= 32'h00178793;
mem['h01F5] <= 32'hFEF42023;
mem['h01F6] <= 32'hFE042703;
mem['h01F7] <= 32'h0FF00793;
mem['h01F8] <= 32'hFAE7DCE3;
mem['h01F9] <= 32'hFC042C23;
mem['h01FA] <= 32'hFC042023;
mem['h01FB] <= 32'h0300006F;
mem['h01FC] <= 32'hFD842783;
mem['h01FD] <= 32'h00279793;
mem['h01FE] <= 32'hFD442703;
mem['h01FF] <= 32'h00F707B3;
mem['h0200] <= 32'h0007A783;
mem['h0201] <= 32'hFEC42703;
mem['h0202] <= 32'h00F747B3;
mem['h0203] <= 32'hFEF42623;
mem['h0204] <= 32'hFD842783;
mem['h0205] <= 32'h00178793;
mem['h0206] <= 32'hFCF42C23;
mem['h0207] <= 32'hFD842703;
mem['h0208] <= 32'h03F00793;
mem['h0209] <= 32'hFCE7D6E3;
mem['h020A] <= 32'hFE842783;
mem['h020B] <= 32'h00178793;
mem['h020C] <= 32'hFEF42423;
mem['h020D] <= 32'hFE842703;
mem['h020E] <= 32'h01300793;
mem['h020F] <= 32'hECE7DEE3;
mem['h0210] <= 32'hC00027F3;
mem['h0211] <= 32'hFCF42423;
mem['h0212] <= 32'hC02027F3;
mem['h0213] <= 32'hFCF42223;
mem['h0214] <= 32'hEBF44783;
mem['h0215] <= 32'h06078E63;
mem['h0216] <= 32'h001017B7;
mem['h0217] <= 32'hA9C78513;
mem['h0218] <= 32'h989FF0EF;
mem['h0219] <= 32'hFC842703;
mem['h021A] <= 32'hFD042783;
mem['h021B] <= 32'h40F707B3;
mem['h021C] <= 32'h00800593;
mem['h021D] <= 32'h00078513;
mem['h021E] <= 32'h9C1FF0EF;
mem['h021F] <= 32'h00A00513;
mem['h0220] <= 32'h919FF0EF;
mem['h0221] <= 32'h001017B7;
mem['h0222] <= 32'hAA878513;
mem['h0223] <= 32'h95DFF0EF;
mem['h0224] <= 32'hFC442703;
mem['h0225] <= 32'hFCC42783;
mem['h0226] <= 32'h40F707B3;
mem['h0227] <= 32'h00800593;
mem['h0228] <= 32'h00078513;
mem['h0229] <= 32'h995FF0EF;
mem['h022A] <= 32'h00A00513;
mem['h022B] <= 32'h8EDFF0EF;
mem['h022C] <= 32'h001017B7;
mem['h022D] <= 32'hAB478513;
mem['h022E] <= 32'h931FF0EF;
mem['h022F] <= 32'h00800593;
mem['h0230] <= 32'hFEC42503;
mem['h0231] <= 32'h975FF0EF;
mem['h0232] <= 32'h00A00513;
mem['h0233] <= 32'h8CDFF0EF;
mem['h0234] <= 32'hEB842783;
mem['h0235] <= 32'h00078C63;
mem['h0236] <= 32'hFC442703;
mem['h0237] <= 32'hFCC42783;
mem['h0238] <= 32'h40F70733;
mem['h0239] <= 32'hEB842783;
mem['h023A] <= 32'h00E7A023;
mem['h023B] <= 32'hFC842703;
mem['h023C] <= 32'hFD042783;
mem['h023D] <= 32'h40F707B3;
mem['h023E] <= 32'h00078513;
mem['h023F] <= 32'h14C12083;
mem['h0240] <= 32'h14812403;
mem['h0241] <= 32'h15010113;
mem['h0242] <= 32'h00008067;
mem['h0243] <= 32'hFE010113;
mem['h0244] <= 32'h00112E23;
mem['h0245] <= 32'h00812C23;
mem['h0246] <= 32'h02010413;
mem['h0247] <= 32'h030007B7;
mem['h0248] <= 32'h01F00713;
mem['h0249] <= 32'h00E7A023;
mem['h024A] <= 32'h020007B7;
mem['h024B] <= 32'h00478793;
mem['h024C] <= 32'h0D900713;
mem['h024D] <= 32'h00E7A023;
mem['h024E] <= 32'h001017B7;
mem['h024F] <= 32'hAC078513;
mem['h0250] <= 32'h8A9FF0EF;
mem['h0251] <= 32'h030007B7;
mem['h0252] <= 32'h03F00713;
mem['h0253] <= 32'h00E7A023;
mem['h0254] <= 32'h030007B7;
mem['h0255] <= 32'h07F00713;
mem['h0256] <= 32'h00E7A023;
mem['h0257] <= 32'h00000013;
mem['h0258] <= 32'h001017B7;
mem['h0259] <= 32'hACC78513;
mem['h025A] <= 32'hC41FF0EF;
mem['h025B] <= 32'h00050793;
mem['h025C] <= 32'h00078713;
mem['h025D] <= 32'h00D00793;
mem['h025E] <= 32'hFEF714E3;
mem['h025F] <= 32'h001017B7;
mem['h0260] <= 32'hAE878513;
mem['h0261] <= 32'h865FF0EF;
mem['h0262] <= 32'h001017B7;
mem['h0263] <= 32'hAEC78513;
mem['h0264] <= 32'h859FF0EF;
mem['h0265] <= 32'h001017B7;
mem['h0266] <= 32'hB1478513;
mem['h0267] <= 32'h84DFF0EF;
mem['h0268] <= 32'h001017B7;
mem['h0269] <= 32'hB3C78513;
mem['h026A] <= 32'h841FF0EF;
mem['h026B] <= 32'h001017B7;
mem['h026C] <= 32'hB6078513;
mem['h026D] <= 32'h835FF0EF;
mem['h026E] <= 32'h001017B7;
mem['h026F] <= 32'hB8878513;
mem['h0270] <= 32'h829FF0EF;
mem['h0271] <= 32'h001017B7;
mem['h0272] <= 32'hAE878513;
mem['h0273] <= 32'h81DFF0EF;
mem['h0274] <= 32'h001017B7;
mem['h0275] <= 32'hAE878513;
mem['h0276] <= 32'h811FF0EF;
mem['h0277] <= 32'h001017B7;
mem['h0278] <= 32'hBB078513;
mem['h0279] <= 32'h805FF0EF;
mem['h027A] <= 32'h001017B7;
mem['h027B] <= 32'hAE878513;
mem['h027C] <= 32'hFF8FF0EF;
mem['h027D] <= 32'h00A00793;
mem['h027E] <= 32'hFEF42623;
mem['h027F] <= 32'h0780006F;
mem['h0280] <= 32'h001017B7;
mem['h0281] <= 32'hBD478513;
mem['h0282] <= 32'hFE0FF0EF;
mem['h0283] <= 32'hC95FF0EF;
mem['h0284] <= 32'h00050793;
mem['h0285] <= 32'hFEF405A3;
mem['h0286] <= 32'hFEB44703;
mem['h0287] <= 32'h02000793;
mem['h0288] <= 32'h00E7FE63;
mem['h0289] <= 32'hFEB44703;
mem['h028A] <= 32'h07E00793;
mem['h028B] <= 32'h00E7E863;
mem['h028C] <= 32'hFEB44783;
mem['h028D] <= 32'h00078513;
mem['h028E] <= 32'hF60FF0EF;
mem['h028F] <= 32'h001017B7;
mem['h0290] <= 32'hAE878513;
mem['h0291] <= 32'hFA4FF0EF;
mem['h0292] <= 32'hFEB44703;
mem['h0293] <= 32'h03900793;
mem['h0294] <= 32'h00F71C63;
mem['h0295] <= 32'h00000593;
mem['h0296] <= 32'h00100513;
mem['h0297] <= 32'hC75FF0EF;
mem['h0298] <= 32'h00000013;
mem['h0299] <= 32'h0180006F;
mem['h029A] <= 32'hFEC42783;
mem['h029B] <= 32'hFFF78793;
mem['h029C] <= 32'hFEF42623;
mem['h029D] <= 32'hFEC42783;
mem['h029E] <= 32'hF8F044E3;
mem['h029F] <= 32'hF49FF06F;
mem['h02A0] <= 32'h33323130;
mem['h02A1] <= 32'h37363534;
mem['h02A2] <= 32'h62613938;
mem['h02A3] <= 32'h66656463;
mem['h02A4] <= 32'h00000000;
mem['h02A5] <= 32'h30313D3E;
mem['h02A6] <= 32'h00000030;
mem['h02A7] <= 32'h6C637943;
mem['h02A8] <= 32'h203A7365;
mem['h02A9] <= 32'h00007830;
mem['h02AA] <= 32'h74736E49;
mem['h02AB] <= 32'h203A736E;
mem['h02AC] <= 32'h00007830;
mem['h02AD] <= 32'h736B6843;
mem['h02AE] <= 32'h203A6D75;
mem['h02AF] <= 32'h00007830;
mem['h02B0] <= 32'h746F6F42;
mem['h02B1] <= 32'h2E676E69;
mem['h02B2] <= 32'h00000A2E;
mem['h02B3] <= 32'h73657250;
mem['h02B4] <= 32'h4E452073;
mem['h02B5] <= 32'h20524554;
mem['h02B6] <= 32'h63206F74;
mem['h02B7] <= 32'h69746E6F;
mem['h02B8] <= 32'h2E65756E;
mem['h02B9] <= 32'h00000A2E;
mem['h02BA] <= 32'h0000000A;
mem['h02BB] <= 32'h5F5F2020;
mem['h02BC] <= 32'h20205F5F;
mem['h02BD] <= 32'h2020205F;
mem['h02BE] <= 32'h20202020;
mem['h02BF] <= 32'h5F202020;
mem['h02C0] <= 32'h205F5F5F;
mem['h02C1] <= 32'h20202020;
mem['h02C2] <= 32'h20202020;
mem['h02C3] <= 32'h5F5F5F5F;
mem['h02C4] <= 32'h0000000A;
mem['h02C5] <= 32'h20207C20;
mem['h02C6] <= 32'h285C205F;
mem['h02C7] <= 32'h5F20295F;
mem['h02C8] <= 32'h5F205F5F;
mem['h02C9] <= 32'h202F5F5F;
mem['h02CA] <= 32'h7C5F5F5F;
mem['h02CB] <= 32'h5F5F2020;
mem['h02CC] <= 32'h2F20205F;
mem['h02CD] <= 32'h5F5F5F20;
mem['h02CE] <= 32'h00000A7C;
mem['h02CF] <= 32'h7C207C20;
mem['h02D0] <= 32'h7C20295F;
mem['h02D1] <= 32'h202F7C20;
mem['h02D2] <= 32'h202F5F5F;
mem['h02D3] <= 32'h5F5C205F;
mem['h02D4] <= 32'h5C205F5F;
mem['h02D5] <= 32'h5F202F20;
mem['h02D6] <= 32'h207C5C20;
mem['h02D7] <= 32'h00000A7C;
mem['h02D8] <= 32'h20207C20;
mem['h02D9] <= 32'h7C2F5F5F;
mem['h02DA] <= 32'h28207C20;
mem['h02DB] <= 32'h28207C5F;
mem['h02DC] <= 32'h7C20295F;
mem['h02DD] <= 32'h20295F5F;
mem['h02DE] <= 32'h5F28207C;
mem['h02DF] <= 32'h207C2029;
mem['h02E0] <= 32'h5F5F5F7C;
mem['h02E1] <= 32'h0000000A;
mem['h02E2] <= 32'h7C5F7C20;
mem['h02E3] <= 32'h7C202020;
mem['h02E4] <= 32'h5F5C7C5F;
mem['h02E5] <= 32'h5F5C5F5F;
mem['h02E6] <= 32'h5F2F5F5F;
mem['h02E7] <= 32'h2F5F5F5F;
mem['h02E8] <= 32'h5F5F5C20;
mem['h02E9] <= 32'h5C202F5F;
mem['h02EA] <= 32'h5F5F5F5F;
mem['h02EB] <= 32'h00000A7C;
mem['h02EC] <= 32'h5B202020;
mem['h02ED] <= 32'h52205D39;
mem['h02EE] <= 32'h73206E75;
mem['h02EF] <= 32'h6C706D69;
mem['h02F0] <= 32'h69747369;
mem['h02F1] <= 32'h65622063;
mem['h02F2] <= 32'h6D68636E;
mem['h02F3] <= 32'h0A6B7261;
mem['h02F4] <= 32'h00000000;
mem['h02F5] <= 32'h6D6D6F43;
mem['h02F6] <= 32'h3E646E61;
mem['h02F7] <= 32'h00000020;
end
always @(posedge clk)
mem_data <= mem[mem_addr];
// ============================================================================
reg o_ready;
always @(posedge clk or negedge rstn)
if (!rstn) o_ready <= 1'd0;
else o_ready <= valid && ((addr & MEM_ADDR_MASK) != 0);
// Output connectins
assign ready = o_ready;
assign rdata = mem_data;
assign mem_addr = addr[MEM_SIZE_BITS+1:2];
endmodule
regression/issue_00870/top.v 0 → 100644
module mux1( select, d, q );
input select;
input[1:0] d;
output q;
wire q;
wire select;
wire[1:0] d;
assign q = d[select];
endmodule
module top(select, d, q);
input[1:0] select;
input[1:0] d;
output q;
wire q;
wire[1:0] select;
wire[1:0] d;
wire[1:0] q_tmp;
mux1 m1(
.select(select[0]),
.d(d),
.q(q_tmp[0])
);
mux1 m2(
.select(select[1]),
.d(d),
.q(q_tmp[1])
);
mux1 m3(
.select(select[0]),
.d(q_tmp),
.q(q)
);
endmodule
regression/issue_00873/top.v 0 → 100644
module template (input clk, input d, output reg q);
parameter neg_clk = 0;
initial q = 1'b1;
generate
if (neg_clk) begin
always @(negedge clk) q <= d;
end
else begin
always @(posedge clk) q <= d;
end
endgenerate
endmodule
module top(input clk, input d, output [1:0] q);
template #(.neg_clk(1)) neg_clk(clk, d, q[0]);
template #(.neg_clk(0)) pos_clk(clk, d, q[1]);
endmodule
regression/issue_00888/top.v 0 → 100644
module top (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 1;
parameter DATAWIDTH = 2;
input CLK, CE;
input [DATAWIDTH-1:0] SI;
input [SELWIDTH-1:0] SEL;
output [DATAWIDTH-1:0] DO;
localparam DATADEPTH = 2**SELWIDTH;
reg [0:DATADEPTH-1] data1 [DATAWIDTH-1:0];
reg [DATADEPTH-1:0] data2 [DATAWIDTH-1:0];
generate
genvar i;
for (i = 0; i < DATAWIDTH; i=i+1) begin
always @(posedge CLK)
begin
if (CE == 1'b1) begin
`ifdef BROKEN
data1[i] <= {SI[i], data1[i][0:DATADEPTH-2]};
`else
data2[i] <= {data2[i][DATADEPTH-2:0], SI[i]};
`endif
end
end
`ifdef BROKEN
assign DO[i] = data1[i][SEL];
`else
assign DO[i] = data2[i][SEL];
`endif
end
endgenerate
endmodule
regression/issue_00922/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
/*initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end*/
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
regression/issue_00931/top.v 0 → 100644
module top (
input [1:0] S,
input [7:0] A, B, C, D,
output reg [7:0] Y
);
always @* begin
case (S)
2'b00: Y <= A;
2'b01: Y <= B;
2'b10: Y <= C;
2'b11: Y <= D;
endcase
end
endmodule
regression/run.sh
#!/bin/bash
set -ex
set -x
test -d $1
test -f scripts/$2.ys
......@@ -8,6 +8,7 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
# cases where 'syntax error' or other errors are expected
if [ "$1" = "issue_00089" ] ||\
......@@ -41,12 +42,12 @@ if [ "$1" = "issue_00089" ] ||\
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
if grep "$expected_string" yosys.log; then
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
else
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
fi
fi
......@@ -73,7 +74,13 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00835" ] ||\
[ "$1" = "issue_00857" ] ||\
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00865" ]; then
[ "$1" = "issue_00865" ] ||\
[ "$1" = "issue_00867" ] ||\
[ "$1" = "issue_00870" ] ||\
[ "$1" = "issue_00873" ] ||\
[ "$1" = "issue_00888" ] ||\
[ "$1" = "issue_00922" ] ||\
[ "$1" = "issue_00931" ]; then
expected_string=""
expected="1"
......@@ -91,7 +98,8 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00689" ] ||\
[ "$1" = "issue_00708" ] ||\
[ "$1" = "issue_00826" ] ||\
[ "$1" = "issue_00862" ]; then
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00870" ]; then
expected_string="Successfully finished Verilog frontend"
elif [ "$1" = "issue_00655" ]; then
expected_string="Executing EDIF backend"
......@@ -117,31 +125,55 @@ elif [ "$1" = "issue_00502" ] ||\
expected_string="_DFF_P_ 1"
elif [ "$1" = "issue_00865" ]; then
expected_string="FDRE 14"
elif [ "$1" = "issue_00867" ]; then
expected_string="RAMB36E1 1"
elif [ "$1" = "issue_00873" ]; then
expected_string="has an unprocessed 'init' attribute."
expected="0"
elif [ "$1" = "issue_00888" ]; then
expected_string="FDRE 4"
elif [ "$1" = "issue_00922" ]; then
expected_string="ERROR: Unclocked write port 0 on memory top.ram."
expected="0"
elif [ "$1" = "issue_00931" ]; then
expected_string="Number of cells: 5"
fi
yosys -ql yosys.log ../../scripts/$2.ys;
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if grep "$expected_string" result.log; then
if [ $expected = "1" ]; then
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
else
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
fi
else
if [ $expected = "1" ]; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
fi
# cases with simulation checks
else
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
TECHLIBS_PREFIX=../../../../../techlibs
else
COMMON_PREFIX=/usr/local/share/yosys
TECHLIBS_PREFIX=/usr/local/share/yosys
fi
iverilog_adds=""
#Additional sources for iverilog simulation
if [ "$1" = "issue_00084" ]; then
iverilog_adds="../../../../../techlibs/xilinx/brams_bb.v"
iverilog_adds="$TECHLIBS_PREFIX/xilinx/brams_bb.v"
elif [ "$1" = "issue_00160" ] ||\
[ "$1" = "issue_00182" ] ||\
[ "$1" = "issue_00183" ] ||\
......@@ -149,20 +181,32 @@ else
[ "$1" = "issue_00567" ] ||\
[ "$1" = "issue_00589" ] ||\
[ "$1" = "issue_00628" ]; then
iverilog_adds="../../../../../techlibs/ice40/cells_sim.v"
iverilog_adds="$TECHLIBS_PREFIX/ice40/cells_sim.v"
elif [ "$1" = "pr_00896" ]; then
iverilog_adds="../../../../../techlibs/ecp5/cells_sim.v"
iverilog_adds="$TECHLIBS_PREFIX/ecp5/cells_sim.v"
fi
yosys -ql yosys.log ../../scripts/$2.ys
iverilog -o testbench ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v $iverilog_adds
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo fail > ${1}_${2}.status
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
fi
......
regression/scripts/issue_00867.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -flatten
tee -o result.log stat
regression/scripts/issue_00870.ys 0 → 100644
read_verilog ../top.v
hierarchy -auto-top -check;
proc; clean;
memory;
opt -full;
flatten;
write_verilog multimux_out_1.v
opt -full;
write_verilog multimux_out_2.v
delete;
tee -o result.log read_verilog multimux_out_2.v
regression/scripts/issue_00873.ys 0 → 100644
tee -a result.log read_verilog ../top.v
tee -a result.log synth_xilinx
tee -a result.log flatten
tee -a result.log dump top
regression/scripts/issue_00888.ys 0 → 100644
read_verilog ../top.v
tee -a result.log synth_xilinx
regression/scripts/issue_00922.ys 0 → 100644
read_verilog ../top.v
proc
memory_dff -nordff
memory_collect
opt_reduce
clean
tee -a result.log write_firrtl firrtl.firrtl
regression/scripts/issue_00931.ys 0 → 100644
read_verilog ../top.v
tee -a result.log prep
report.py 0 → 100755
#!/usr/bin/env python3
import os, time
from pathlib import Path
def getListOfFiles(dirName):
listOfFile = os.listdir(dirName)
allFiles = list()
for entry in listOfFile:
fullPath = os.path.join(dirName, entry)
if os.path.isdir(fullPath):
allFiles = allFiles + getListOfFiles(fullPath)
else:
if Path(fullPath).suffix==".status":
allFiles.append(fullPath)
return allFiles
def main():
listOfFiles = getListOfFiles('.')
listOfFiles.sort()
testsuits = list()
casenumber = dict()
errors = dict()
failures = dict()
total_errors = 0
total_failures = 0
min_start_time = time.time()
max_end_time = 0
for elem in listOfFiles :
st = elem.split('/')
testsuit = st[1]
testcase = st[-1].replace('.status','')
if (testsuit not in testsuits):
testsuits.append(testsuit)
casenumber[testsuit] = 0
errors[testsuit] = 0
failures[testsuit] = 0
casenumber[testsuit] += 1
status = open(elem, 'r').read().strip()
min_start_time = min(min_start_time, os.path.getmtime(os.path.join(os.path.dirname(elem),'.start')))
max_end_time = max(max_end_time, os.path.getmtime(os.path.join(os.path.dirname(elem),'.stamp')))
if (status=='ERROR'):
errors[testsuit] += 1
total_errors += 1
if (status=='FAIL'):
failures[testsuit] += 1
total_failures += 1
# Creating report
with open("report.xml", "w") as f:
print('<?xml version="1.0" encoding="UTF-8"?>', file=f)
print('<testsuites disabled="0" errors="%d" failures="%d" tests="%d" time="%d">' % (total_errors, total_failures, len(listOfFiles), max_end_time - min_start_time), file=f)
for suite in testsuits:
print(' <testsuite disabled="0" errors="%d" failures="%d" name="%s" skipped="0" tests="%d" time="%d">' % (errors[suite], failures[suite], suite, casenumber[suite], 0), file=f)
for elem in listOfFiles :
st = elem.split('/')
testsuit = st[1]
if (testsuit != suite):
continue
testcase = st[-1].replace('.status','')
casenumber[testsuit] += 1
status = open(elem, 'r').read().strip()
print(' <testcase classname="%s.%s" name="%s" status="%s" time="%d">' % (testsuit, st[2].replace('.status',''), testcase, status,
os.path.getmtime(os.path.join(os.path.dirname(elem),'.stamp')) - os.path.getmtime(os.path.join(os.path.dirname(elem),'.start'))), file=f)
if (status=='ERROR'):
print(' <error message="%s" type="%s"/>' % (status, status), file=f)
if (status=='FAIL'):
print(' <failure message="%s" type="%s"/>' % (status, status), file=f)
file_tb = os.path.join(os.path.dirname(elem),'testbench.log')
file_re = os.path.join(os.path.dirname(elem),'result.log')
file_ys = os.path.join(os.path.dirname(elem),'yosys.log')
if (os.path.isfile(file_tb)):
print('<system-out>', end="", file=f)
with open(file_tb, "r") as logf:
for line in logf:
print(line.replace("&", "&amp;").replace("<", "&lt;").replace(">", "&gt;").replace("\"", "&quot;"), end="", file=f)
print('</system-out>', file=f)
elif (os.path.isfile(file_re)):
print('<system-out>', end="", file=f)
with open(file_re, "r") as logf:
for line in logf:
print(line.replace("&", "&amp;").replace("<", "&lt;").replace(">", "&gt;").replace("\"", "&quot;"), end="", file=f)
print('</system-out>', file=f)
elif (os.path.isfile(file_ys)):
print('<system-out>', end="", file=f)
with open(file_ys, "r") as logf:
for line in logf:
print(line.replace("&", "&amp;").replace("<", "&lt;").replace(">", "&gt;").replace("\"", "&quot;"), end="", file=f)
print('</system-out>', file=f)
print(' </testcase>', file=f)
print(' </testsuite>', file=f)
print('</testsuites>', file=f)
if __name__ == '__main__':
main()
simple/Makefile
......@@ -154,7 +154,7 @@ $(eval $(call template,share_macc, share_force_macc share_aggressive_macc share_
#+ yosys -ql yosys.log ../../scripts/share_force.ys
#ERROR: Abort in passes/opt/share.cc:724.
#make: *** [Makefile:152: share_fsm/work_share_force/.stamp] Error 1
#$(eval $(call template,share_fsm, share share_force share_aggressive share_fast share_limit))
$(eval $(call template,share_fsm, share share_force share_aggressive share_fast share_limit))
#opt_expr
$(eval $(call template,opt_expr, opt_expr))
......
simple/async2sync/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/async2sync/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
simple/clk2fflogic/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/clk2fflogic/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
simple/dff2dffe_unmap/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/dff2dffs/testbench.v
......@@ -64,7 +64,7 @@ module testbench;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/extract/testbench.v
......@@ -64,7 +64,7 @@ module testbench;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
......
simple/flowmap/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/flowmap/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
simple/hierarchy/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/hierarchy/top.v
......@@ -47,7 +47,7 @@ module dffe
initial begin
q = Z;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
simple/hierarchy_huge/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/hierarchy_huge/top.v
......@@ -47,7 +47,7 @@ module dffe
initial begin
q = Z;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
simple/prep/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/prep/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
simple/run.sh
#!/bin/bash
set -ex
set -x
test -d $1
if [ "$2" != "verify" -a "$2" != "falsify" ]; then
......@@ -11,13 +11,35 @@ rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
if [ "$2" = "verify" ]; then
iverilog -o testbench ../testbench.v ../../common.v ../top.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
elif [ "$2" = "falsify" ]; then
iverilog -DBUG -o testbench ../testbench.v ../../common.v ../top.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
else
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
iverilog -o testbench ../testbench.v ../../common.v synth.v $(yosys-config --datdir/simcells.v)
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
fi
if [ "$2" = "falsify" ]; then
......@@ -26,7 +48,7 @@ if [ "$2" = "falsify" ]; then
elif ! grep 'ERROR' testbench.log || grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
else
if ! vvp -N testbench > testbench.log 2>&1; then
......@@ -35,7 +57,7 @@ else
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo pass > ${1}_${2}.status
echo PASS > ${1}_${2}.status
fi
fi
......
simple/synth/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/synth/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 0;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
simple/uniquify/testbench.v
......@@ -63,8 +63,8 @@ module testbench;
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
......
simple/uniquify/top.v
......@@ -35,7 +35,7 @@ module dffe
initial begin
q = 1'bZ;
end
always @( posedge clk, posedge en )
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
......
verific/opers/run.sh
#!/bin/bash
set -ex
set -x
trap "echo FAIL > $1.status" ERR
yosys -p "
......@@ -19,6 +19,11 @@ yosys -p "
miter -equiv -flatten A B miter
sat -verify -prove trigger 0 miter
"
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
echo PASS > $1.status
verific/sva/run.sh
#!/bin/bash
set -ex
set -x
test -f $1.sv
trap "echo FAIL > $1.status" ERR
......@@ -23,6 +23,11 @@ while read t; do
echo "$1.sv"
} > $1.$t.sby
sby -f $1.$t.sby
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
done < <( egrep '^module (pass|fail)_[0-9][0-9]' $1.sv | gawk '{ print $2; }'; )
echo PASS > $1.status
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