Review 'misc' test group (abc - eval)

misc_reviewed/.gitignore

+*/work_*/
+/.stamp
+/run-test.mk

misc_reviewed/Makefile

+PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
+
+all::
+
+run-test.mk: ../generate.py
+	@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
+
+include run-test.mk
+
+.PHONY: all clean

misc_reviewed/abc/abc.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc
+
+select -assert-count 3 t:$_NAND_
+select -assert-count 2 t:$_XOR_
+
+select -assert-none t:$_NAND_ t:$_XOR_ %% t:* %D

misc_reviewed/abc/abc_D.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc -D 2

misc_reviewed/abc/abc_S.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log abc -S 2

misc_reviewed/abc/abc_cannot_open_fail.pat

+ERROR: Can't open ABC output file

misc_reviewed/abc/abc_cannot_open_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out abc -liberty -constr
+ abc -liberty -constr

misc_reviewed/abc/abc_clk_domain_not_found_fail.pat

+ERROR: Clock domain u not found.

misc_reviewed/abc/abc_clk_domain_not_found_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out  abc -dff -clk u
+ abc -dff -clk u

misc_reviewed/abc/abc_constr_liberty.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out  abc -liberty  -constr top.lib

misc_reviewed/abc/abc_constr_no_liberty_fail.pat

+ERROR: Got -constr but no -liberty!

misc_reviewed/abc/abc_constr_no_liberty_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out abc -constr -liberty
+abc -constr -liberty

misc_reviewed/abc/abc_dff.ys

+read_verilog ../top_dff.v
+synth -top top
+dff2dffe
+tee -o result.log  abc -dff
+ abc -dff

misc_reviewed/abc/abc_dff_keepff.ys

+read_verilog ../top_dff.v
+synth -top top
+tee -o result.log  abc -keepff
+ abc -dff

misc_reviewed/abc/abc_div_mul.ys

+read_verilog ../top_div_mul.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc

misc_reviewed/abc/abc_ffs.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc

misc_reviewed/abc/abc_ffs_clk.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc -clk clk

misc_reviewed/abc/abc_fsm.ys

+read_verilog ../top_fsm.v
+synth -top top
+tee -o result.out abc

misc_reviewed/abc/abc_fsm_all.disable

+read_verilog ../top_fsm.v
+synth -top top
+tee -o result.out abc -g all

misc_reviewed/abc/abc_fsm_all.ys

+read_verilog ../top_fsm.v
+synth -top top
+tee -o result.out abc -g all

misc_reviewed/abc/abc_fsm_cmos4.ys

+read_verilog ../top_fsm.v
+synth -top top
+abc -g cmos4
+select -assert-count 6 t:$_AOI3_
+select -assert-count 1 t:$_AOI4_
+select -assert-count 2 t:$_OAI3_

misc_reviewed/abc/abc_fsm_gates.ys

+read_verilog ../top_fsm.v
+synth -top top
+abc -g gates

misc_reviewed/abc/abc_g_aig.ys

+read_verilog ../top.v
+synth -top top
+abc -g aig
+select -assert-count 2 t:$_AND_
+select -assert-count 3 t:$_NAND_
+select -assert-count 2 t:$_OR_

misc_reviewed/abc/abc_g_cmos.ys

+read_verilog ../top.v
+synth -top top
+abc -g cmos
+
+select -assert-count 1 t:$_NAND_
+select -assert-count 1 t:$_NOT_
+select -assert-count 1 t:$_OAI3_
+select -assert-count 2 t:$_XNOR_

misc_reviewed/abc/abc_g_cmos2.ys

+read_verilog ../top.v
+synth -top top
+abc -g cmos2
+
+select -assert-count 4 t:$_NAND_
+select -assert-count 5 t:$_NOR_
+select -assert-count 3 t:$_NOT_

misc_reviewed/abc/abc_g_simple.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc -g simple
+
+select -assert-count 2 t:$_AND_
+select -assert-count 1 t:$_OR_
+select -assert-count 2 t:$_NOT_

misc_reviewed/abc/abc_i.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -I 4
+ abc -dff

misc_reviewed/abc/abc_inv_luts_synt_fail.pat

+ERROR: Invalid -luts syntax.

misc_reviewed/abc/abc_inv_luts_synt_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out  abc -luts :
+ abc -liberty -luts :

misc_reviewed/abc/abc_logic.ys

+read_verilog ../top_logic.v
+proc
+synth -top top
+tee -o result.out abc

misc_reviewed/abc/abc_logic_loop.ys

+read_verilog ../top_logic_loop.v
+proc
+synth -top top
+tee -o result.out abc

misc_reviewed/abc/abc_lut.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -lut 4
+ abc -lut 3
+ stat

misc_reviewed/abc/abc_lut_liberty_fail.pat

+ERROR: Got -lut and -liberty! This two options are exclusive.

misc_reviewed/abc/abc_lut_liberty_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out  abc -lut 2 -liberty top.lib
+ abc -lut 2 -liberty top.lib

misc_reviewed/abc/abc_lut_neg.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -lut -4
+ abc -lut -3:1

misc_reviewed/abc/abc_luts.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -luts 3:4

misc_reviewed/abc/abc_markgroups.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+tee -o result.out abc -markgroups

misc_reviewed/abc/abc_mux.ys

+read_verilog ../top_mux.v
+proc
+synth -top top
+abc
+select -assert-count 139 t:$_MUX_

misc_reviewed/abc/abc_mux16.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.log abc -mux16
+stat

misc_reviewed/abc/abc_mux4.ys

+read_verilog ../top_mux.v
+synth -top top
+abc -mux4
+select -assert-count 75 t:$_MUX4_

misc_reviewed/abc/abc_mux8.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.log abc -mux8
+stat

misc_reviewed/abc/abc_mux_cmos3.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.out abc -g cmos3
+ abc -g cmos3
+select -assert-count 144 t:$_AOI3_
+select -assert-count 169 t:$_OAI3_

misc_reviewed/abc/abc_mux_cmos4.ys

+read_verilog ../top_mux.v
+synth -top top
+tee -o result.out abc -g cmos4
+ abc -g cmos4
+
+select -assert-count 111 t:$_AOI3_
+select -assert-count 28  t:$_AOI4_
+select -assert-count 111 t:$_AOI3_
+select -assert-count 24  t:$_OAI4_

misc_reviewed/abc/abc_no_proc.ys

+read_verilog ../top.v
+tee -o result.out abc

misc_reviewed/abc/abc_no_synth.ys

+read_verilog ../top.v
+proc
+tee -o result.out abc

misc_reviewed/abc/abc_p.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log  abc -P 4
+ abc -dff

misc_reviewed/abc/abc_return_code_fail.pat

+failed: return code 134.

misc_reviewed/abc/abc_return_code_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out abc -g XOR
+abc -g XOR

misc_reviewed/abc/abc_script_o_fail.pat

+ERROR: Can't open ABC output file

misc_reviewed/abc/abc_script_o_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out abc -script o
+abc -script o

misc_reviewed/abc/abc_script_top_fail.pat

+ERROR: Can't open ABC output file

misc_reviewed/abc/abc_script_top_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out abc -script top.yss
+abc -script top.yss

misc_reviewed/abc/abc_skip_module.ys

+read_verilog ../top_dff.v
+tee -o result.out abc

misc_reviewed/abc/abc_unsup_gate_type_fail.pat

+ERROR: Command syntax error: Unsupported gate type: XO

misc_reviewed/abc/abc_unsup_gate_type_fail.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.out abc -g XO
+abc -g XO

misc_reviewed/abc/top.lib

+

misc_reviewed/abc/top.v

+(* black_box *) module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule

misc_reviewed/abc/top_dff.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

misc_reviewed/abc/top_div_mul.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign cout = x / y * cin;
+
+endmodule

misc_reviewed/abc/top_fsm.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

misc_reviewed/abc/top_logic.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg A1,cout1,A2,cout2;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+
+always @(posedge x) begin
+    A2 <=  ~(y | cin);
+end
+always @(posedge x) begin
+    cout2 <= cin ~|y;
+end
+
+endmodule

misc_reviewed/abc/top_logic_loop.v

+module top
+(
+ input x,
+ input y,
+ input z,
+
+ output A,
+ output B
+ );
+
+ wire A1,B1,A2,B2;
+
+ assign A1 = x & A2;
+ assign A2 = A1 & y;
+ assign A = ~A2;
+
+endmodule

misc_reviewed/abc/top_mux.v

+module top (
+input [7:0] S,
+input [255:0] D,
+output M256
+);
+
+assign M256 = D[S];
+
+endmodule

misc_reviewed/abc9/abc9_D.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -D 2 -lut 2

misc_reviewed/abc9/abc9_W.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -W -lut 2

misc_reviewed/abc9/abc9_box.ys

+abc9 -box box.txt -lut 2

misc_reviewed/abc9/abc9_cant_open_output_file_fail.pat

+ERROR: Can't open ABC output file

misc_reviewed/abc9/abc9_cant_open_output_file_fail.ys

+read_verilog ../top.v
+abc9 -luts uu

misc_reviewed/abc9/abc9_dff.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+abc9 -lut 5
+abc9 -lut 5

misc_reviewed/abc9/abc9_dff_nomfs.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+synth -top top
+abc9 -lut 5 -nomfs
+abc9 -lut 5

misc_reviewed/abc9/abc9_dff_techmap.ys

+read_verilog ../top_dff.v
+proc
+dff2dffe
+techmap
+abc9 -lut 5
+abc9 -lut 5

misc_reviewed/abc9/abc9_fast.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -fast -lut 2

misc_reviewed/abc9/abc9_invalid_luts_syntax_fail.pat

+ERROR: Invalid -luts syntax.

misc_reviewed/abc9/abc9_invalid_luts_syntax_fail.ys

+read_verilog ../top.v
+abc9 -luts 2:2:2:/2

misc_reviewed/abc9/abc9_lut.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -lut 2

misc_reviewed/abc9/abc9_luts.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -luts 2,3,4

misc_reviewed/abc9/abc9_markgroups.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -markgroups -lut 2

misc_reviewed/abc9/abc9_mem.ys

+read_verilog ../top_mem.v
+proc
+dff2dffe
+synth -top top
+abc9 -D 2 -lut 2

misc_reviewed/abc9/abc9_mux.ys

+read_verilog ../top_mux.v
+proc
+synth -top top
+abc9 -lut 2

misc_reviewed/abc9/abc9_nocleanup.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -nocleanup -lut 2

misc_reviewed/abc9/abc9_script.ys

+abc9 -script box.txt -lut 2

misc_reviewed/abc9/abc9_showtmp.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+abc9 -showtmp -lut 2

misc_reviewed/abc9/abc9_techmap.ys

+read_verilog ../top_mux.v
+proc
+techmap
+abc9 -lut 2

misc_reviewed/abc9/abc9_wo_proc.ys

+read_verilog ../top_dff.v
+abc9 -lut 2

misc_reviewed/abc9/abc9_wo_synth.ys

+read_verilog ../top_mux.v
+proc
+abc9 -lut 2

misc_reviewed/abc9/top.lib

+

misc_reviewed/abc9/top.v

+(* black_box *) module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule

misc_reviewed/abc9/top_dff.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

misc_reviewed/abc9/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/abc9/top_mux.v

+module top (
+input [7:0] S,
+input [255:0] D,
+output M256
+);
+parameter i = 3;
+
+assign M256 = D[S];
+
+endmodule

misc_reviewed/add/add.pat

+wire width 0 \\w

misc_reviewed/add/add.ys

+read_verilog ../top.v
+add -wire w 0
+tee -o result.out dump

misc_reviewed/add/add_error_fail.pat

+ERROR: Found incompatible object with same name in module \\top2!

misc_reviewed/add/add_error_fail.ys

+read_verilog ../top.v
+add -input i 2
+add -wire i 2
+tee -o result.log dump

misc_reviewed/add/add_global_input.pat

+wire width 32000 input 6 \\gi

misc_reviewed/add/add_global_input.ys

+read_verilog ../top.v
+add -global_input gi 32000
+tee -o result.out dump

misc_reviewed/add/add_inout.pat

+wire width 3 inout 6 \\34

misc_reviewed/add/add_inout.ys

+read_verilog ../top.v
+ add -inout \34 3
+tee -o result.out dump

misc_reviewed/add/add_input.pat

+wire width 2 input 6 \\i

misc_reviewed/add/add_input.ys

+read_verilog ../top.v
+add -input i 2
+add -input i 2
+tee -o result.out dump

misc_reviewed/add/add_mod.pat

+module \\top3

misc_reviewed/add/add_mod.ys

+read_verilog ../top.v
+add -mod top3 -wire w 0
+tee -o result.out dump

misc_reviewed/add/add_output.pat

+wire width 3 output 6 \\o

misc_reviewed/add/add_output.ys

+read_verilog ../top.v
+add -output o 3
+tee -o result.out dump

misc_reviewed/add/add_wire.pat

+wire \\w

misc_reviewed/add/add_wire.ys

+read_verilog ../top.v
+add -wire w 1
+tee -o result.out dump

misc_reviewed/add/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule
+
+module top2
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin * y / x;
+
+endmodule

misc_reviewed/assertpmux/assertpmux.ys

+read_verilog ../top.v
+proc
+assertpmux
+tee -o result.log dump

misc_reviewed/assertpmux/assertpmux_always.ys

+read_verilog ../top.v
+proc
+assertpmux -always
+tee -o result.log dump

misc_reviewed/assertpmux/assertpmux_mux.ys

+read_verilog ../top_mux.v
+proc
+assertpmux
+tee -o result.log dump

misc_reviewed/assertpmux/assertpmux_noinit.ys

+read_verilog ../top.v
+proc
+assertpmux -noinit
+tee -o result.log dump

misc_reviewed/assertpmux/top.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

misc_reviewed/assertpmux/top_mux.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+     begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+            default: Y = 1'bx;
+        endcase
+     end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+     begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+            4 : Y = D[4];
+            5 : Y = D[5];
+            6 : Y = D[6];
+            7 : Y = D[7];
+            default: Y = 1'bx;
+        endcase
+     end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+reg Y;
+wire[3:0] S;
+wire[15:0] D;
+
+always @*
+     begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+            4 : Y = D[4];
+            5 : Y = D[5];
+            6 : Y = D[6];
+            7 : Y = D[7];
+            8 : Y = D[8];
+            9 : Y = D[9];
+            10 : Y = D[10];
+            11 : Y = D[11];
+            12 : Y = D[12];
+            13 : Y = D[13];
+            14 : Y = D[14];
+            15 : Y = D[15];
+            default: Y = 1'bx;
+        endcase
+     end
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

misc_reviewed/blackbox/blackbox.pat

+attribute \\blackbox 1
+attribute \\cells_not_processed 1
+attribute \\src "../top.v:1"
+module \\bb

misc_reviewed/blackbox/blackbox.ys

+read_verilog ../top.v
+blackbox bb
+tee -o result.out dump

misc_reviewed/blackbox/blackbox_mem.ys

+read_verilog ../top_mem.v
+blackbox top
+tee -o result.log dump

misc_reviewed/blackbox/blackbox_top.pat

+attribute \\blackbox 1
+attribute \\cells_not_processed 1
+attribute \\src "../top.v:15"
+module \\top

misc_reviewed/blackbox/blackbox_top.ys

+read_verilog ../top.v
+blackbox top
+tee -o result.out dump

misc_reviewed/blackbox/top.v

+module bb
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule
+
+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+bb u_bb (x,y,cin,A,cout);
+
+endmodule

misc_reviewed/blackbox/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/bugpoint/bugpoint_cells_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss -cells

misc_reviewed/bugpoint/bugpoint_clean_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss -clean

misc_reviewed/bugpoint/bugpoint_connections_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss -connections

misc_reviewed/bugpoint/bugpoint_do_not_crash_fail.pat

+ERROR: The provided script file and Yosys binary do not crash on this design!

misc_reviewed/bugpoint/bugpoint_do_not_crash_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss -connections

misc_reviewed/bugpoint/bugpoint_fast_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss -fast

misc_reviewed/bugpoint/bugpoint_fully_selected_des_fail.pat

+ERROR: This command only operates on fully selected designs!

misc_reviewed/bugpoint/bugpoint_fully_selected_des_fail.ys

+read_verilog ../top.v
+select bb
+tee -o result.log bugpoint  -script ../script.yss

misc_reviewed/bugpoint/bugpoint_grep_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint  -script ../script.yss -grep "Simplifications exhausted"

misc_reviewed/bugpoint/bugpoint_grep_string_not_found_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint  -script ../script.yss -grep "SSS"

misc_reviewed/bugpoint/bugpoint_missing_script_fail.pat

+ERROR: Missing -script option.

misc_reviewed/bugpoint/bugpoint_missing_script_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint

misc_reviewed/bugpoint/bugpoint_modules_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss -modules

misc_reviewed/bugpoint/bugpoint_ports_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss -ports

misc_reviewed/bugpoint/bugpoint_script_fail.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script ../script.yss

misc_reviewed/bugpoint/bugpoint_yosys.ys

+read_verilog ../top.v
+tee -o result.log bugpoint -script script.ys -yosys yosys.yss

misc_reviewed/bugpoint/script.yss

+read_verilog ../top2.v
+abc -g cmos4

misc_reviewed/bugpoint/top.v

+module bb
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+bb u_bb (x,y,cin,A,cout);
+
+endmodule

misc_reviewed/bugpoint/top2.v

+module bb2
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module top2
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+bb2 u_bb2 (x,y,cin,A,cout);
+
+endmodule

misc_reviewed/check/check.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.out check

misc_reviewed/check/check_assert.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.out check -assert

misc_reviewed/check/check_error_fail.pat

+ERROR: Found 1 problems in 'check -assert'.

misc_reviewed/check/check_error_fail.ys

+read_verilog -sv ../top1.v
+proc
+check -assert

misc_reviewed/check/check_initdrv.ys

+read_verilog -sv ../top1.v
+proc
+tee -o result.out check -initdrv

misc_reviewed/check/check_logic_loop.ys

+read_verilog -sv ../top_logic_loop.v
+proc
+tee -o result.out check

misc_reviewed/check/check_noinit.ys

+read_verilog -sv ../top1.v
+proc
+tee -o result.out check -noinit

misc_reviewed/check/top.v

+module top
+    ( input d, clk, output reg q );
+
+    wire u;
+
+
+	always @( posedge clk )
+            q <= d;
+endmodule

misc_reviewed/check/top1.v

+module top
+    ( input d, clk, output reg q );
+
+    wire u;
+    wire s;
+
+    assign u = s;
+
+	assign u = d;
+
+	assign u = clk;
+
+	always @( posedge clk )
+            q <= u;
+endmodule

misc_reviewed/check/top_logic_loop.v

+module top
+(
+ input x,
+ input y,
+ input z,
+
+ output A,
+ output B
+ );
+
+ wire A1,B1,A2,B2;
+
+ assign A1 = x & A2;
+ assign A2 = A1 & y;
+ assign A = ~A2;
+
+endmodule

misc_reviewed/chformal/chformal.ys

+read_verilog -sv ../top.v
+chformal -remove
+tee -o result.log dump

misc_reviewed/chformal/chformal_assert.ys

+read_verilog -sv ../top.v
+chformal -assert -remove
+tee -o result.log dump

misc_reviewed/chformal/chformal_assert2assume.ys

+read_verilog -sv ../top.v
+chformal -assert2assume
+tee -o result.log dump

misc_reviewed/chformal/chformal_assume.ys

+read_verilog -sv ../top.v
+chformal -assume -remove
+tee -o result.log dump

misc_reviewed/chformal/chformal_assume2assert.ys

+read_verilog -sv ../top.v
+chformal -assume2assert
+tee -o result.log dump

misc_reviewed/chformal/chformal_cover.ys

+read_verilog -sv ../top.v
+tee -o result.log chformal -cover -remove

misc_reviewed/chformal/chformal_delay.ys

+read_verilog -sv ../top.v
+tee -o result.log chformal -delay 2

misc_reviewed/chformal/chformal_dff.ys

+read_verilog -sv ../top_dff.v
+chformal -remove
+tee -o result.log dump

misc_reviewed/chformal/chformal_early.ys

+read_verilog -sv ../top.v
+tee -o result.log chformal -early

misc_reviewed/chformal/chformal_error_fail.pat

+ERROR: Mode option is missing.

misc_reviewed/chformal/chformal_error_fail.ys

+read_verilog -sv ../top.v
+chformal
+tee -o result.log dump

misc_reviewed/chformal/chformal_fair.ys

+read_verilog -sv ../top.v
+tee -o res dump
+chformal -fair -remove
+tee -o result.log dump

misc_reviewed/chformal/chformal_fair2live.ys

+read_verilog -sv ../top.v
+chformal -fair2live
+tee -o result.log dump

misc_reviewed/chformal/chformal_fair2live_assert2assume.ys

+read_verilog -sv ../top.v
+chformal -fair2live -assert2assume
+tee -o result.log dump

misc_reviewed/chformal/chformal_ff.ys

+read_verilog -sv ../top.v
+proc
+clk2fflogic
+chformal -early
+tee -o result.log dump

misc_reviewed/chformal/chformal_lat.ys

+read_verilog -sv ../top_lat.v
+chformal -remove
+tee -o result.log dump

misc_reviewed/chformal/chformal_live.ys

+read_verilog -sv ../top.v
+chformal -live -remove
+tee -o result.log dump

misc_reviewed/chformal/chformal_live2fair.ys

+read_verilog -sv ../top.v
+chformal -live2fair
+tee -o result.log dump

misc_reviewed/chformal/chformal_proc_early.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log chformal -early

misc_reviewed/chformal/chformal_skip.ys

+read_verilog -sv ../top.v
+tee -o result.log chformal -skip 2

misc_reviewed/chformal/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

misc_reviewed/chformal/top_dff.v

+module top
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule

misc_reviewed/chformal/top_lat.v

+module alat
+    ( input d, en, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @(*)
+		if ( clr )
+			q <= 1'b0;
+		else if (en)
+            q <= d;
+endmodule
+
+module alatn
+    ( input d, en, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @(*)
+		if ( !clr )
+			q <= 1'b0;
+		else if (!en)
+            q <= d;
+endmodule
+
+module latsr
+    ( input d, en, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @(*)
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else if ( en )
+            q <= d;
+endmodule
+
+module nlatsr
+    ( input d, en, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @(*)
+		if ( !clr )
+			q <= 1'b0;
+		else if ( !pre )
+			q <= 1'b1;
+		else if ( !en )
+            q <= d;
+endmodule
+
+module dlatchsr (EN, SET, CLR, D, Q);
+
+    input EN;
+    input SET, CLR, D;
+    output reg Q;
+
+    always @*
+        if (CLR)
+            Q = 0;
+        else if (SET)
+            Q = 1;
+        else if (EN)
+            Q = D;
+
+endmodule
+
+module top (
+input en,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3
+);
+
+latsr u_latsr (
+        .en (en ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+nlatsr u_nlatsr (
+        .en (en ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+alat u_alat (
+        .en (en ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+alatn u_alatn (
+        .en (en ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+endmodule

misc_reviewed/chparam/chparam.ys

+read_verilog ../top.v
+proc
+tee -o result.log chparam

misc_reviewed/chparam/chparam_error_fail.pat

+ERROR: The options -set and -list cannot be used together.

misc_reviewed/chparam/chparam_error_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log chparam -set X 2 -list top

misc_reviewed/chparam/chparam_list.pat

+middle:
+top:
+  X

misc_reviewed/chparam/chparam_list.ys

+read_verilog ../top.v
+proc
+chparam -set X 2 top
+tee -o result.out chparam -list
+

misc_reviewed/chparam/chparam_set.pat

+Parameter \\X = 2

misc_reviewed/chparam/chparam_set.ys

+read_verilog ../top.v
+proc
+tee -o result.out chparam -set X 2 top

misc_reviewed/chparam/chparam_top.ys

+read_verilog ../top.v
+proc
+tee -o result.log chparam top

misc_reviewed/chparam/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+ parameter X = 1;
+
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/chtype/chtype.ys

+read_verilog -sv ../top.v
+proc
+chtype

misc_reviewed/chtype/chtype_map.ys

+read_verilog -sv ../top.v
+proc
+chtype -map $dff $adff $2

misc_reviewed/chtype/chtype_selection.ys

+read_verilog -sv ../top.v
+proc
+chtype $2

misc_reviewed/chtype/chtype_set.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log chtype -set $adff $2

misc_reviewed/chtype/top.v

+module top
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule

misc_reviewed/connect/connect_cannot_parse_set_lhs_expr_fail.pat

+ERROR: Failed to parse set lhs expression `sdf'.

misc_reviewed/connect/connect_cannot_parse_set_lhs_expr_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log connect -set sdf sdf

misc_reviewed/connect/connect_cannot_parse_set_rhs_expr_fail.pat

+ERROR: Failed to parse set rhs expression `sdf'.

misc_reviewed/connect/connect_cannot_parse_set_rhs_expr_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log connect -set d sdf

misc_reviewed/connect/connect_cant_find_cell_fail.pat

+ERROR: Can't find cell $procddff$2.

misc_reviewed/connect/connect_cant_find_cell_fail.ys

+read_verilog -sv ../top.v
+proc
+connect -set d q
+tee -o result.log connect -port $procddff$2 D d

misc_reviewed/connect/connect_failed_parse_unset_fail.pat

+ERROR: Failed to parse unset expression `sdf'.

misc_reviewed/connect/connect_failed_parse_unset_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log connect -unset sdf

misc_reviewed/connect/connect_failed_to_parse_port_expr_fail.pat

+ERROR: Failed to parse port expression `dd'.

misc_reviewed/connect/connect_failed_to_parse_port_expr_fail.ys

+read_verilog -sv ../top.v
+proc
+connect -set d q
+tee -o result.log connect -port $procdff$2 D dd

misc_reviewed/connect/connect_found_process_fail.pat

+ERROR: Found processes in selected module.

misc_reviewed/connect/connect_found_process_fail.ys

+read_verilog -sv ../top.v
+tee -o result.log connect -unset d q

misc_reviewed/connect/connect_multiple_modules_fail.pat

+ERROR: Multiple modules selected: top2, top

misc_reviewed/connect/connect_multiple_modules_fail.ys

+read_verilog -sv ../top_2.v
+proc
+tee -o result.log connect -unset d q

misc_reviewed/connect/connect_no_modules_fail.pat

+ERROR: No modules selected.

misc_reviewed/connect/connect_no_modules_fail.ys

+tee -o result.log connect -unset d q

misc_reviewed/connect/connect_nomap_port.pat

+connect \\D \\d1

misc_reviewed/connect/connect_nomap_port.ys

+read_verilog -sv ../top.v
+proc
+connect -nomap -port $procdff$2 D d1
+tee -o result.out dump

misc_reviewed/connect/connect_nomap_set.pat

+connect \\d1 \\q

misc_reviewed/connect/connect_nomap_set.ys

+read_verilog -sv ../top.v
+proc
+connect -nomap -set d1 q
+tee -o result.out dump

misc_reviewed/connect/connect_nomap_unset.pat

+wire $auto$connect.cc:33:unset_drivers$3

misc_reviewed/connect/connect_nomap_unset.ys

+read_verilog -sv ../top.v
+proc
+connect -nomap -unset d q
+tee -o result.out dump

misc_reviewed/connect/connect_nounset_set.pat

+connect \\d1 \\q

misc_reviewed/connect/connect_nounset_set.ys

+read_verilog -sv ../top.v
+proc
+connect -nounset -set d1 q
+tee -o result.out dump

misc_reviewed/connect/connect_opt_expected_fail.pat

+ERROR: Expected -set, -unset, or -port.

misc_reviewed/connect/connect_opt_expected_fail.ys

+read_verilog -sv ../top.v
+proc
+connect -set d q
+tee -o result.log connect

misc_reviewed/connect/connect_port.pat

+connect \\D \\d1

misc_reviewed/connect/connect_port.ys

+read_verilog -sv ../top.v
+proc
+connect -port $procdff$2 D d1
+tee -o result.out dump

misc_reviewed/connect/connect_port_with_nounset_fail.pat

+ERROR: Can't use -port together with -nounset.

misc_reviewed/connect/connect_port_with_nounset_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log connect -port $procdff$2 D d -nounset d

misc_reviewed/connect/connect_set.pat

+connect \\d1 \\q

misc_reviewed/connect/connect_set.ys

+read_verilog -sv ../top.v
+proc
+connect -set d1 q
+tee -o result.out dump

misc_reviewed/connect/connect_set_with_port_fail.pat

+ERROR: Can't use -set together with -unset and/or -port.

misc_reviewed/connect/connect_set_with_port_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log connect -set d q -port $procdff$2 D d

misc_reviewed/connect/connect_set_with_unset_and_port_fail.pat

+ERROR: Can't use -set together with -unset and/or -port.

misc_reviewed/connect/connect_set_with_unset_and_port_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log connect -set d q -unset d -port $procdff$2 D d

misc_reviewed/connect/connect_set_with_unset_fail.pat

+ERROR: Can't use -set together with -unset and/or -port.

misc_reviewed/connect/connect_set_with_unset_fail.ys

+read_verilog -sv ../top.v
+proc
+tee -o result.log connect -set d q -unset d

misc_reviewed/connect/connect_unset.pat

+  connect $auto$connect.cc:33:unset_drivers$4 \\q

misc_reviewed/connect/connect_unset.ys

+read_verilog -sv ../top.v
+proc
+connect -set d1 q
+connect -unset d1 q
+tee -o result.out dump

misc_reviewed/connect/connect_unset_with_nounset_and_port_fail.pat

+ERROR: Can't use -unset together with -port and/or -nounset.

misc_reviewed/connect/connect_unset_with_nounset_and_port_fail.ys

+read_verilog -sv ../top.v
+proc
+connect -set d q
+tee -o result.log connect -unset d -port $procdff$2 D d -nounset d

misc_reviewed/connect/connect_unset_with_nounset_fail.pat

+ERROR: Can't use -unset together with -port and/or -nounset.

misc_reviewed/connect/connect_unset_with_nounset_fail.ys

+read_verilog -sv ../top.v
+proc
+connect -set d q
+tee -o result.log connect -unset d -nounset d

misc_reviewed/connect/connect_unset_with_port_fail.pat

+ERROR: Can't use -unset together with -port and/or -nounset.

misc_reviewed/connect/connect_unset_with_port_fail.ys

+read_verilog -sv ../top.v
+proc
+connect -set d q
+tee -o result.log connect -unset d -port $procdff$2 D d

misc_reviewed/connect/top.v

+module top
+    ( input d, d1, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule

misc_reviewed/connect/top_2.v

+module top
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule
+
+module top2
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule

misc_reviewed/connwrappers/connwrappers.ys

+read_verilog ../top.v
+proc
+connwrappers

misc_reviewed/connwrappers/connwrappers_port.ys

+read_verilog ../top.v
+proc
+connwrappers -port $dff d1 32000 1

misc_reviewed/connwrappers/connwrappers_signed.ys

+read_verilog ../top.v
+proc
+connwrappers -signed $dff d 3

misc_reviewed/connwrappers/connwrappers_unsigned.ys

+read_verilog ../top.v
+proc
+connwrappers -unsigned $dff d 0

misc_reviewed/connwrappers/top.v

+module top
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule

misc_reviewed/cover/cover.ys

+read_verilog ../top.v
+tee -o result.log cover

misc_reviewed/cover/cover_a.ys

+read_verilog ../top.v
+tee -o result.log cover -a out.txt

misc_reviewed/cover/cover_cant_create_file_fail.pat

+ERROR: Can't create file aa/out.txt.

misc_reviewed/cover/cover_cant_create_file_fail.ys

+read_verilog ../top.v
+tee -o result.log cover -o aa/out.txt

misc_reviewed/cover/cover_dir.ys

+read_verilog ../top.v
+tee -o result.log cover -d ../test

misc_reviewed/cover/cover_dir_fail.pat

+ERROR: Can't create file in directory test.

misc_reviewed/cover/cover_dir_fail.ys

+read_verilog ../top.v
+tee -o result.log cover -d test

misc_reviewed/cover/cover_o.ys

+read_verilog ../top.v
+tee -o result.log cover -o out.txt

misc_reviewed/cover/cover_q.ys

+read_verilog ../top.v
+tee -o result.log cover -q

misc_reviewed/cover/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule

misc_reviewed/cutpoint/cutpoint.ys

+read_verilog ../top.v
+tee -o result.log cutpoint top/y top/x top/cout top/A top/cin
+tee -o result.log cutpoint top
+

misc_reviewed/cutpoint/cutpoint_asserts.ys

+read_verilog -sv ../top_asserts.v
+tee -o result.log cutpoint top/y top/x top/cout top/A top/cin
+tee -o result.log cutpoint -undef top/cin
+tee -o result.log cutpoint top/$auto$cutpoint.cc:70:execute$53
+dump
+

misc_reviewed/cutpoint/cutpoint_undef.ys

+read_verilog ../top.v
+tee -o result.log cutpoint top/y top/x top/cout top/A
+tee -o result.log cutpoint -undef top/cin
+tee -o result.log cutpoint -undef top

misc_reviewed/cutpoint/top.v

+module bb
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+
+assign {cout,A} =  cin + y + x;
+
+endmodule
+
+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+bb u_bb (x,y,cin,A,cout);
+
+endmodule

misc_reviewed/cutpoint/top_asserts.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+
+endmodule

misc_reviewed/debug/debug.ys

+debug read_verilog ../top.v
+debug proc
+tee -o result.log debug synth -top top

misc_reviewed/debug/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+assign {cout,A} =  cin + y + x;
+
+endmodule

misc_reviewed/delete/delete.ys

+read_verilog ../top.v
+delete middle
+tee -o result.log dump

misc_reviewed/delete/delete_cell.ys

+read_verilog ../top.v
+delete top/$2
+tee -o result.log dump

misc_reviewed/delete/delete_input.ys

+read_verilog ../top.v
+tee -o res.log dump
+delete -input top/x
+tee -o result.log dump

misc_reviewed/delete/delete_mem.ys

+read_verilog ../top_mem.v
+delete top/$memrd$\ram$../top.v:30$7
+tee -o result.log dump

misc_reviewed/delete/delete_memory.ys

+read_verilog ../top_mem.v
+proc
+memory
+delete top/$memrd$\ram$../top.v:30$7
+tee -o result.log dump

misc_reviewed/delete/delete_output.ys

+read_verilog ../top.v
+delete -output middle/o
+tee -o result.log dump

misc_reviewed/delete/delete_port.ys

+read_verilog ../top.v
+delete -port top/A
+tee -o result.log dump

misc_reviewed/delete/delete_proc.ys

+read_verilog ../top.v
+tee -o resul.log dump
+delete top/$1
+tee -o result.log dump

misc_reviewed/delete/delete_wire.ys

+read_verilog ../top.v
+tee -o resul.log dump
+delete top/o
+tee -o result.log dump

misc_reviewed/delete/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input ux,
+	input y,
+	output o
+);
+
+assign o = ux + y;
+endmodule

misc_reviewed/delete/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

misc_reviewed/design/design_as.ys

+read_verilog -sv ../top.v
+proc
+design -save first
+design -copy-from first -as top_2 top
+design -copy-to first -as top_2 top

misc_reviewed/design/design_copy_from.ys

+read_verilog -sv ../top.v
+proc
+design -save first
+design -reset
+design -copy-from first top

misc_reviewed/design/design_copy_to.ys

+read_verilog -sv ../top.v
+proc
+design -save first
+design -reset
+design -copy-to first top

misc_reviewed/design/design_copy_to_no_saved_des.ys

+design -copy-to first top

misc_reviewed/design/design_import.ys

+read_verilog -sv ../top.v
+proc
+design -save first
+design -import first top

misc_reviewed/design/design_no_pushed_design_fail.pat

+ERROR: No pushed designs.

misc_reviewed/design/design_no_pushed_design_fail.ys

+read_verilog -sv ../top.v
+proc
+design -pop

misc_reviewed/design/design_no_saved_design_copy_from_fail.pat

+ERROR: No saved design 'first' found!

misc_reviewed/design/design_no_saved_design_copy_from_fail.ys

+read_verilog -sv ../top.v
+proc
+design -copy-from first -as top_2 top

misc_reviewed/design/design_no_saved_design_import_fail.pat

+ERROR: No saved design 'first' found!

misc_reviewed/design/design_no_saved_design_import_fail.ys

+read_verilog -sv ../top.v
+proc
+design -import first top

misc_reviewed/design/design_no_saved_design_load_fail.pat

+ERROR: No saved design 'first' found!

misc_reviewed/design/design_no_saved_design_load_fail.ys

+read_verilog -sv ../top.v
+proc
+design -load first

misc_reviewed/design/design_no_top_module_fail.pat

+ERROR: No top module found in source design.

misc_reviewed/design/design_no_top_module_fail.ys

+read_verilog -sv ../top.v
+design -save first
+design -import first

misc_reviewed/design/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+always @(posedge cin)
+	A <= o;
+
+
+middle u_mid (.x(x),.o(o));
+u_rtl inst_u_rtl (.x(x),.o(o));
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/echo/echo.ys

+echo

misc_reviewed/echo/echo_off.ys

+echo off

misc_reviewed/echo/echo_on.ys

+echo on

misc_reviewed/echo/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (x,y,o);
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/edgetypes/edgetypes.pat

+$_DFF_P_.Q $_XOR_.A
+$_XOR_.Y $_DFF_N_.D
+$_XOR_.Y $_DFF_P_.D

misc_reviewed/edgetypes/edgetypes.ys

+read_verilog ../top.v
+synth
+tee -o result.out edgetypes

misc_reviewed/edgetypes/edgetypes_fulladder.pat

+$_ANDNOT_.Y $_OR_.A
+$_AND_.Y $_OR_.B
+$_XNOR_.Y $_ANDNOT_.B
+$_XNOR_.Y $_XNOR_.A

misc_reviewed/edgetypes/edgetypes_fulladder.ys

+read_verilog ../top_fulladder.v
+edgetypes
+synth
+tee -o result.out edgetypes

misc_reviewed/edgetypes/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+        cout <=  y + A;
+end
+
+endmodule

misc_reviewed/edgetypes/top_fulladder.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc_reviewed/eval/eval.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval middle

misc_reviewed/eval/eval_brute_force_equiv_checker.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -brute_force_equiv_checker_x top top

misc_reviewed/eval/eval_cant_find_input_fail.pat

+ERROR: Can't find input s in module middle!

misc_reviewed/eval/eval_cant_find_input_fail.ys

+read_verilog ../top_err_1.v
+tee -o result.log eval -vloghammer_report mid dle s 1
+

misc_reviewed/eval/eval_cant_find_mod_1_fail.pat

+ERROR: Can't find module `\\u'!

misc_reviewed/eval/eval_cant_find_mod_1_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -brute_force_equiv_checker u top
+

misc_reviewed/eval/eval_cant_find_mod_2_fail.pat

+ERROR: Can't find module `\\u'!

misc_reviewed/eval/eval_cant_find_mod_2_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -brute_force_equiv_checker top u
+

misc_reviewed/eval/eval_cant_find_mod_in_curr_des_fail.pat

+ERROR: Can't find module dle in current design!

misc_reviewed/eval/eval_cant_find_mod_in_curr_des_fail.ys

+read_verilog ../top.v
+tee -o result.log eval -vloghammer_report middle dle x 1
+

misc_reviewed/eval/eval_diff_lhs_rhs_sizes_fail.pat

+ERROR: Set expression with different lhs and rhs sizes:

misc_reviewed/eval/eval_diff_lhs_rhs_sizes_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set x 1 -set y 2'b11 u_rtl
+

misc_reviewed/eval/eval_empty_selection_fail.pat

+ERROR: Can't perform EVAL on an empty selection!

misc_reviewed/eval/eval_empty_selection_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval u

misc_reviewed/eval/eval_failed_to_parse_lhs_fail.pat

+ERROR: Failed to parse lhs set expression `u'.

misc_reviewed/eval/eval_failed_to_parse_lhs_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set u 0 middle

misc_reviewed/eval/eval_failed_to_parse_pattern_fail.pat

+ERROR: Failed to parse pattern d!

misc_reviewed/eval/eval_failed_to_parse_pattern_fail.ys

+read_verilog ../top.v
+tee -o result.log eval -vloghammer_report mid dle x d
+

misc_reviewed/eval/eval_failed_to_parse_rhs_fail.pat

+ERROR: Failed to parse rhs set expression `u'.

misc_reviewed/eval/eval_failed_to_parse_rhs_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set x u middle

misc_reviewed/eval/eval_failed_to_parse_show_expr_fail.pat

+ERROR: Failed to parse show expression `u'.

misc_reviewed/eval/eval_failed_to_parse_show_expr_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -show u middle
+

misc_reviewed/eval/eval_failed_to_parse_table_expr_fail.pat

+ERROR: Failed to parse table expression `u'.

misc_reviewed/eval/eval_failed_to_parse_table_expr_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -table u middle
+

misc_reviewed/eval/eval_has_no_counterpart_fail.pat

+ERROR: Port \\cout in module 1 has no counterpart in module 2!

misc_reviewed/eval/eval_has_no_counterpart_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -brute_force_equiv_checker top u_rtl
+

misc_reviewed/eval/eval_mods_arent_equiv_fail.pat

+ERROR: Modules are not equivalent!

misc_reviewed/eval/eval_mods_arent_equiv_fail.ys

+read_verilog ../top_err_1.v
+proc
+tee -o result.log eval -brute_force_equiv_checker middle u_rtl
+

misc_reviewed/eval/eval_no_output_wire_fail.pat

+ERROR: No output wire (y) found in module middle!

misc_reviewed/eval/eval_no_output_wire_fail.ys

+read_verilog ../top_err_1.v
+tee -o result.log eval -vloghammer_report mid dle x 1
+

misc_reviewed/eval/eval_only_one_module_fail.pat

+ERROR: Only one module must be selected for the EVAL pass! (selected: u_rtl and middle)

misc_reviewed/eval/eval_only_one_module_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval

misc_reviewed/eval/eval_pattern_is_to_short_fail.pat

+ERROR: Pattern 1'b1 is to short!

misc_reviewed/eval/eval_pattern_is_to_short_fail.ys

+read_verilog ../top_err_2.v
+tee -o result.log eval -vloghammer_report mid dle x 1'b1
+

misc_reviewed/eval/eval_port_doesnt_match_fail.pat

+ERROR: Port \\o in module 1 does not match its counterpart in module 2!

misc_reviewed/eval/eval_port_doesnt_match_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -brute_force_equiv_checker u_rtl top
+

misc_reviewed/eval/eval_rhs_expr_fail.pat

+ERROR: Right-hand-side set expression `x' is not constant.

misc_reviewed/eval/eval_rhs_expr_fail.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set x 1 -set y x u_rtl
+

misc_reviewed/eval/eval_set.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set x 1 -set y 0 middle

misc_reviewed/eval/eval_set_undef.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set-undef middle

misc_reviewed/eval/eval_show.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set x 1 -set y 0 -show o middle

misc_reviewed/eval/eval_show_not_set.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -show o middle

misc_reviewed/eval/eval_table.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -table o middle

misc_reviewed/eval/eval_table_set.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -set-undef -table o middle

misc_reviewed/eval/eval_two_distinct_solutions_fail.pat

+ERROR: Found two distinct solutions to SAT problem.

misc_reviewed/eval/eval_two_distinct_solutions_fail.ys

+read_verilog ../top_err_3.v
+tee -o result.log eval -vloghammer_report u_ rtl x 1'b1
+

misc_reviewed/eval/eval_vloghammer_report.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -vloghammer_report mid dle x 1

misc_reviewed/eval/eval_vloghammer_report_rtl.ys

+read_verilog ../top.v
+proc
+tee -o result.log eval -vloghammer_report u_ rtl y 1

misc_reviewed/eval/eval_wire_isnt_an_input_fail.pat

+ERROR: Wire w in module middle is not an input!

misc_reviewed/eval/eval_wire_isnt_an_input_fail.ys

+read_verilog ../top.v
+tee -o result.log eval -vloghammer_report mid dle w 1
+

misc_reviewed/eval/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o),.y(1'b0));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+wire w;
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/eval/top_err_1.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+ wire w;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o),.y(1'b0));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+//	input y,
+	output o
+);
+
+assign o = x;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/eval/top_err_2.v

+module top
+(
+ input [7:0] x,
+ input[7:0] y,
+ input cin,
+
+ output reg [7:0] A,
+ output [7:0] cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle #(7) u_mid (.x(x),.o(o),.y(1'b0));
+middle #(0) u_mid2 (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	x,
+	y,
+	o
+);
+
+parameter u = 7;
+
+input [u:0] x;
+input [u:0] y;
+output  [u:0] o;
+
+assign o = x + y;
+endmodule
+
+module xiddle
+(
+	input [1:0] x,
+	input y,
+	output [1:0] o
+);
+
+assign o = x + y;
+endmodule

misc_reviewed/eval/top_err_3.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle u_mid (.x(x),.o(o),.y(1'b0));
+u_rtl inst_u_rtl (.x(x),.o(o));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+wire w;
+
+assign o = x + y;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule