fix ordering of and outputs

eb908b8d · Zachary Snow · a1705363 · eb908b8d
Commit eb908b8d authored Sep 13, 2020 by Zachary Snow
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src/Language/SystemVerilog/Parser/Parse.y
+1 -1

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--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -781,7 +781,7 @@ NOutputGate :: { (Expr, Identifier, [LHS], Expr) }
  : DelayControlOrNil opt(Identifier) "(" NOutputGateItems { ($1, fromMaybe "" $2, fst $4, snd $4) }
 NOutputGateItems :: { ([LHS], Expr) }
  : Expr ")" { ([], $1) }
-  | Expr "," NOutputGateItems { (fst $3 ++ [toLHS $1], snd $3) }
+  | Expr "," NOutputGateItems { (toLHS $1 : fst $3, snd $3) }
 DelayControlOrNil :: { Expr }
  : DelayControl { $1 }
  | {- empty -} { Nil }