support wait statements

CHANGELOG.md

@@ -9,6 +9,7 @@
 
 * Added support for attributes in unary, binary, and ternary expressions
 * Added support for shadowing interface names with local typenames
+* Added support for passing through `wait` statements
 
 ### Bug Fixes
 

src/Convert/Traverse.hs

@@ -256,6 +256,7 @@ traverseSinglyNestedStmtsM fullMapper = cs
         cs (Subroutine expr exprs) = return $ Subroutine expr exprs
         cs (Trigger blocks x) = return $ Trigger blocks x
         cs stmt@Force{} = return stmt
+        cs (Wait e stmt) = fullMapper stmt >>= return . Wait e
         cs (Assertion a) =
             traverseAssertionStmtsM fullMapper a >>= return . Assertion
         cs (Continue) = return Continue
@@ -710,6 +711,8 @@ traverseStmtExprsM exprMapper = flatStmtMapper
         l' <- lhsMapper l
         e' <- exprMapper e
         return $ Force kw l' e'
+    flatStmtMapper (Wait e stmt) =
+        exprMapper e >>= \e' -> return $ Wait e' stmt
     flatStmtMapper (Assertion a) =
         traverseAssertionExprsM exprMapper a >>= return . Assertion
     flatStmtMapper (Continue) = return Continue

src/Language/SystemVerilog/AST/Stmt.hs

@@ -53,6 +53,7 @@ data Stmt
     | Trigger Bool Identifier
     | Assertion Assertion
     | Force Bool LHS Expr
+    | Wait Expr Stmt
     | Continue
     | Break
     | Null
@@ -106,6 +107,7 @@ instance Show Stmt where
                 (True , False) -> "release"
                 (False, True ) -> "assign"
                 (False, False) -> "deassign"
+    show (Wait      e s) = printf "wait (%s)%s" (show e) (showShortBranch s)
     show (Continue     ) = "continue;"
     show (Break        ) = "break;"
     show (Null         ) = ";"

src/Language/SystemVerilog/Parser/Parse.y

@@ -1149,6 +1149,7 @@ StmtNonBlock :: { Stmt }
   | "deassign" LHS          ";"                { Force False $2 Nil }
   | "force"    LHS "=" Expr ";"                { Force True  $2  $4 }
   | "release"  LHS          ";"                { Force True  $2 Nil }
+  | "wait" "(" Expr ")" Stmt                   { Wait $3 $5 }
 
 OptDelayOrEvent :: { Maybe Timing }
   : DelayOrEvent { Just $1 }

test/basic/wait.sv

+module top;
+    reg a, b, c, d;
+
+    initial begin
+        fork
+            #1 a = 1;
+            wait(a);
+        join
+        $display("a %0d", $time);
+    end
+
+    initial begin
+        fork
+            b = 1;
+            #1 wait(b);
+        join
+        $display("b %0d", $time);
+    end
+
+    initial begin
+        fork
+            #1 wait(c) $display("c done %0d", $time);
+            #1 wait(d) $display("d done %0d", $time);
+            begin
+                #1 c = 1;
+                #1 d = 1;
+            end
+        join
+        $display("cd %0d", $time);
+    end
+endmodule