preliminary support for enums

Convert/PackedArrayFlatten.hs

@@ -120,6 +120,7 @@ typeDims (Reg     r) = (Reg    , r)
 typeDims (Wire     r) = (Wire    , r)
 typeDims (Logic    r) = (Logic   , r)
 typeDims (Alias  t r) = (Alias  t, r)
+typeDims (Enum t v r) = (Enum t v, r)
 
 prefix :: Identifier -> Identifier
 prefix ident = "_sv2v_" ++ ident
@@ -168,6 +169,7 @@ rewriteExpr dimMap = rewriteExpr'
         rewriteExpr' (BinOp      o e1 e2) = BinOp o (re e1) (re e2)
         rewriteExpr' (Mux        e1 e2 e3) = Mux (re e1) (re e2) (re e3)
         rewriteExpr' (Bit        e n) = Bit (re e) n
+        rewriteExpr' (Cast       t e) = Cast t (re e)
 
 flattenRanges :: [Range] -> [Range]
 flattenRanges rs =

Convert/Typedef.hs

@@ -7,6 +7,8 @@
 -- TODO: Right now we only support typedefs for module data items. Function
 -- parameters, block items, etc., probably support typedefs, too.
 
+-- TODO FIXME XXX: `Cast` contains a type, which we'll need to resolve/convert?
+
 module Convert.Typedef (convert) where
 
 import Data.Maybe
@@ -38,11 +40,14 @@ resolveType :: Types -> Type -> Type
 resolveType _ (Reg   rs) = Reg   rs
 resolveType _ (Wire  rs) = Wire  rs
 resolveType _ (Logic rs) = Logic rs
+resolveType _ (Enum Nothing vals rs) = Enum Nothing vals rs
+resolveType types (Enum (Just t) vals rs) = Enum (Just $ resolveType types t) vals rs
 resolveType types (Alias st rs1) =
     case resolveType types $ types Map.! st of
         (Reg      rs2) -> Reg      $ rs2 ++ rs1
         (Wire     rs2) -> Wire     $ rs2 ++ rs1
         (Logic    rs2) -> Logic    $ rs2 ++ rs1
+        (Enum t v rs2) -> Enum t v $ rs2 ++ rs1
         (Alias    _ _) -> error $ "resolveType invariant failed on " ++ st
 
 convertModuleItem :: Types -> ModuleItem -> ModuleItem

Language/SystemVerilog/AST.hs

@@ -77,6 +77,7 @@ data Type
   | Wire  [Range]
   | Logic [Range]
   | Alias String [Range]
+  | Enum (Maybe Type) [(Identifier, Maybe Expr)] [Range]
   deriving Eq
 
 instance Show Type where
@@ -84,6 +85,13 @@ instance Show Type where
   show (Wire    r) = "wire"  ++ (showRanges r)
   show (Logic   r) = "logic" ++ (showRanges r)
   show (Alias t r) = t ++ (showRanges r)
+  show (Enum mt vals r) = printf "enum %s{%s}%s" tStr (commas $ map showVal vals) (showRanges r)
+    where
+      tStr = case mt of
+        Nothing -> ""
+        Just t -> (show t) ++ " "
+      showVal :: (Identifier, Maybe Expr) -> String
+      showVal (x, e) = x ++ (showAssignment e)
 
 data ModuleItem
   = Comment    String
@@ -207,6 +215,7 @@ data Expr
   | BinOp      BinOp Expr Expr
   | Mux        Expr Expr Expr
   | Bit        Expr Int
+  | Cast       Type Expr
   deriving Eq
 
 data UniOp
@@ -295,6 +304,7 @@ instance Show Expr where
     BinOp      a b c    -> printf "(%s %s %s)" (show b) (show a) (show c)
     Mux        a b c    -> printf "(%s ? %s : %s)" (show a) (show b) (show c)
     Bit        a b      -> printf "(%s [%d])" (show a) b
+    Cast       a b      -> printf "%s'(%s)" (show a) (show b)
 
 data LHS
   = LHS       Identifier

Language/SystemVerilog/Parser/Lex.x

@@ -68,6 +68,7 @@ tokens :-
   "endmodule"        { tok KW_endmodule  }
   "endfunction"      { tok KW_endfunction}
   "endgenerate"      { tok KW_endgenerate}
+  "enum"             { tok KW_enum       }
   "function"         { tok KW_function   }
   "for"              { tok KW_for        }
   "generate"         { tok KW_generate   }

Language/SystemVerilog/Parser/Parse.y

@@ -33,6 +33,7 @@ import Language.SystemVerilog.Parser.Tokens
 "endfunction"      { Token KW_endfunction _ _ }
 "endgenerate"      { Token KW_endgenerate _ _ }
 "endmodule"        { Token KW_endmodule  _ _ }
+"enum"             { Token KW_enum       _ _ }
 "function"         { Token KW_function   _ _ }
 "for"              { Token KW_for        _ _ }
 "generate"         { Token KW_generate   _ _ }
@@ -178,10 +179,13 @@ Description :: { Description }
 Typedef :: { Description }
   : "typedef" Type Identifier ";" { Typedef $2 $3 }
 
-Type :: { Type }
+TypeNonAlias :: { Type }
   : "wire"  Dimensions { Wire  $2 }
   | "reg"   Dimensions { Reg   $2 }
   | "logic" Dimensions { Logic $2 }
+  | "enum" opt(Type) "{" VariablePortIdentifiers "}" Dimensions { Enum $2 $4 $6 }
+Type :: { Type }
+  : TypeNonAlias          { $1 }
   | Identifier Dimensions { Alias $1 $2 }
 
 Module :: { Description }
@@ -243,9 +247,8 @@ ModuleItem :: { [ModuleItem] }
   : PortDecl(";")                                        { $1 }
   -- TODO: Allowing Ranges on aliases creates conflicts
   | Identifier                    VariableIdentifiers ";" { map (uncurry $ LocalNet (Alias $1 [])) $2 }
-  | "wire"  Dimensions VariableIdentifiers ";"           { map (uncurry $ LocalNet $ Wire  $2) $3 }
-  | "reg"   Dimensions VariableIdentifiers ";"           { map (uncurry $ LocalNet $ Reg   $2) $3 }
-  | "logic" Dimensions VariableIdentifiers ";"           { map (uncurry $ LocalNet $ Logic $2) $3 }
+  | Identifier DimensionsNonEmpty VariableIdentifiers ";" { map (uncurry $ LocalNet (Alias $1 $2)) $3 }
+  | TypeNonAlias                  VariableIdentifiers ";" { map (uncurry $ LocalNet $1) $2 }
   | ParameterDeclaration                                 { map MIParameter  $1 }
   | LocalparamDeclaration                                { map MILocalparam $1 }
   | IntegerDeclaration                                   { map MIIntegerV   $1 }
@@ -473,6 +476,7 @@ Expr :: { Expr }
 | "^"  Expr %prec RedOps      { UniOp RedXor  $2 }
 | "~^" Expr %prec RedOps      { UniOp RedXnor $2 }
 | "^~" Expr %prec RedOps      { UniOp RedXnor $2 }
+| Type "'" "(" Expr ")"       { Cast $1 $4 }
 
 GenItemOrNull :: { GenItem }
   : GenItem { $1 }