support for edge event

CHANGELOG.md

@@ -5,6 +5,7 @@
 * Added support for excluding the conversion of unbased unsized literals (e.g.,
   `'1`, `'x`) via `--exclude UnbasedUniszed`
 * Added support for enumerated type ranges (e.g., `enum { X[3:5] }`)
+* Added support for the SystemVerilog `edge` event
 * Added support for passing through DPI imports and exports
 * Added support for passing through functions with output ports
 

src/Convert.hs

@@ -41,6 +41,7 @@ import qualified Convert.ParamType
 import qualified Convert.PortDecl
 import qualified Convert.RemoveComments
 import qualified Convert.ResolveBindings
+import qualified Convert.SenseEdge
 import qualified Convert.Simplify
 import qualified Convert.Stream
 import qualified Convert.StringParam
@@ -101,6 +102,7 @@ initialPhases selectExclude =
     , Convert.Jump.convert
     , Convert.KWArgs.convert
     , Convert.Unique.convert
+    , Convert.SenseEdge.convert
     , Convert.LogOp.convert
     , Convert.EmptyArgs.convert
     , Convert.Foreach.convert

src/Convert/SenseEdge.hs

+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Conversion for `edge` sensitivity
+ -
+ - IEEE 1800-2017 Section 9.4.2 defines `edge` as either `posedge` or `negedge`.
+ - This does not convert senses in assertions as they are likely either removed
+ - or fully supported downstream.
+ -}
+
+module Convert.SenseEdge (convert) where
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: [AST] -> [AST]
+convert =
+    map $ traverseDescriptions $ traverseModuleItems $ traverseStmts $
+        traverseNestedStmts convertStmt
+
+convertStmt :: Stmt -> Stmt
+convertStmt (Asgn op (Just timing) lhs expr) =
+    Asgn op (Just $ convertTiming timing) lhs expr
+convertStmt (Timing timing stmt) =
+    Timing (convertTiming timing) stmt
+convertStmt other = other
+
+convertTiming :: Timing -> Timing
+convertTiming (Event sense) = Event $ convertSense sense
+convertTiming other = other
+
+convertSense :: Sense -> Sense
+convertSense (SenseOr s1 s2) =
+    SenseOr (convertSense s1) (convertSense s2)
+convertSense (SenseEdge lhs) =
+    SenseOr (SensePosedge lhs) (SenseNegedge lhs)
+convertSense other = other

src/Convert/Traverse.hs

@@ -386,6 +386,7 @@ traverseStmtLHSsM mapper = stmtMapper
         senseMapper (Sense        lhs) = fullMapper lhs >>= return . Sense
         senseMapper (SensePosedge lhs) = fullMapper lhs >>= return . SensePosedge
         senseMapper (SenseNegedge lhs) = fullMapper lhs >>= return . SenseNegedge
+        senseMapper (SenseEdge    lhs) = fullMapper lhs >>= return . SenseEdge
         senseMapper (SenseOr    s1 s2) = do
             s1' <- senseMapper s1
             s2' <- senseMapper s2

src/Language/SystemVerilog/AST/Stmt.hs

@@ -175,6 +175,7 @@ data Sense
     | SenseOr      Sense Sense
     | SensePosedge LHS
     | SenseNegedge LHS
+    | SenseEdge    LHS
     | SenseStar
     deriving Eq
 
@@ -183,6 +184,7 @@ instance Show Sense where
     show (SenseOr      a b) = printf "%s or %s" (show a) (show b)
     show (SensePosedge a  ) = printf "posedge %s" (show a)
     show (SenseNegedge a  ) = printf "negedge %s" (show a)
+    show (SenseEdge    a  ) = printf "edge %s" (show a)
     show (SenseStar       ) = "*"
 
 data ActionBlock

src/Language/SystemVerilog/Parser/Parse.y

@@ -1234,10 +1234,12 @@ Senses :: { Sense }
 Sense :: { Sense }
   : "(" Sense ")"         {              $2 }
   |           LHS         { Sense        $1 }
-  | "posedge"     LHS     { SensePosedge $2 }
-  | "negedge"     LHS     { SenseNegedge $2 }
-  | "posedge" "(" LHS ")" { SensePosedge $3 }
-  | "negedge" "(" LHS ")" { SenseNegedge $3 }
+  | "posedge" LHSOptParen { SensePosedge $2 }
+  | "negedge" LHSOptParen { SenseNegedge $2 }
+  | "edge"    LHSOptParen { SenseEdge    $2 }
+LHSOptParen :: { LHS }
+  :     LHS     { $1 }
+  | "(" LHS ")" { $2 }
 
 CaseKW :: { CaseKW }
   : "case"  { CaseN }

sv2v.cabal

@@ -94,6 +94,7 @@ executable sv2v
     Convert.RemoveComments
     Convert.ResolveBindings
     Convert.Scoper
+    Convert.SenseEdge
     Convert.Simplify
     Convert.Stream
     Convert.StringParam

test/core/edge.sv

+module mod(input clk);
+    always @(posedge clk)
+        $display($time, "posedge");
+    always @(negedge clk)
+        $display($time, "negedge");
+    always @(edge clk)
+        $display($time, "edge");
+endmodule

test/core/edge.v

+module mod(input clk);
+    always @(posedge clk)
+        $display($time, "posedge");
+    always @(negedge clk)
+        $display($time, "negedge");
+    always @(posedge clk or negedge clk)
+        $display($time, "edge");
+endmodule

test/core/edge_tb.v

+module top;
+    reg clk;
+    initial begin
+        clk = 0;
+        repeat (10)
+            #5 clk = ~clk;
+    end
+    mod m(clk);
+endmodule