Commit e4adf6a7 by Zachary Snow

apply reordering in generate blocks

parent 8c967ea9
...@@ -15,7 +15,7 @@ convert :: [AST] -> [AST] ...@@ -15,7 +15,7 @@ convert :: [AST] -> [AST]
convert = convert =
map $ traverseDescriptions $ traverseModuleItems $ map $ traverseDescriptions $ traverseModuleItems $
( traverseStmts convertStmt ( traverseStmts convertStmt
. traverseGenItems convertGenItem . traverseGenItems (traverseNestedGenItems convertGenItem)
) )
convertGenItem :: GenItem -> GenItem convertGenItem :: GenItem -> GenItem
......
...@@ -407,13 +407,27 @@ convertDescription _ other = other ...@@ -407,13 +407,27 @@ convertDescription _ other = other
-- attempt to fix simple declaration order issues -- attempt to fix simple declaration order issues
reorderItems :: [ModuleItem] -> [ModuleItem] reorderItems :: [ModuleItem] -> [ModuleItem]
reorderItems items = reorderItems items =
addItems localPIs Set.empty (map addUsedPIs items) addItems localPIs Set.empty $ map addUsedPIs $
map (traverseGenItems $ traverseNestedGenItems reorderGenItem) items
where where
localPIs = Map.fromList $ concat $ mapMaybe toPIElem items localPIs = Map.fromList $ concat $ mapMaybe toPIElem items
toPIElem :: ModuleItem -> Maybe [(Identifier, PackageItem)] toPIElem :: ModuleItem -> Maybe [(Identifier, PackageItem)]
toPIElem (MIPackageItem item) = Just $ map (, item) (piNames item) toPIElem (MIPackageItem item) = Just $ map (, item) (piNames item)
toPIElem _ = Nothing toPIElem _ = Nothing
-- attempt to declaration order issues within generate blocks
reorderGenItem :: GenItem -> GenItem
reorderGenItem (GenBlock name genItems) =
GenBlock name $ map unwrap $ reorderItems $ map wrap genItems
where
wrap :: GenItem -> ModuleItem
wrap (GenModuleItem item) = item
wrap item = Generate [item]
unwrap :: ModuleItem -> GenItem
unwrap (Generate [item]) = item
unwrap item = GenModuleItem item
reorderGenItem item = item
-- iteratively inserts missing package items exactly where they are needed -- iteratively inserts missing package items exactly where they are needed
addItems :: PIs -> Idents -> [(ModuleItem, Idents)] -> [ModuleItem] addItems :: PIs -> Idents -> [(ModuleItem, Idents)] -> [ModuleItem]
addItems pis existingPIs ((item, usedPIs) : items) = addItems pis existingPIs ((item, usedPIs) : items) =
...@@ -523,7 +537,6 @@ traverseStmtIdentsM identMapper = fullMapper ...@@ -523,7 +537,6 @@ traverseStmtIdentsM identMapper = fullMapper
fullMapper = stmtMapper fullMapper = stmtMapper
>=> traverseStmtExprsM (traverseExprIdentsM identMapper) >=> traverseStmtExprsM (traverseExprIdentsM identMapper)
>=> traverseStmtLHSsM (traverseLHSIdentsM identMapper) >=> traverseStmtLHSsM (traverseLHSIdentsM identMapper)
>=> traverseSinglyNestedStmtsM fullMapper
stmtMapper (Subroutine (Ident x) args) = stmtMapper (Subroutine (Ident x) args) =
identMapper x >>= \x' -> return $ Subroutine (Ident x') args identMapper x >>= \x' -> return $ Subroutine (Ident x') args
stmtMapper other = return other stmtMapper other = return other
......
...@@ -978,9 +978,8 @@ collectTypesM = collectTypesM' IncludeParamTypes ...@@ -978,9 +978,8 @@ collectTypesM = collectTypesM' IncludeParamTypes
traverseGenItemsM :: Monad m => MapperM m GenItem -> MapperM m ModuleItem traverseGenItemsM :: Monad m => MapperM m GenItem -> MapperM m ModuleItem
traverseGenItemsM mapper = moduleItemMapper traverseGenItemsM mapper = moduleItemMapper
where where
fullMapper = traverseNestedGenItemsM mapper
moduleItemMapper (Generate genItems) = moduleItemMapper (Generate genItems) =
mapM fullMapper genItems >>= return . Generate mapM mapper genItems >>= return . Generate
moduleItemMapper other = return other moduleItemMapper other = return other
traverseGenItems :: Mapper GenItem -> Mapper ModuleItem traverseGenItems :: Mapper GenItem -> Mapper ModuleItem
......
...@@ -2,4 +2,15 @@ module top; ...@@ -2,4 +2,15 @@ module top;
assign arr[0][0] = 1; assign arr[0][0] = 1;
logic [1:0][2:0] arr; logic [1:0][2:0] arr;
initial $display("%b", arr); initial $display("%b", arr);
parameter YES = 1;
if (YES) begin : blk
assign brr[0][0] = 1;
logic [2:0][3:0] brr;
initial $display("%b", brr);
if (YES) begin : blk2
assign crr[0][0] = 1;
logic [3:0][4:0] crr;
initial $display("%b", crr);
end
end
endmodule endmodule
...@@ -2,4 +2,17 @@ module top; ...@@ -2,4 +2,17 @@ module top;
wire [5:0] arr; wire [5:0] arr;
assign arr[0] = 1; assign arr[0] = 1;
initial $display("%b", arr); initial $display("%b", arr);
parameter YES = 1;
generate
if (YES) begin : blk
wire [11:0] brr;
assign brr[0] = 1;
initial $display("%b", brr);
if (YES) begin : blk2
assign crr[0] = 1;
wire [19:0] crr;
initial $display("%b", crr);
end
end
endgenerate
endmodule endmodule
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