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lvzhengyang
sv2v
Commits
e006e36d
Commit
e006e36d
authored
Mar 07, 2019
by
Zachary Snow
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preliminary support for tasks
parent
0f4a60be
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5 changed files
with
27 additions
and
3 deletions
+27
-3
src/Convert/Traverse.hs
+12
-0
src/Language/SystemVerilog/AST.hs
+5
-0
src/Language/SystemVerilog/Parser/Lex.x
+2
-0
src/Language/SystemVerilog/Parser/Parse.y
+6
-3
src/Language/SystemVerilog/Parser/ParseDecl.hs
+2
-0
No files found.
src/Convert/Traverse.hs
View file @
e006e36d
...
@@ -110,6 +110,9 @@ traverseStmtsM mapper = moduleItemMapper
...
@@ -110,6 +110,9 @@ traverseStmtsM mapper = moduleItemMapper
moduleItemMapper
(
MIPackageItem
(
Function
lifetime
ret
name
decls
stmts
))
=
do
moduleItemMapper
(
MIPackageItem
(
Function
lifetime
ret
name
decls
stmts
))
=
do
stmts'
<-
mapM
fullMapper
stmts
stmts'
<-
mapM
fullMapper
stmts
return
$
MIPackageItem
$
Function
lifetime
ret
name
decls
stmts'
return
$
MIPackageItem
$
Function
lifetime
ret
name
decls
stmts'
moduleItemMapper
(
MIPackageItem
(
Task
lifetime
name
decls
stmts
))
=
do
stmts'
<-
mapM
fullMapper
stmts
return
$
MIPackageItem
$
Task
lifetime
name
decls
stmts'
moduleItemMapper
(
Initial
stmt
)
=
moduleItemMapper
(
Initial
stmt
)
=
fullMapper
stmt
>>=
return
.
Initial
fullMapper
stmt
>>=
return
.
Initial
moduleItemMapper
other
=
return
$
other
moduleItemMapper
other
=
return
$
other
...
@@ -298,6 +301,10 @@ traverseExprsM mapper = moduleItemMapper
...
@@ -298,6 +301,10 @@ traverseExprsM mapper = moduleItemMapper
decls'
<-
mapM
declMapper
decls
decls'
<-
mapM
declMapper
decls
stmts'
<-
mapM
stmtMapper
stmts
stmts'
<-
mapM
stmtMapper
stmts
return
$
MIPackageItem
$
Function
lifetime
ret
f
decls'
stmts'
return
$
MIPackageItem
$
Function
lifetime
ret
f
decls'
stmts'
moduleItemMapper
(
MIPackageItem
(
Task
lifetime
f
decls
stmts
))
=
do
decls'
<-
mapM
declMapper
decls
stmts'
<-
mapM
stmtMapper
stmts
return
$
MIPackageItem
$
Task
lifetime
f
decls'
stmts'
moduleItemMapper
(
Instance
m
params
x
ml
)
=
do
moduleItemMapper
(
Instance
m
params
x
ml
)
=
do
if
ml
==
Nothing
if
ml
==
Nothing
then
return
$
Instance
m
params
x
Nothing
then
return
$
Instance
m
params
x
Nothing
...
@@ -357,6 +364,9 @@ traverseDeclsM mapper item = do
...
@@ -357,6 +364,9 @@ traverseDeclsM mapper item = do
miMapperA
(
MIPackageItem
(
Function
l
t
x
decls
s
))
=
do
miMapperA
(
MIPackageItem
(
Function
l
t
x
decls
s
))
=
do
decls'
<-
mapM
mapper
decls
decls'
<-
mapM
mapper
decls
return
$
MIPackageItem
$
Function
l
t
x
decls'
s
return
$
MIPackageItem
$
Function
l
t
x
decls'
s
miMapperA
(
MIPackageItem
(
Task
l
x
decls
s
))
=
do
decls'
<-
mapM
mapper
decls
return
$
MIPackageItem
$
Task
l
x
decls'
s
miMapperA
other
=
return
other
miMapperA
other
=
return
other
miMapperB
(
Block
(
Just
(
name
,
decls
))
stmts
)
=
do
miMapperB
(
Block
(
Just
(
name
,
decls
))
stmts
)
=
do
decls'
<-
mapM
mapper
decls
decls'
<-
mapM
mapper
decls
...
@@ -400,6 +410,8 @@ traverseTypesM mapper item =
...
@@ -400,6 +410,8 @@ traverseTypesM mapper item =
fullMapper
t
>>=
\
t'
->
return
$
Variable
d
t'
x
a
me
fullMapper
t
>>=
\
t'
->
return
$
Variable
d
t'
x
a
me
miMapper
(
MIPackageItem
(
Function
l
t
x
d
s
))
=
miMapper
(
MIPackageItem
(
Function
l
t
x
d
s
))
=
fullMapper
t
>>=
\
t'
->
return
$
MIPackageItem
$
Function
l
t'
x
d
s
fullMapper
t
>>=
\
t'
->
return
$
MIPackageItem
$
Function
l
t'
x
d
s
miMapper
(
MIPackageItem
(
other
@
(
Task
_
_
_
_
)))
=
return
$
MIPackageItem
other
miMapper
other
=
return
other
miMapper
other
=
return
other
traverseTypes
::
Mapper
Type
->
Mapper
ModuleItem
traverseTypes
::
Mapper
Type
->
Mapper
ModuleItem
...
...
src/Language/SystemVerilog/AST.hs
View file @
e006e36d
...
@@ -53,6 +53,7 @@ type AST = [Description]
...
@@ -53,6 +53,7 @@ type AST = [Description]
data
PackageItem
data
PackageItem
=
Typedef
Type
Identifier
=
Typedef
Type
Identifier
|
Function
(
Maybe
Lifetime
)
Type
Identifier
[
Decl
]
[
Stmt
]
|
Function
(
Maybe
Lifetime
)
Type
Identifier
[
Decl
]
[
Stmt
]
|
Task
(
Maybe
Lifetime
)
Identifier
[
Decl
]
[
Stmt
]
|
Comment
String
|
Comment
String
deriving
Eq
deriving
Eq
...
@@ -62,6 +63,10 @@ instance Show PackageItem where
...
@@ -62,6 +63,10 @@ instance Show PackageItem where
printf
"function %s%s%s;
\n
%s
\n
%s
\n
endfunction"
printf
"function %s%s%s;
\n
%s
\n
%s
\n
endfunction"
(
showLifetime
ml
)
(
showPad
t
)
x
(
indent
$
show
i
)
(
showLifetime
ml
)
(
showPad
t
)
x
(
indent
$
show
i
)
(
indent
$
unlines'
$
map
show
b
)
(
indent
$
unlines'
$
map
show
b
)
show
(
Task
ml
x
i
b
)
=
printf
"task %s%s;
\n
%s
\n
%s
\n
endtask"
(
showLifetime
ml
)
x
(
indent
$
show
i
)
(
indent
$
unlines'
$
map
show
b
)
show
(
Comment
c
)
=
"// "
++
c
show
(
Comment
c
)
=
"// "
++
c
data
Description
data
Description
...
...
src/Language/SystemVerilog/Parser/Lex.x
View file @
e006e36d
...
@@ -71,6 +71,7 @@ tokens :-
...
@@ -71,6 +71,7 @@ tokens :-
"endgenerate" { tok KW_endgenerate }
"endgenerate" { tok KW_endgenerate }
"endinterface" { tok KW_endinterface }
"endinterface" { tok KW_endinterface }
"endmodule" { tok KW_endmodule }
"endmodule" { tok KW_endmodule }
"endtask" { tok KW_endtask }
"enum" { tok KW_enum }
"enum" { tok KW_enum }
"for" { tok KW_for }
"for" { tok KW_for }
"forever" { tok KW_forever }
"forever" { tok KW_forever }
...
@@ -98,6 +99,7 @@ tokens :-
...
@@ -98,6 +99,7 @@ tokens :-
"return" { tok KW_return }
"return" { tok KW_return }
"static" { tok KW_static }
"static" { tok KW_static }
"struct" { tok KW_struct }
"struct" { tok KW_struct }
"task" { tok KW_task }
"typedef" { tok KW_typedef }
"typedef" { tok KW_typedef }
"unique" { tok KW_unique }
"unique" { tok KW_unique }
"while" { tok KW_while }
"while" { tok KW_while }
...
...
src/Language/SystemVerilog/Parser/Parse.y
View file @
e006e36d
...
@@ -36,6 +36,7 @@ import Language.SystemVerilog.Parser.Tokens
...
@@ -36,6 +36,7 @@ import Language.SystemVerilog.Parser.Tokens
"endgenerate" { Token KW_endgenerate _ _ }
"endgenerate" { Token KW_endgenerate _ _ }
"endinterface" { Token KW_endinterface _ _ }
"endinterface" { Token KW_endinterface _ _ }
"endmodule" { Token KW_endmodule _ _ }
"endmodule" { Token KW_endmodule _ _ }
"endtask" { Token KW_endtask _ _ }
"enum" { Token KW_enum _ _ }
"enum" { Token KW_enum _ _ }
"for" { Token KW_for _ _ }
"for" { Token KW_for _ _ }
"forever" { Token KW_forever _ _ }
"forever" { Token KW_forever _ _ }
...
@@ -63,6 +64,7 @@ import Language.SystemVerilog.Parser.Tokens
...
@@ -63,6 +64,7 @@ import Language.SystemVerilog.Parser.Tokens
"return" { Token KW_return _ _ }
"return" { Token KW_return _ _ }
"static" { Token KW_static _ _ }
"static" { Token KW_static _ _ }
"struct" { Token KW_struct _ _ }
"struct" { Token KW_struct _ _ }
"task" { Token KW_task _ _ }
"typedef" { Token KW_typedef _ _ }
"typedef" { Token KW_typedef _ _ }
"unique" { Token KW_unique _ _ }
"unique" { Token KW_unique _ _ }
"while" { Token KW_while _ _ }
"while" { Token KW_while _ _ }
...
@@ -324,7 +326,8 @@ ModuleItem :: { [ModuleItem] }
...
@@ -324,7 +326,8 @@ ModuleItem :: { [ModuleItem] }
PackageItem :: { PackageItem }
PackageItem :: { PackageItem }
: "typedef" Type Identifier ";" { Typedef $2 $3 }
: "typedef" Type Identifier ";" { Typedef $2 $3 }
| "function" opt(Lifetime) FuncRetAndName FunctionItems DeclsAndStmts "endfunction" opt(Tag) { Function $2 (fst $3) (snd $3) (map defaultFuncInput $ $4 ++ fst $5) (snd $5) }
| "function" opt(Lifetime) FuncRetAndName TFItems DeclsAndStmts "endfunction" opt(Tag) { Function $2 (fst $3) (snd $3) (map defaultFuncInput $ (map makeInput $4) ++ fst $5) (snd $5) }
| "task" opt(Lifetime) Identifier TFItems DeclsAndStmts "endtask" opt(Tag) { Task $2 $3 (map defaultFuncInput $ $4 ++ fst $5) (snd $5) }
FuncRetAndName :: { (Type, Identifier) }
FuncRetAndName :: { (Type, Identifier) }
: {- empty -} Identifier { (Implicit [], $1) }
: {- empty -} Identifier { (Implicit [], $1) }
...
@@ -345,8 +348,8 @@ ModuleInstantiation :: { (Identifier, Maybe [PortBinding]) }
...
@@ -345,8 +348,8 @@ ModuleInstantiation :: { (Identifier, Maybe [PortBinding]) }
: Identifier "(" Bindings ")" { ($1, Just $3) }
: Identifier "(" Bindings ")" { ($1, Just $3) }
| Identifier "(" ".*" ")" { ($1, Nothing) }
| Identifier "(" ".*" ")" { ($1, Nothing) }
Function
Items :: { [Decl] }
TF
Items :: { [Decl] }
: "(" DeclTokens(")") ";" {
map makeInput $
parseDTsAsDecls $2 }
: "(" DeclTokens(")") ";" { parseDTsAsDecls $2 }
| ";" { [] }
| ";" { [] }
ParamType :: { Type }
ParamType :: { Type }
...
...
src/Language/SystemVerilog/Parser/ParseDecl.hs
View file @
e006e36d
...
@@ -183,6 +183,8 @@ finalize (dir, typ, trips) =
...
@@ -183,6 +183,8 @@ finalize (dir, typ, trips) =
-- internal; entrypoint of the critical portion of our parser
-- internal; entrypoint of the critical portion of our parser
parseDTsAsComponents
::
[
DeclToken
]
->
[
Component
]
parseDTsAsComponents
::
[
DeclToken
]
->
[
Component
]
parseDTsAsComponents
[]
=
[]
parseDTsAsComponents
[]
=
[]
parseDTsAsComponents
[
DTDir
dir
,
DTIdent
ident
]
=
[(
dir
,
Implicit
[]
,
[(
ident
,
[]
,
Nothing
)])]
parseDTsAsComponents
l0
=
parseDTsAsComponents
l0
=
component
:
parseDTsAsComponents
l4
component
:
parseDTsAsComponents
l4
where
where
...
...
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